Excluding the reserved interrupts fixes the task priorities. I also
considered refactoring `rtic/src/export/riscv_esp32c6.rs` to use esp-hal
instead of esp32c6 directly as it has code to do all the pointer
wrangling itself, but decided against it for now. It might be nice to
refactor both esp implentations to use it though.
* Update `rtic` package to use latest version of `esp32c3` dependency
* Update `rtic-macros` ESP32-C3 bindings to reflect changes in HAL
* Update the ESP32-C3 examples to use latest versions of all dependencies
* Update changelogs
* adjust expected qemu output, add compile-time checks
* remove runtime checks, this is checked at compile time
* fix expected qemu output
* Clean up interrupt enable code a bit
* Update `rtic-monotonic` to use the latest PAC for ESP32-C3
* Update `CHANGELOG.md` for `rtic-monotonic`
* ci: esp32c3: Format runner.sh
* ci: esp32c3: Default to silent boot
export DEBUGGING while running to get verbose boot
env DEBUGGING=1 cargo xtask ...
* ci: esp32c3: Update expected example output
---------
Co-authored-by: onsdagens <pawdzi-7@student.ltu.se>
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* Rebase to master
* using interrupt_mod
* bug fixes
* fix other backends
* Add changelog
* forgot about rtic-macros
* backend-specific configuration
* core peripherals optional over macro argument
* pre_init_preprocessing binding
* CI for RISC-V (WIP)
* separation of concerns
* add targets for RISC-V examples
* remove qemu feature
* prepare examples folder
* move examples all together
* move ci out of examples
* minor changes
* add cortex-m
* new xtask: proof of concept
* fix build.yml
* feature typo
* clean rtic examples
* reproduce weird issue
* remove unsafe code in user app
* update dependencies
* allow builds on riscv32imc
* let's fix QEMU
* Update .github/workflows/build.yml
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* New build.rs
* removing test features
* adapt ui test to new version of clippy
* add more examples to RISC-V backend
* proper configuration of heapless for riscv32imc
* opt-out examples for riscv32imc
* point to new version of riscv-slic
* adapt new macro bindings
* adapt examples and CI to stable
* fix cortex-m CI
* Review
---------
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* Update syn requirement from 1.0.107 to 2.0.48
Updates the requirements on [syn](https://github.com/dtolnay/syn) to permit the latest version.
- [Release notes](https://github.com/dtolnay/syn/releases)
- [Commits](https://github.com/dtolnay/syn/compare/1.0.107...2.0.48)
---
updated-dependencies:
- dependency-name: syn
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
* rtic-macros: attr.path -> attr.path()
* rtic-macros: tokens -> parse_args()
Fix parsing of InitArgs, IdleArgs, *Args
Including HardwareTaskArgs, SoftwareTaskArgs
* rtic-macros: Rename content to input
As syn2 removes the surrounding parenthesis as
part of parse_args() the distinction between
input and content is redundant
* rtic-macros: Handle removal of Expr::Type
Manually parse local_resources
With type ascription de-RFCd syn2 dropped
Expr::Type
* rtic-macros: Syn upgrade CHANGELOG
* rtic-macro: Retain most old errors as they were
Spans are not equal, but good enough
* rtic-macros: syn2 changed some error messages
Additionally some spans were not retained
with the manual parsing workaround
* rtic-macros: clippy fixes
---------
Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
