Román Cárdenas Rodríguez 4060c3def8 RISC-V support over CLINT (#815) ... * Rebase to master * using interrupt_mod * bug fixes * fix other backends * Add changelog * forgot about rtic-macros * backend-specific configuration * core peripherals optional over macro argument * pre_init_preprocessing binding * CI for RISC-V (WIP) * separation of concerns * add targets for RISC-V examples * remove qemu feature * prepare examples folder * move examples all together * move ci out of examples * minor changes * add cortex-m * new xtask: proof of concept * fix build.yml * feature typo * clean rtic examples * reproduce weird issue * remove unsafe code in user app * update dependencies * allow builds on riscv32imc * let's fix QEMU * Update .github/workflows/build.yml Co-authored-by: Henrik Tjäder <henrik@tjaders.com> * New build.rs * removing test features * adapt ui test to new version of clippy * add more examples to RISC-V backend * proper configuration of heapless for riscv32imc * opt-out examples for riscv32imc * point to new version of riscv-slic * adapt new macro bindings * adapt examples and CI to stable * fix cortex-m CI * Review --------- Co-authored-by: Henrik Tjäder <henrik@tjaders.com>		2024-03-20 20:06:47 +00:00
..
src	RISC-V support over CLINT (#815)	2024-03-20 20:06:47 +00:00
tests	Move rtic macros to repo root, tune xtask	2023-03-01 00:35:13 +01:00
ui	Update syn requirement from 1.0.107 to 2.0.48 (#881)	2024-01-16 07:03:49 +00:00
.gitignore	Move rtic macros to repo root, tune xtask	2023-03-01 00:35:13 +01:00
Cargo.toml	RISC-V support over CLINT (#815)	2024-03-20 20:06:47 +00:00
CHANGELOG.md	RISC-V support over CLINT (#815)	2024-03-20 20:06:47 +00:00