Add mecall backend

examples/hifive1/Cargo.lock

@@ -1,6 +1,6 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
-version = 3
+version = 4
 
 [[package]]
 name = "bare-metal"
@@ -23,7 +23,8 @@ checksum = "790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b"
 [[package]]
 name = "e310x"
 version = "0.12.0"
-source = "git+https://github.com/riscv-rust/e310x.git?branch=ehv1#ddc85fd4a8138c24d8080810469fb354ccb46d2d"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d0edf103c72b301d8a96d1ff0ff252f8def1bd405ab3443e8382615c9b3268c1"
 dependencies = [
  "critical-section",
  "riscv",
@@ -35,11 +36,13 @@ dependencies = [
 [[package]]
 name = "e310x-hal"
 version = "0.12.0"
-source = "git+https://github.com/riscv-rust/e310x.git?branch=ehv1#ddc85fd4a8138c24d8080810469fb354ccb46d2d"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2603680fc5d4ee9d126c59e6a1ddb39171ecfed9a4f4ddd499a60d3d66116bf4"
 dependencies = [
  "e310x",
  "embedded-hal",
  "embedded-hal-nb",
+ "embedded-io",
  "nb",
  "portable-atomic",
  "riscv",
@@ -61,6 +64,12 @@ dependencies = [
  "nb",
 ]
 
+[[package]]
+name = "embedded-io"
+version = "0.6.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "edd0f118536f44f5ccd48bcb8b111bdc3de888b58c74639dfb034a357d0f206d"
+
 [[package]]
 name = "equivalent"
 version = "1.0.1"
@@ -95,8 +104,9 @@ dependencies = [
 
 [[package]]
 name = "hifive1"
-version = "0.14.0"
-source = "git+https://github.com/riscv-rust/e310x.git?branch=ehv1#ddc85fd4a8138c24d8080810469fb354ccb46d2d"
+version = "0.13.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bbaca49e50464e57ab3737a236897296306bc50e1ccca16c18eb990ccbb2f417"
 dependencies = [
  "critical-section",
  "e310x-hal",
@@ -237,8 +247,9 @@ dependencies = [
 
 [[package]]
 name = "riscv-slic"
-version = "0.1.1"
-source = "git+https://github.com/romancardenas/riscv-slic.git?branch=mecall#a4800b26bfa8c1e46567703bed3154b137032023"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3cab62a2a0c21946a4be5ba289b68da75bf9ec899fbfb211fc400e5d21b1f94a"
 dependencies = [
  "critical-section",
  "heapless",
@@ -248,8 +259,9 @@ dependencies = [
 
 [[package]]
 name = "riscv-slic-macros"
-version = "0.1.0"
-source = "git+https://github.com/romancardenas/riscv-slic.git?branch=mecall#a4800b26bfa8c1e46567703bed3154b137032023"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "885639f9aefd03c71dc2c205c6b196af19c63c1fee811c255d36102c712ef008"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -258,7 +270,7 @@ dependencies = [
 
 [[package]]
 name = "rtic"
-version = "2.1.1"
+version = "2.1.2"
 dependencies = [
  "bare-metal",
  "critical-section",
@@ -277,7 +289,7 @@ checksum = "d9369355b04d06a3780ec0f51ea2d225624db777acbc60abd8ca4832da5c1a42"
 
 [[package]]
 name = "rtic-macros"
-version = "2.1.0"
+version = "2.1.2"
 dependencies = [
  "indexmap",
  "proc-macro-error2",

examples/hifive1/Cargo.toml

@@ -11,11 +11,11 @@ edition = "2021"
 [dependencies]
 rtic = { path = "../../rtic" }
 heapless = { version = "0.8.0", features = ["portable-atomic-unsafe-assume-single-core"] }
-hifive1 = { git = "https://github.com/riscv-rust/e310x.git", branch = "ehv1", features = ["board-redv"] }
+hifive1 = { version = "0.13.0", features = ["board-redv"] }
 riscv-rt = {version = "0.13.0", features = ["single-hart"]}
 riscv = "0.12.1"
 semihosting = { version = "0.1", features = ["stdio", "panic-handler"] }
-portable-atomic = { version = "1.9", features = ["unsafe-assume-single-core", "force-amo"] }
+portable-atomic = { version = "1", features = ["unsafe-assume-single-core", "force-amo"] }
 
 [features]
 riscv-clint-backend = ["rtic/riscv-clint-backend"]

rtic-macros/src/codegen/bindings/riscv_slic.rs

@@ -108,10 +108,6 @@ pub fn pre_init_checks(app: &App, _analysis: &SyntaxAnalysis) -> Vec<TokenStream
 pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
     let mut stmts = vec![];
 
-    // First, we reset and disable all the interrupt controllers
-    stmts.push(quote!(rtic::export::clear_interrupts();));
-
-    // Then, we set the corresponding priorities
     let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id));
     for (&p, name) in interrupt_ids.chain(
         app.hardware_tasks
@@ -122,8 +118,7 @@ pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<
             rtic::export::set_priority(slic::SoftwareInterrupt::#name, #p);
         ));
     }
-    // Finally, we activate the interrupts
-    stmts.push(quote!(rtic::export::set_interrupts();));
+
     stmts
 }
 

rtic/CHANGELOG.md

@@ -23,6 +23,9 @@ Example:
 ### Changed
 
 - Updated esp32c3 dependency to v0.27.0
+### Added
+
+- Support for RISC-V targets compatible with `riscv-slic` using machine-level environment call exceptions.
 
 ## [v2.1.2] - 2024-12-06
 

rtic/src/export/slic.rs

@@ -7,16 +7,16 @@ pub use riscv_slic::{lock, pend, run, InterruptNumber};
 compile_error!("Building for the riscv-slic, but no compatible backend selected");
 
 /// USE CASE RE-EXPORTS: needed for SLIC-only
-pub use riscv_slic::{self, clear_interrupts, codegen, set_interrupts, set_priority};
+pub use riscv_slic::{self, codegen, set_priority};
 
 pub mod interrupt {
+    #[inline]
     pub fn disable() {
         riscv_slic::disable();
-        riscv_slic::clear_interrupts();
     }
 
+    #[inline]
     pub unsafe fn enable() {
-        riscv_slic::set_interrupts();
         riscv_slic::enable();
     }
 }