Crate rp2040_pac

source
Expand description

Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.31.5 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

  • pub use self::pll_sys as pll_usb;
  • pub use self::uart0 as uart1;
  • pub use self::spi0 as spi1;
  • pub use self::i2c0 as i2c1;
  • pub use self::pio0 as pio1;

Modules§

  • adc
    Control and data interface to SAR ADC
  • busctrl
    Register block for busfabric control signals and performance counters
  • clocks
    CLOCKS
  • dma
    DMA with separate read and write masters
  • generic
    Common register and bit access and modify traits
  • i2c0
    DW_apb_i2c address block
  • io_bank0
    IO_BANK0
  • io_qspi
    IO_QSPI
  • pads_bank0
    PADS_BANK0
  • pads_qspi
    PADS_QSPI
  • pio0
    Programmable IO block
  • pll_sys
    PLL_SYS
  • ppb
    PPB
  • psm
    PSM
  • pwm
    Simple PWM
  • resets
    RESETS
  • rosc
    ROSC
  • rtc
    Register block to control RTC
  • sio
    Single-cycle IO block
    Provides core-local and inter-core hardware for the two processors, with single-cycle access.
  • spi0
    SPI0
  • syscfg
    Register block for various chip control signals
  • sysinfo
    SYSINFO
  • tbman
    Testbench manager. Allows the programmer to know what platform their software is running on.
  • timer
    Controls time and alarms
    time is a 64 bit value indicating the time in usec since power-on
    timeh is the top 32 bits of time & timel is the bottom 32 bits
    to change time write to timelw before timehw
    to read time read from timelr before timehr
    An alarm is set by setting alarm_enable and writing to the corresponding alarm register
    When an alarm is pending, the corresponding alarm_running signal will be high
    An alarm can be cancelled before it has finished by clearing the alarm_enable
    When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
    To clear the interrupt write a 1 to the corresponding alarm_irq
  • uart0
    UART0
  • usbctrl_dpram
    DPRAM layout for USB device.
  • usbctrl_regs
    USB FS/LS controller device registers
  • vreg_and_chip_reset
    control and status for on-chip voltage regulator and chip level reset subsystem
  • watchdog
    WATCHDOG
  • xip_ctrl
    QSPI flash execute-in-place block
  • xip_ssi
    DW_apb_ssi has the following features:
  • xosc
    Controls the crystal oscillator

Structs§

  • ADC
    Control and data interface to SAR ADC
  • BUSCTRL
    Register block for busfabric control signals and performance counters
  • CBP
    Cache and branch predictor maintenance operations
  • CLOCKS
    CLOCKS
  • CPUID
    CPUID
  • CorePeripherals
    Core peripherals
  • DCB
    Debug Control Block
  • DMA
    DMA with separate read and write masters
  • DWT
    Data Watchpoint and Trace unit
  • FPB
    Flash Patch and Breakpoint unit
  • I2C0
    DW_apb_i2c address block
  • I2C1
    DW_apb_i2c address block
  • IO_BANK0
    IO_BANK0
  • IO_QSPI
    IO_QSPI
  • ITM
    Instrumentation Trace Macrocell
  • MPU
    Memory Protection Unit
  • NVIC
    Nested Vector Interrupt Controller
  • PADS_BANK0
    PADS_BANK0
  • PADS_QSPI
    PADS_QSPI
  • PIO0
    Programmable IO block
  • PIO1
    Programmable IO block
  • PLL_SYS
    PLL_SYS
  • PLL_USB
    PLL_USB
  • PPB
    PPB
  • PSM
    PSM
  • PWM
    Simple PWM
  • Peripherals
    All the peripherals.
  • RESETS
    RESETS
  • ROSC
    ROSC
  • RTC
    Register block to control RTC
  • SCB
    System Control Block
  • SIO
    Single-cycle IO block
    Provides core-local and inter-core hardware for the two processors, with single-cycle access.
  • SPI0
    SPI0
  • SPI1
    SPI1
  • SYSCFG
    Register block for various chip control signals
  • SYSINFO
    SYSINFO
  • SYST
    SysTick: System Timer
  • TBMAN
    Testbench manager. Allows the programmer to know what platform their software is running on.
  • TIMER
    Controls time and alarms
    time is a 64 bit value indicating the time in usec since power-on
    timeh is the top 32 bits of time & timel is the bottom 32 bits
    to change time write to timelw before timehw
    to read time read from timelr before timehr
    An alarm is set by setting alarm_enable and writing to the corresponding alarm register
    When an alarm is pending, the corresponding alarm_running signal will be high
    An alarm can be cancelled before it has finished by clearing the alarm_enable
    When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
    To clear the interrupt write a 1 to the corresponding alarm_irq
  • TPIU
    Trace Port Interface Unit
  • UART0
    UART0
  • UART1
    UART1
  • USBCTRL_DPRAM
    DPRAM layout for USB device.
  • USBCTRL_REGS
    USB FS/LS controller device registers
  • VREG_AND_CHIP_RESET
    control and status for on-chip voltage regulator and chip level reset subsystem
  • WATCHDOG
    WATCHDOG
  • XIP_CTRL
    QSPI flash execute-in-place block
  • XIP_SSI
    DW_apb_ssi has the following features:
  • XOSC
    Controls the crystal oscillator

Enums§

Constants§