Struct SYSCFG

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pub struct SYSCFG { /* private fields */ }

Expand description

Register block for various chip control signals

Implementations§

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impl SYSCFG

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pub const PTR: const RegisterBlock = {0x40004000 as const syscfg::RegisterBlock}

Pointer to the register block

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pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

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pub unsafe fn steal() -> Self

Steal an instance of this peripheral

§Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

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pub fn proc0_nmi_mask(&self) -> &PROC0_NMI_MASK

0x00 - Processor core 0 NMI source mask
Set a bit high to enable NMI from that IRQ

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pub fn proc1_nmi_mask(&self) -> &PROC1_NMI_MASK

0x04 - Processor core 1 NMI source mask
Set a bit high to enable NMI from that IRQ

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pub fn proc_config(&self) -> &PROC_CONFIG

0x08 - Configuration for processors

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pub fn proc_in_sync_bypass(&self) -> &PROC_IN_SYNC_BYPASS

0x0c - For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0…29.

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pub fn proc_in_sync_bypass_hi(&self) -> &PROC_IN_SYNC_BYPASS_HI

0x10 - For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30…35 (the QSPI IOs).

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