rp2040_pac

Module timer

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Expand description

Controls time and alarms
time is a 64 bit value indicating the time in usec since power-on
timeh is the top 32 bits of time & timel is the bottom 32 bits
to change time write to timelw before timehw
to read time read from timelr before timehr
An alarm is set by setting alarm_enable and writing to the corresponding alarm register
When an alarm is pending, the corresponding alarm_running signal will be high
An alarm can be cancelled before it has finished by clearing the alarm_enable
When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
To clear the interrupt write a 1 to the corresponding alarm_irq

Modules§

  • alarm0
    Arm alarm 0, and configure the time it will fire.
    Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
    The alarm will disarm itself once it fires, and can
    be disarmed early using the ARMED status register.
  • alarm1
    Arm alarm 1, and configure the time it will fire.
    Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
    The alarm will disarm itself once it fires, and can
    be disarmed early using the ARMED status register.
  • alarm2
    Arm alarm 2, and configure the time it will fire.
    Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
    The alarm will disarm itself once it fires, and can
    be disarmed early using the ARMED status register.
  • alarm3
    Arm alarm 3, and configure the time it will fire.
    Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
    The alarm will disarm itself once it fires, and can
    be disarmed early using the ARMED status register.
  • armed
    Indicates the armed/disarmed status of each alarm.
    A write to the corresponding ALARMx register arms the alarm.
    Alarms automatically disarm upon firing, but writing ones here
    will disarm immediately without waiting to fire.
  • dbgpause
    Set bits high to enable pause when the corresponding debug ports are active
  • inte
    Interrupt Enable
  • intf
    Interrupt Force
  • intr
    Raw Interrupts
  • ints
    Interrupt status after masking & forcing
  • pause
    Set high to pause the timer
  • timehr
    Read from bits 63:32 of time
    always read timelr before timehr
  • timehw
    Write to bits 63:32 of time
    always write timelw before timehw
  • timelr
    Read from bits 31:0 of time
  • timelw
    Write to bits 31:0 of time
    writes do not get copied to time until timehw is written
  • timerawh
    Raw read from bits 63:32 of time (no side effects)
  • timerawl
    Raw read from bits 31:0 of time (no side effects)

Structs§

Type Aliases§

  • ALARM0
    ALARM0 (rw) register accessor: Arm alarm 0, and configure the time it will fire.
    Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
    The alarm will disarm itself once it fires, and can
    be disarmed early using the ARMED status register.
  • ALARM1
    ALARM1 (rw) register accessor: Arm alarm 1, and configure the time it will fire.
    Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
    The alarm will disarm itself once it fires, and can
    be disarmed early using the ARMED status register.
  • ALARM2
    ALARM2 (rw) register accessor: Arm alarm 2, and configure the time it will fire.
    Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
    The alarm will disarm itself once it fires, and can
    be disarmed early using the ARMED status register.
  • ALARM3
    ALARM3 (rw) register accessor: Arm alarm 3, and configure the time it will fire.
    Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
    The alarm will disarm itself once it fires, and can
    be disarmed early using the ARMED status register.
  • ARMED
    ARMED (rw) register accessor: Indicates the armed/disarmed status of each alarm.
    A write to the corresponding ALARMx register arms the alarm.
    Alarms automatically disarm upon firing, but writing ones here
    will disarm immediately without waiting to fire.
  • DBGPAUSE
    DBGPAUSE (rw) register accessor: Set bits high to enable pause when the corresponding debug ports are active
  • INTE
    INTE (rw) register accessor: Interrupt Enable
  • INTF
    INTF (rw) register accessor: Interrupt Force
  • INTR
    INTR (rw) register accessor: Raw Interrupts
  • INTS
    INTS (r) register accessor: Interrupt status after masking & forcing
  • PAUSE
    PAUSE (rw) register accessor: Set high to pause the timer
  • TIMEHR
    TIMEHR (r) register accessor: Read from bits 63:32 of time
    always read timelr before timehr
  • TIMEHW
    TIMEHW (w) register accessor: Write to bits 63:32 of time
    always write timelw before timehw
  • TIMELR
    TIMELR (r) register accessor: Read from bits 31:0 of time
  • TIMELW
    TIMELW (w) register accessor: Write to bits 31:0 of time
    writes do not get copied to time until timehw is written
  • TIMERAWH
    TIMERAWH (r) register accessor: Raw read from bits 63:32 of time (no side effects)
  • TIMERAWL
    TIMERAWL (r) register accessor: Raw read from bits 31:0 of time (no side effects)