Commit graph

1284 commits

Author SHA1 Message Date
Emil Fresk
35c97b61c1 All examples pass with cargo xtask --target all 2023-03-01 00:33:28 +01:00
Emil Fresk
ceaf3613d3 Update semihosting 2023-03-01 00:33:28 +01:00
Emil Fresk
9a67f00a30 Fix typos 2023-03-01 00:33:28 +01:00
Emil Fresk
cbe5926880 Fix failing UI test 2023-03-01 00:33:27 +01:00
Emil Fresk
584ac7e1b3 Update UI tests, 1 failing that needs fixing 2023-03-01 00:33:27 +01:00
Per Lindgren
9a4f97ca5e more examples 2023-03-01 00:33:24 +01:00
Emil Fresk
5606ba3cf3 Fix locks, basepri writeback error 2023-03-01 00:31:09 +01:00
Per Lindgren
569a761122 examples/multiloc fixed 2023-03-01 00:31:08 +01:00
Emil Fresk
76595b7aed All codegen is now explicit 2023-03-01 00:31:08 +01:00
Per Lindgren
b054e871d4 examples/lock fixed 2023-03-01 00:31:08 +01:00
Per Lindgren
bd20d0d89e examples/locals fixed 2023-03-01 00:31:08 +01:00
Emil Fresk
b9b3ded5e2 Cleanup weird locals in codegen 2023-03-01 00:31:07 +01:00
Per Lindgren
4337e3980c examples/idle-wfi fixed 2023-03-01 00:31:07 +01:00
Per Lindgren
6dc2d29cd9 export Cell removed, expmples updated 2023-03-01 00:31:07 +01:00
Emil Fresk
29228c4723 Main in main codegen 2023-03-01 00:31:07 +01:00
Per Lindgren
9247252cc7 examples/async-task fixup 2023-03-01 00:31:07 +01:00
Emil Fresk
fe2b5cc52e Removed same prio spawn 2023-03-01 00:31:06 +01:00
Emil Fresk
2ad36a6efe Lifetime cleanup 2023-03-01 00:31:06 +01:00
Emil Fresk
511ff675b5 Break codegen for 0-prio async 2023-03-01 00:31:06 +01:00
Emil Fresk
714020a624 Removed Priority, simplified lifetime handling 2023-03-01 00:31:06 +01:00
Emil Fresk
53f3d397e7 More removal 2023-03-01 00:31:05 +01:00
Emil Fresk
3b97531a5c First example builds again 2023-03-01 00:31:05 +01:00
Emil Fresk
858320cbfc Even more cleanup 2023-03-01 00:31:05 +01:00
Emil Fresk
5c3cedf69a Fix fences 2023-03-01 00:31:05 +01:00
Emil Fresk
d27d0fe33f Added software task codegen back 2023-03-01 00:31:05 +01:00
Emil Fresk
f8352122a3 Min codegen 2023-03-01 00:31:04 +01:00
Emil Fresk
d7ed7a8b9f syntax: Remove parse settings struct 2023-03-01 00:31:04 +01:00
Emil Fresk
9829d0ac07 Add check again 2023-03-01 00:31:04 +01:00
Emil Fresk
582c602912 Old xtask test pass 2023-03-01 00:31:01 +01:00
Emil Fresk
7614b96fe4 RTIC v2: Initial commit
rtic-syntax is now part of RTIC repository
2023-03-01 00:29:10 +01:00
bors[bot]
1c5db277e4
Merge #698
698: Release: v1.1.4 r=perlindgren a=AfoHT



Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2023-02-26 16:33:16 +00:00
Henrik Tjäder
e1a0987dc2 Release: v1.1.4 2023-02-26 17:30:10 +01:00
Henrik Tjäder
dbc6964f88 example: pool: Do not print the addr
Unstable and prone to fail CI
2023-02-26 17:30:09 +01:00
bors[bot]
d43c2b64cc
Merge #692
692: CFG: Support HW tasks, cleanup for SW tasks r=korken89 a=AfoHT

Fixes #665

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2023-01-25 20:34:49 +00:00
bors[bot]
a601c6e449
Merge #691
691: Basic cfg support, kind of, for Monotonics r=korken89 a=AfoHT

- Enable at least masking out a Monotonic
- Add example cfg-ing a Monotonic, showing limitations imposed by rtic-syntax
- Update changelog

The use case detailed in linked issue seems to be covered: Fixes #664 

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2023-01-25 20:15:31 +00:00
bors[bot]
a5e18cd529
Merge #686
686: Book: Editorial review r=korken89 a=AfoHT

Continuation of https://github.com/rtic-rs/cortex-m-rtic/pull/618

Better late than never...

A big thanks to `@jvanderk` !

Co-authored-by: John van der Koijk <33966414+jvanderk@users.noreply.github.com>
2023-01-25 20:11:17 +00:00
John van der Koijk
04189cc684 Mostly editorial review. 2023-01-25 21:07:38 +01:00
Henrik Tjäder
800904a105 Handle more cfgs, support cfg on HW/SW tasks 2023-01-22 13:38:43 +01:00
Henrik Tjäder
259be7bbf9 Update changelog 2023-01-22 12:13:49 +01:00
Henrik Tjäder
022330bfcb Add example cfg-ing a Monotonic, showing limitations imposed by rtic-syntax 2023-01-22 12:00:12 +01:00
Henrik Tjäder
be74469ab7 Enable at least masking out a Monotonic
Simplest case working, but leaves a lot to ask
as shown by examples/cfg-monotonic.rs

Current `rtic-syntax` is unable to validate and
handle the `cfgs[]` which limits the usefulness
of this.
2023-01-22 12:00:08 +01:00
bors[bot]
3240fb332a
Merge #690
690: NVIC prio bits must be in the range 1..=255: Handled by logical2hw() r=korken89 a=AfoHT

Fixes #687

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2023-01-22 07:06:30 +00:00
bors[bot]
b0bda53e4e
Merge #689
689: Missing docs: Improve #[doc] generation r=korken89 a=AfoHT

Improve RTIC doc handling

Enable use of

```
#![deny(missing_docs)]
```

and makes the cargo doc output more useful

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2023-01-22 06:57:56 +00:00
Henrik Tjäder
c29e477aa1 Cleanup NVIC prio too high example 2023-01-22 01:19:49 +01:00
Henrik Tjäder
3f74f3b845 Make clippy happy 2023-01-22 00:35:03 +01:00
Henrik Tjäder
7ba23044e6 Update changelog 2023-01-22 00:30:40 +01:00
Henrik Tjäder
f6b0d18e24 Improve RTIC doc handling
Enable use of

```
 #![deny(missing_docs)]
```
2023-01-22 00:26:23 +01:00
Henrik Tjäder
1237f5b33b Heapless 0.7.16 pool!() generates undocumented struct 2023-01-22 00:22:46 +01:00
Henrik Tjäder
40d5ace111 Deny missing_docs for all examples 2023-01-21 23:10:43 +01:00
bors[bot]
86ce8919ae
Merge #680
680: Update cortex-m-semihosting requirement from 0.3.3 to 0.5.0 r=AfoHT a=dependabot[bot]

Updates the requirements on [cortex-m-semihosting](https://github.com/rust-embedded/cortex-m) to permit the latest version.
<details>
<summary>Changelog</summary>
<p><em>Sourced from <a href="https://github.com/rust-embedded/cortex-m/blob/master/CHANGELOG.md">cortex-m-semihosting's changelog</a>.</em></p>
<blockquote>
<h2>[v0.5.0] - 2018-05-11</h2>
<h3>Added</h3>
<ul>
<li>
<p><code>DebugMonitor</code> and <code>SecureFault</code> variants to the <code>Exception</code> enumeration.</p>
</li>
<li>
<p>An optional <code>&quot;inline-asm&quot;</code> feature</p>
</li>
</ul>
<h3>Changed</h3>
<ul>
<li>
<p>[breaking-change] This crate now requires <code>arm-none-eabi-gcc</code> to be installed and available in
<code>$PATH</code> when built with the <code>&quot;inline-asm&quot;</code> feature disabled (which is disabled by default).</p>
</li>
<li>
<p>[breaking-change] The <code>register::{apsr,lr,pc}</code> modules are now behind the <code>&quot;inline-asm&quot;</code> feature.</p>
</li>
<li>
<p>[breaking-change] Some variants of the <code>Exception</code> enumeration are no longer available on
<code>thumbv6m-none-eabi</code>. See API docs for details.</p>
</li>
<li>
<p>[breaking-change] Several of the variants of the <code>Exception</code> enumeration have been renamed to
match the CMSIS specification.</p>
</li>
<li>
<p>[breaking-change] fixed typo in <code>shcrs</code> field of <code>scb::RegisterBlock</code>; it was previously named
<code>shpcrs</code>.</p>
</li>
<li>
<p>[breaking-change] removed several fields from <code>scb::RegisterBlock</code> on ARMv6-M. These registers are
not available on that sub-architecture.</p>
</li>
<li>
<p>[breaking-change] changed the type of <code>scb::RegisterBlock.shpr</code> from <code>RW&lt;u8&gt;</code> to <code>RW&lt;u32&gt;</code> on
ARMv6-M. These registers are word accessible only on that sub-architecture.</p>
</li>
<li>
<p>[breaking-change] renamed the <code>mmar</code> field of <code>scb::RegisterBlock</code> to <code>mmfar</code> to match the CMSIS
name.</p>
</li>
<li>
<p>[breaking-change] removed the <code>iabr</code> field from <code>scb::RegisterBlock</code> on ARMv6-M. This register is
not available on that sub-architecture.</p>
</li>
<li>
<p>[breaking-change] removed several fields from <code>cpuid::RegisterBlock</code> on ARMv6-M. These registers
are not available on that sub-architecture.</p>
</li>
<li>
<p>[breaking-change] The <code>Mutex.new</code> constructor is not a <code>const fn</code> by default. To make it a <code>const fn</code> you have to opt into the <code>&quot;const-fn&quot;</code> feature, which was added in v0.5.1, and switch to a
nightly compiler.</p>
</li>
</ul>
<h3>Removed</h3>
<ul>
<li>[breaking-change] The <code>exception</code> module has been removed. A replacement for <code>Exception::active</code>
can be found in <code>SCB::vect_active</code>. A modified version <code>exception::Exception</code> can be found in the
<code>peripheral::scb</code> module.</li>
</ul>
<h2>[v0.4.3] - 2018-01-25</h2>
<!-- raw HTML omitted -->
</blockquote>
<p>... (truncated)</p>
</details>
<details>
<summary>Commits</summary>
<ul>
<li><a href="a448e9156e"><code>a448e91</code></a> v0.5.0</li>
<li><a href="e3217ad94d"><code>e3217ad</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/88">#88</a></li>
<li><a href="05bbc3b815"><code>05bbc3b</code></a> always list all the peripherals in <code>Peripherals</code></li>
<li><a href="550f94902f"><code>550f949</code></a> fix build for ARMv7E-M + &quot;inline-asm&quot;</li>
<li><a href="7d51707b5f"><code>7d51707</code></a> simplify #[cfg]s</li>
<li><a href="2cd6092848"><code>2cd6092</code></a> ARMv6-M: remove fields that are not available from cpuid::RegisterBlock</li>
<li><a href="17bd0c8e88"><code>17bd0c8</code></a> fix x86_64 tests</li>
<li><a href="c290aa4ee8"><code>c290aa4</code></a> ARMv6-M: remove fields that are not available from NVIC and SCB</li>
<li><a href="716398ce54"><code>716398c</code></a> fix build on ARMv6-M</li>
<li><a href="1d68643772"><code>1d68643</code></a> fix build on ARMv7E-M</li>
<li>Additional commits viewable in <a href="https://github.com/rust-embedded/cortex-m/compare/c-m-sh-v0.3.5...v0.5.0">compare view</a></li>
</ul>
</details>
<br />


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Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2023-01-14 21:02:10 +00:00