86ce8919ae
680: Update cortex-m-semihosting requirement from 0.3.3 to 0.5.0 r=AfoHT a=dependabot[bot] Updates the requirements on [cortex-m-semihosting](https://github.com/rust-embedded/cortex-m) to permit the latest version. <details> <summary>Changelog</summary> <p><em>Sourced from <a href="https://github.com/rust-embedded/cortex-m/blob/master/CHANGELOG.md">cortex-m-semihosting's changelog</a>.</em></p> <blockquote> <h2>[v0.5.0] - 2018-05-11</h2> <h3>Added</h3> <ul> <li> <p><code>DebugMonitor</code> and <code>SecureFault</code> variants to the <code>Exception</code> enumeration.</p> </li> <li> <p>An optional <code>"inline-asm"</code> feature</p> </li> </ul> <h3>Changed</h3> <ul> <li> <p>[breaking-change] This crate now requires <code>arm-none-eabi-gcc</code> to be installed and available in <code>$PATH</code> when built with the <code>"inline-asm"</code> feature disabled (which is disabled by default).</p> </li> <li> <p>[breaking-change] The <code>register::{apsr,lr,pc}</code> modules are now behind the <code>"inline-asm"</code> feature.</p> </li> <li> <p>[breaking-change] Some variants of the <code>Exception</code> enumeration are no longer available on <code>thumbv6m-none-eabi</code>. See API docs for details.</p> </li> <li> <p>[breaking-change] Several of the variants of the <code>Exception</code> enumeration have been renamed to match the CMSIS specification.</p> </li> <li> <p>[breaking-change] fixed typo in <code>shcrs</code> field of <code>scb::RegisterBlock</code>; it was previously named <code>shpcrs</code>.</p> </li> <li> <p>[breaking-change] removed several fields from <code>scb::RegisterBlock</code> on ARMv6-M. These registers are not available on that sub-architecture.</p> </li> <li> <p>[breaking-change] changed the type of <code>scb::RegisterBlock.shpr</code> from <code>RW<u8></code> to <code>RW<u32></code> on ARMv6-M. These registers are word accessible only on that sub-architecture.</p> </li> <li> <p>[breaking-change] renamed the <code>mmar</code> field of <code>scb::RegisterBlock</code> to <code>mmfar</code> to match the CMSIS name.</p> </li> <li> <p>[breaking-change] removed the <code>iabr</code> field from <code>scb::RegisterBlock</code> on ARMv6-M. This register is not available on that sub-architecture.</p> </li> <li> <p>[breaking-change] removed several fields from <code>cpuid::RegisterBlock</code> on ARMv6-M. These registers are not available on that sub-architecture.</p> </li> <li> <p>[breaking-change] The <code>Mutex.new</code> constructor is not a <code>const fn</code> by default. To make it a <code>const fn</code> you have to opt into the <code>"const-fn"</code> feature, which was added in v0.5.1, and switch to a nightly compiler.</p> </li> </ul> <h3>Removed</h3> <ul> <li>[breaking-change] The <code>exception</code> module has been removed. A replacement for <code>Exception::active</code> can be found in <code>SCB::vect_active</code>. A modified version <code>exception::Exception</code> can be found in the <code>peripheral::scb</code> module.</li> </ul> <h2>[v0.4.3] - 2018-01-25</h2> <!-- raw HTML omitted --> </blockquote> <p>... (truncated)</p> </details> <details> <summary>Commits</summary> <ul> <li><a href=" |
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Real-Time Interrupt-driven Concurrency
A concurrency framework for building real-time systems.
Formerly known as Real-Time For the Masses.
Features
-
Tasks as the unit of concurrency 1. Tasks can be event triggered (fired in response to asynchronous stimuli) or spawned by the application on demand.
-
Message passing between tasks. Specifically, messages can be passed to software tasks at spawn time.
-
A timer queue 2. Software tasks can be scheduled to run at some time in the future. This feature can be used to implement periodic tasks.
-
Support for prioritization of tasks and, thus, preemptive multitasking.
-
Efficient and data race free memory sharing through fine grained priority based critical sections 1.
-
Deadlock free execution guaranteed at compile time. This is a stronger guarantee than what's provided by the standard
Mutex
abstraction.
-
Minimal scheduling overhead. The task scheduler has minimal software footprint; the hardware does the bulk of the scheduling.
-
Highly efficient memory usage: All the tasks share a single call stack and there's no hard dependency on a dynamic memory allocator.
-
All Cortex-M devices are fully supported.
-
This task model is amenable to known WCET (Worst Case Execution Time) analysis and scheduling analysis techniques.
Crate cortex-m
0.6 vs 0.7 in RTIC 0.5.x
The crate cortex-m
0.7 started using trait InterruptNumber
for interrupts instead of Nr
from bare-metal
. In order to preserve backwards compatibility, RTIC 0.5.x will keep using cortex-m
0.6 by default. cortex-m
0.7 can be enabled using the feature cortex-m-7
and disabling default features:
cortex-m-rtic = { version = "0.5.8", default-features = false, features = ["cortex-m-7"] }
RTIC 1.0.0 already uses cortex-m
0.7 by default.
User documentation
Documentation for the development version.
API reference
Community provided examples repo
Chat
Join us and talk about RTIC in the Matrix room.
Weekly meeting notes can be found over at HackMD
Contributing
New features and big changes should go through the RFC process in the dedicated RFC repository.
Running tests locally
To check all Run-pass tests
locally on your thumbv6m-none-eabi
or thumbv7m-none-eabi
target device, run
$ cargo xtask --target <your target>
# ˆˆˆˆˆˆˆˆˆˆˆˆ
# e.g. thumbv7m-none-eabi
Acknowledgments
This crate is based on the Real-Time For the Masses language created by the Embedded Systems group at Luleå University of Technology, led by Prof. Per Lindgren.
References
License
All source code (including code snippets) is licensed under either of
- Apache License, Version 2.0 (LICENSE-APACHE or https://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or https://opensource.org/licenses/MIT)
at your option.
The written prose contained within the book is licensed under the terms of the Creative Commons CC-BY-SA v4.0 license (LICENSE-CC-BY-SA or https://creativecommons.org/licenses/by-sa/4.0/legalcode).
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be licensed as above, without any additional terms or conditions.
-
Eriksson, J., Häggström, F., Aittamaa, S., Kruglyak, A., & Lindgren, P. (2013, June). Real-time for the masses, step 1: Programming API and static priority SRP kernel primitives. In Industrial Embedded Systems (SIES), 2013 8th IEEE International Symposium on (pp. 110-113). IEEE. ↩︎
-
Lindgren, P., Fresk, E., Lindner, M., Lindner, A., Pereira, D., & Pinho, L. M. (2016). Abstract timers and their implementation onto the arm cortex-m family of mcus. ACM SIGBED Review, 13(1), 48-53. ↩︎