Struct CH

#[repr(C)]
pub struct CH { /* private fields */ }

Register block

Implementations

impl CH

pub const fn ch_read_addr(&self) -> &CH_READ_ADDR

0x00 - DMA Channel 0 Read Address pointer
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.

pub const fn ch_write_addr(&self) -> &CH_WRITE_ADDR

0x04 - DMA Channel 0 Write Address pointer
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

pub const fn ch_trans_count(&self) -> &CH_TRANS_COUNT

0x08 - DMA Channel 0 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

pub const fn ch_ctrl_trig(&self) -> &CH_CTRL_TRIG

0x0c - DMA Channel 0 Control and Status

pub const fn ch_al1_ctrl(&self) -> &CH_AL1_CTRL

0x10 - DMA Channel 0 Control and Status

pub const fn ch_al1_read_addr(&self) -> &CH_AL1_READ_ADDR

0x14 - Alias for channel 0 READ_ADDR register

pub const fn ch_al1_write_addr(&self) -> &CH_AL1_WRITE_ADDR

0x18 - Alias for channel 0 WRITE_ADDR register

pub const fn ch_al1_trans_count_trig(&self) -> &CH_AL1_TRANS_COUNT_TRIG

0x1c - Alias for channel 0 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.

pub const fn ch_al2_ctrl(&self) -> &CH_AL2_CTRL

0x20 - DMA Channel 0 Control and Status

pub const fn ch_al2_trans_count(&self) -> &CH_AL2_TRANS_COUNT

0x24 - Alias for channel 0 TRANS_COUNT register

pub const fn ch_al2_read_addr(&self) -> &CH_AL2_READ_ADDR

0x28 - Alias for channel 0 READ_ADDR register

pub const fn ch_al2_write_addr_trig(&self) -> &CH_AL2_WRITE_ADDR_TRIG

0x2c - Alias for channel 0 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.

pub const fn ch_al3_ctrl(&self) -> &CH_AL3_CTRL

0x30 - DMA Channel 0 Control and Status

pub const fn ch_al3_write_addr(&self) -> &CH_AL3_WRITE_ADDR

0x34 - Alias for channel 0 WRITE_ADDR register

pub const fn ch_al3_trans_count(&self) -> &CH_AL3_TRANS_COUNT

0x38 - Alias for channel 0 TRANS_COUNT register

pub const fn ch_al3_read_addr_trig(&self) -> &CH_AL3_READ_ADDR_TRIG

0x3c - Alias for channel 0 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.