Struct W

pub struct W(/* private fields */);

Register INTENSET writer

Implementations

impl W

pub fn ready(&mut self) -> READY_W<'_, 0>

Bit 0 - Write ‘1’ to enable interrupt for READY event

pub fn address(&mut self) -> ADDRESS_W<'_, 1>

Bit 1 - Write ‘1’ to enable interrupt for ADDRESS event

pub fn payload(&mut self) -> PAYLOAD_W<'_, 2>

Bit 2 - Write ‘1’ to enable interrupt for PAYLOAD event

pub fn end(&mut self) -> END_W<'_, 3>

Bit 3 - Write ‘1’ to enable interrupt for END event

pub fn disabled(&mut self) -> DISABLED_W<'_, 4>

Bit 4 - Write ‘1’ to enable interrupt for DISABLED event

pub fn devmatch(&mut self) -> DEVMATCH_W<'_, 5>

Bit 5 - Write ‘1’ to enable interrupt for DEVMATCH event

pub fn devmiss(&mut self) -> DEVMISS_W<'_, 6>

Bit 6 - Write ‘1’ to enable interrupt for DEVMISS event

pub fn rssiend(&mut self) -> RSSIEND_W<'_, 7>

Bit 7 - Write ‘1’ to enable interrupt for RSSIEND event

pub fn bcmatch(&mut self) -> BCMATCH_W<'_, 10>

Bit 10 - Write ‘1’ to enable interrupt for BCMATCH event

pub fn crcok(&mut self) -> CRCOK_W<'_, 12>

Bit 12 - Write ‘1’ to enable interrupt for CRCOK event

pub fn crcerror(&mut self) -> CRCERROR_W<'_, 13>

Bit 13 - Write ‘1’ to enable interrupt for CRCERROR event

pub fn framestart(&mut self) -> FRAMESTART_W<'_, 14>

Bit 14 - Write ‘1’ to enable interrupt for FRAMESTART event

pub fn edend(&mut self) -> EDEND_W<'_, 15>

Bit 15 - Write ‘1’ to enable interrupt for EDEND event

pub fn edstopped(&mut self) -> EDSTOPPED_W<'_, 16>

Bit 16 - Write ‘1’ to enable interrupt for EDSTOPPED event

pub fn ccaidle(&mut self) -> CCAIDLE_W<'_, 17>

Bit 17 - Write ‘1’ to enable interrupt for CCAIDLE event

pub fn ccabusy(&mut self) -> CCABUSY_W<'_, 18>

Bit 18 - Write ‘1’ to enable interrupt for CCABUSY event

pub fn ccastopped(&mut self) -> CCASTOPPED_W<'_, 19>

Bit 19 - Write ‘1’ to enable interrupt for CCASTOPPED event

pub fn rateboost(&mut self) -> RATEBOOST_W<'_, 20>

Bit 20 - Write ‘1’ to enable interrupt for RATEBOOST event

pub fn txready(&mut self) -> TXREADY_W<'_, 21>

Bit 21 - Write ‘1’ to enable interrupt for TXREADY event

pub fn rxready(&mut self) -> RXREADY_W<'_, 22>

Bit 22 - Write ‘1’ to enable interrupt for RXREADY event

pub fn mhrmatch(&mut self) -> MHRMATCH_W<'_, 23>

Bit 23 - Write ‘1’ to enable interrupt for MHRMATCH event

pub fn phyend(&mut self) -> PHYEND_W<'_, 27>

Bit 27 - Write ‘1’ to enable interrupt for PHYEND event

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<INTENSET_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<INTENSET_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<INTENSET_SPEC>> for W

fn from(writer: W<INTENSET_SPEC>) -> Self

Converts to this type from the input type.