691: Basic cfg support, kind of, for Monotonics r=korken89 a=AfoHT
- Enable at least masking out a Monotonic
- Add example cfg-ing a Monotonic, showing limitations imposed by rtic-syntax
- Update changelog
The use case detailed in linked issue seems to be covered: Fixes#664
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
686: Book: Editorial review r=korken89 a=AfoHT
Continuation of https://github.com/rtic-rs/cortex-m-rtic/pull/618
Better late than never...
A big thanks to `@jvanderk` !
Co-authored-by: John van der Koijk <33966414+jvanderk@users.noreply.github.com>
Simplest case working, but leaves a lot to ask
as shown by examples/cfg-monotonic.rs
Current `rtic-syntax` is unable to validate and
handle the `cfgs[]` which limits the usefulness
of this.
690: NVIC prio bits must be in the range 1..=255: Handled by logical2hw() r=korken89 a=AfoHT
Fixes#687
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
689: Missing docs: Improve #[doc] generation r=korken89 a=AfoHT
Improve RTIC doc handling
Enable use of
```
#![deny(missing_docs)]
```
and makes the cargo doc output more useful
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
680: Update cortex-m-semihosting requirement from 0.3.3 to 0.5.0 r=AfoHT a=dependabot[bot]
Updates the requirements on [cortex-m-semihosting](https://github.com/rust-embedded/cortex-m) to permit the latest version.
<details>
<summary>Changelog</summary>
<p><em>Sourced from <a href="https://github.com/rust-embedded/cortex-m/blob/master/CHANGELOG.md">cortex-m-semihosting's changelog</a>.</em></p>
<blockquote>
<h2>[v0.5.0] - 2018-05-11</h2>
<h3>Added</h3>
<ul>
<li>
<p><code>DebugMonitor</code> and <code>SecureFault</code> variants to the <code>Exception</code> enumeration.</p>
</li>
<li>
<p>An optional <code>"inline-asm"</code> feature</p>
</li>
</ul>
<h3>Changed</h3>
<ul>
<li>
<p>[breaking-change] This crate now requires <code>arm-none-eabi-gcc</code> to be installed and available in
<code>$PATH</code> when built with the <code>"inline-asm"</code> feature disabled (which is disabled by default).</p>
</li>
<li>
<p>[breaking-change] The <code>register::{apsr,lr,pc}</code> modules are now behind the <code>"inline-asm"</code> feature.</p>
</li>
<li>
<p>[breaking-change] Some variants of the <code>Exception</code> enumeration are no longer available on
<code>thumbv6m-none-eabi</code>. See API docs for details.</p>
</li>
<li>
<p>[breaking-change] Several of the variants of the <code>Exception</code> enumeration have been renamed to
match the CMSIS specification.</p>
</li>
<li>
<p>[breaking-change] fixed typo in <code>shcrs</code> field of <code>scb::RegisterBlock</code>; it was previously named
<code>shpcrs</code>.</p>
</li>
<li>
<p>[breaking-change] removed several fields from <code>scb::RegisterBlock</code> on ARMv6-M. These registers are
not available on that sub-architecture.</p>
</li>
<li>
<p>[breaking-change] changed the type of <code>scb::RegisterBlock.shpr</code> from <code>RW<u8></code> to <code>RW<u32></code> on
ARMv6-M. These registers are word accessible only on that sub-architecture.</p>
</li>
<li>
<p>[breaking-change] renamed the <code>mmar</code> field of <code>scb::RegisterBlock</code> to <code>mmfar</code> to match the CMSIS
name.</p>
</li>
<li>
<p>[breaking-change] removed the <code>iabr</code> field from <code>scb::RegisterBlock</code> on ARMv6-M. This register is
not available on that sub-architecture.</p>
</li>
<li>
<p>[breaking-change] removed several fields from <code>cpuid::RegisterBlock</code> on ARMv6-M. These registers
are not available on that sub-architecture.</p>
</li>
<li>
<p>[breaking-change] The <code>Mutex.new</code> constructor is not a <code>const fn</code> by default. To make it a <code>const fn</code> you have to opt into the <code>"const-fn"</code> feature, which was added in v0.5.1, and switch to a
nightly compiler.</p>
</li>
</ul>
<h3>Removed</h3>
<ul>
<li>[breaking-change] The <code>exception</code> module has been removed. A replacement for <code>Exception::active</code>
can be found in <code>SCB::vect_active</code>. A modified version <code>exception::Exception</code> can be found in the
<code>peripheral::scb</code> module.</li>
</ul>
<h2>[v0.4.3] - 2018-01-25</h2>
<!-- raw HTML omitted -->
</blockquote>
<p>... (truncated)</p>
</details>
<details>
<summary>Commits</summary>
<ul>
<li><a href="a448e9156e"><code>a448e91</code></a> v0.5.0</li>
<li><a href="e3217ad94d"><code>e3217ad</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/88">#88</a></li>
<li><a href="05bbc3b815"><code>05bbc3b</code></a> always list all the peripherals in <code>Peripherals</code></li>
<li><a href="550f94902f"><code>550f949</code></a> fix build for ARMv7E-M + "inline-asm"</li>
<li><a href="7d51707b5f"><code>7d51707</code></a> simplify #[cfg]s</li>
<li><a href="2cd6092848"><code>2cd6092</code></a> ARMv6-M: remove fields that are not available from cpuid::RegisterBlock</li>
<li><a href="17bd0c8e88"><code>17bd0c8</code></a> fix x86_64 tests</li>
<li><a href="c290aa4ee8"><code>c290aa4</code></a> ARMv6-M: remove fields that are not available from NVIC and SCB</li>
<li><a href="716398ce54"><code>716398c</code></a> fix build on ARMv6-M</li>
<li><a href="1d68643772"><code>1d68643</code></a> fix build on ARMv7E-M</li>
<li>Additional commits viewable in <a href="https://github.com/rust-embedded/cortex-m/compare/c-m-sh-v0.3.5...v0.5.0">compare view</a></li>
</ul>
</details>
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Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
New semihosting 0.5 does not use error handling,
returns directly and as semihosting is generally slow
this led to missing print statements.
Workaround is to add NOP, which seems sufficient
to let it flush the buffers
670: Add documentation for different Cortex-M architectures r=AfoHT a=n8tlarsen
Most of the RTIC documentation focuses on ARMv7-M architectures. Here's some initial thoughts on useful information I would have liked to know before starting with RTIC on ARMv6-M.
Co-authored-by: Nathan <n8tlarsen@gmail.com>
Co-authored-by: n8tlarsen <96437952+n8tlarsen@users.noreply.github.com>
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
