This doesn't fix the GPIO interrupt triggering during a higher priority
CPU task, but does fix rtic-monotonics. I am unsure how to fix the
former as PLIC_MX doesn't have a function like `cpu_intr_from_cpu_x` to
pend/unpend CPU interrupts, and if the CPU interrupts are enabled with
PLIC_MX instead of INTPRI then the MCU just hangs when there is a CPU
interrupt.
* Fix stm32 read-modify-write problem
The `SR` register for STM32 clears when writing a zero to a bit.
Therefore, all registers that should not be cleared need to be `1`.
`modify` here caused a read-modify-write error that could clear
unrelated flags.
* Add changelog
* Make initialization more deterministic
* Update changelog
* Beautification in comments
---------
Co-authored-by: Martin Stumpf <martin.stumpf@vected.de>
* Update `rtic` package to use latest version of `esp32c3` dependency
* Update `rtic-macros` ESP32-C3 bindings to reflect changes in HAL
* Update the ESP32-C3 examples to use latest versions of all dependencies
* Update changelogs
* adjust expected qemu output, add compile-time checks
* remove runtime checks, this is checked at compile time
* fix expected qemu output
* Clean up interrupt enable code a bit
* Update `rtic-monotonic` to use the latest PAC for ESP32-C3
* Update `CHANGELOG.md` for `rtic-monotonic`
* ci: esp32c3: Format runner.sh
* ci: esp32c3: Default to silent boot
export DEBUGGING while running to get verbose boot
env DEBUGGING=1 cargo xtask ...
* ci: esp32c3: Update expected example output
---------
Co-authored-by: onsdagens <pawdzi-7@student.ltu.se>
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* Add support for RP235x (Raspberry Pico 2)
The xtask build system has not been updated therefor the
components need to be build through Cargo
* Remove unnecessary thumbv8mainhf-backend definition
* Remove unnecessary thumbv8m.main-none-eabihf target
* Update CHANGELOG
* Remove default feature rp235x from rtic-monotonics
* Remove features from rp235x-pac dependency in rtic-monotonics for rp235x
* Update dependencies of stm32g0 timer example
* Replace obsolete probe-run with probe-rs run
* Modify stm32 monotonic to work with timers that have only 2 compare modules
* Add changelog
* Fix typo
* Atomics: Replace polyfill with portable-atomic
* Update Cargo.lock for examples
* RTIC: portable-atomic: Update changelog
* rtic-monotonics: portable-atomic: Update changelog
* lm3s6965: enable critical-section when testing
* xtask: Enable portable-atomic/critical-section
When dealing with rtic-monotonics
* rtic-monotonics: portable-atomics: Do not disable the ability to fallback
---------
Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
* Rework timer_queue and monotonic architecture
Goals:
* make Monotonic purely internal
* make Monotonic purely tick passed, no fugit involved
* create a wrapper struct in the user's code via a macro that then
converts the "now" from the tick based monotonic to a fugit based
timestamp
We need to proxy the delay functions of the timer queue anyway,
so we could simply perform the conversion in those proxy functions.
* Update cargo.lock
* Update readme of rtic-time
* CI: ESP32: Redact esp_image: Too volatile
* Fixup: Changelog double entry rebase mistake
---------
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* Rebase to master
* using interrupt_mod
* bug fixes
* fix other backends
* Add changelog
* forgot about rtic-macros
* backend-specific configuration
* core peripherals optional over macro argument
* pre_init_preprocessing binding
* CI for RISC-V (WIP)
* separation of concerns
* add targets for RISC-V examples
* remove qemu feature
* prepare examples folder
* move examples all together
* move ci out of examples
* minor changes
* add cortex-m
* new xtask: proof of concept
* fix build.yml
* feature typo
* clean rtic examples
* reproduce weird issue
* remove unsafe code in user app
* update dependencies
* allow builds on riscv32imc
* let's fix QEMU
* Update .github/workflows/build.yml
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* New build.rs
* removing test features
* adapt ui test to new version of clippy
* add more examples to RISC-V backend
* proper configuration of heapless for riscv32imc
* opt-out examples for riscv32imc
* point to new version of riscv-slic
* adapt new macro bindings
* adapt examples and CI to stable
* fix cortex-m CI
* Review
---------
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
