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Use PLIC_MX instead of INTPRI to set interrupt priorities

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This doesn't fix the GPIO interrupt triggering during a higher priority
CPU task, but does fix rtic-monotonics. I am unsure how to fix the
former as PLIC_MX doesn't have a function like `cpu_intr_from_cpu_x` to
pend/unpend CPU interrupts, and if the CPU interrupts are enabled with
PLIC_MX instead of INTPRI then the MCU just hangs when there is a CPU
interrupt.
This commit is contained in:
Eli Hastings 2025-02-26 11:39:09 +00:00 • committed by Henrik Tjäder
parent ef09e4b65f
commit 9305963752
2 changed files with 58 additions and 36 deletions
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10
rtic-monotonics/src/esp32c6.rs
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@ -35,7 +35,7 @@ pub mod prelude {
pub use fugit::{self, ExtU64, ExtU64Ceil};
}
use crate::TimerQueueBackend;
use esp32c6::{INTERRUPT_CORE0, INTPRI, SYSTIMER};
use esp32c6::{INTERRUPT_CORE0, PLIC_MX, SYSTIMER};
use rtic_time::timer_queue::TimerQueue;
/// Timer implementing [`TimerQueueBackend`].
@ -57,13 +57,13 @@ impl TimerBackend {
.write_volatile(cpu_interrupt_number as u32);
// Set the interrupt's priority:
(*INTPRI::ptr())
.cpu_int_pri(cpu_interrupt_number as usize)
(*PLIC_MX::ptr())
.mxint_pri(cpu_interrupt_number as usize)
.write(|w| w.bits(15 as u32));
// Finally, enable the CPU interrupt:
(*INTPRI::ptr())
.cpu_int_enable()
(*PLIC_MX::ptr())
.mxint_enable()
.modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits()));
}