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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Cluster Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"><title>rp2040_pac::dma::ch - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module ch</a></h2><h3><a href="#modules">Module Items</a></h3><ul class="block"><li><a href="#modules" title="Modules">Modules</a></li><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>dma</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">dma</a></span><h1>Module <span>ch</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/rp2040_pac/dma/ch.rs.html#1-292">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Cluster
Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="ch_al1_ctrl/index.html" title="mod rp2040_pac::dma::ch::ch_al1_ctrl">ch_<wbr>al1_<wbr>ctrl</a></div><div class="desc docblock-short">DMA Channel 0 Control and Status</div></li><li><div class="item-name"><a class="mod" href="ch_al1_read_addr/index.html" title="mod rp2040_pac::dma::ch::ch_al1_read_addr">ch_<wbr>al1_<wbr>read_<wbr>addr</a></div><div class="desc docblock-short">Alias for channel 0 READ_ADDR register</div></li><li><div class="item-name"><a class="mod" href="ch_al1_trans_count_trig/index.html" title="mod rp2040_pac::dma::ch::ch_al1_trans_count_trig">ch_<wbr>al1_<wbr>trans_<wbr>count_<wbr>trig</a></div><div class="desc docblock-short">Alias for channel 0 TRANS_COUNT register<br />
This is a trigger register (0xc). Writing a nonzero value will<br />
reload the channel counter and start the channel.</div></li><li><div class="item-name"><a class="mod" href="ch_al1_write_addr/index.html" title="mod rp2040_pac::dma::ch::ch_al1_write_addr">ch_<wbr>al1_<wbr>write_<wbr>addr</a></div><div class="desc docblock-short">Alias for channel 0 WRITE_ADDR register</div></li><li><div class="item-name"><a class="mod" href="ch_al2_ctrl/index.html" title="mod rp2040_pac::dma::ch::ch_al2_ctrl">ch_<wbr>al2_<wbr>ctrl</a></div><div class="desc docblock-short">DMA Channel 0 Control and Status</div></li><li><div class="item-name"><a class="mod" href="ch_al2_read_addr/index.html" title="mod rp2040_pac::dma::ch::ch_al2_read_addr">ch_<wbr>al2_<wbr>read_<wbr>addr</a></div><div class="desc docblock-short">Alias for channel 0 READ_ADDR register</div></li><li><div class="item-name"><a class="mod" href="ch_al2_trans_count/index.html" title="mod rp2040_pac::dma::ch::ch_al2_trans_count">ch_<wbr>al2_<wbr>trans_<wbr>count</a></div><div class="desc docblock-short">Alias for channel 0 TRANS_COUNT register</div></li><li><div class="item-name"><a class="mod" href="ch_al2_write_addr_trig/index.html" title="mod rp2040_pac::dma::ch::ch_al2_write_addr_trig">ch_<wbr>al2_<wbr>write_<wbr>addr_<wbr>trig</a></div><div class="desc docblock-short">Alias for channel 0 WRITE_ADDR register<br />
This is a trigger register (0xc). Writing a nonzero value will<br />
reload the channel counter and start the channel.</div></li><li><div class="item-name"><a class="mod" href="ch_al3_ctrl/index.html" title="mod rp2040_pac::dma::ch::ch_al3_ctrl">ch_<wbr>al3_<wbr>ctrl</a></div><div class="desc docblock-short">DMA Channel 0 Control and Status</div></li><li><div class="item-name"><a class="mod" href="ch_al3_read_addr_trig/index.html" title="mod rp2040_pac::dma::ch::ch_al3_read_addr_trig">ch_<wbr>al3_<wbr>read_<wbr>addr_<wbr>trig</a></div><div class="desc docblock-short">Alias for channel 0 READ_ADDR register<br />
This is a trigger register (0xc). Writing a nonzero value will<br />
reload the channel counter and start the channel.</div></li><li><div class="item-name"><a class="mod" href="ch_al3_trans_count/index.html" title="mod rp2040_pac::dma::ch::ch_al3_trans_count">ch_<wbr>al3_<wbr>trans_<wbr>count</a></div><div class="desc docblock-short">Alias for channel 0 TRANS_COUNT register</div></li><li><div class="item-name"><a class="mod" href="ch_al3_write_addr/index.html" title="mod rp2040_pac::dma::ch::ch_al3_write_addr">ch_<wbr>al3_<wbr>write_<wbr>addr</a></div><div class="desc docblock-short">Alias for channel 0 WRITE_ADDR register</div></li><li><div class="item-name"><a class="mod" href="ch_ctrl_trig/index.html" title="mod rp2040_pac::dma::ch::ch_ctrl_trig">ch_<wbr>ctrl_<wbr>trig</a></div><div class="desc docblock-short">DMA Channel 0 Control and Status</div></li><li><div class="item-name"><a class="mod" href="ch_read_addr/index.html" title="mod rp2040_pac::dma::ch::ch_read_addr">ch_<wbr>read_<wbr>addr</a></div><div class="desc docblock-short">DMA Channel 0 Read Address pointer<br />
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</div></li><li><div class="item-name"><a class="mod" href="ch_trans_count/index.html" title="mod rp2040_pac::dma::ch::ch_trans_count">ch_<wbr>trans_<wbr>count</a></div><div class="desc docblock-short">DMA Channel 0 Transfer Count<br />
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).</div></li><li><div class="item-name"><a class="mod" href="ch_write_addr/index.html" title="mod rp2040_pac::dma::ch::ch_write_addr">ch_<wbr>write_<wbr>addr</a></div><div class="desc docblock-short">DMA Channel 0 Write Address pointer<br />
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.CH.html" title="struct rp2040_pac::dma::ch::CH">CH</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.CH_AL1_CTRL.html" title="type rp2040_pac::dma::ch::CH_AL1_CTRL">CH_<wbr>AL1_<wbr>CTRL</a></div><div class="desc docblock-short">CH_AL1_CTRL (rw) register accessor: DMA Channel 0 Control and Status</div></li><li><div class="item-name"><a class="type" href="type.CH_AL1_READ_ADDR.html" title="type rp2040_pac::dma::ch::CH_AL1_READ_ADDR">CH_<wbr>AL1_<wbr>READ_<wbr>ADDR</a></div><div class="desc docblock-short">CH_AL1_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register</div></li><li><div class="item-name"><a class="type" href="type.CH_AL1_TRANS_COUNT_TRIG.html" title="type rp2040_pac::dma::ch::CH_AL1_TRANS_COUNT_TRIG">CH_<wbr>AL1_<wbr>TRANS_<wbr>COUNT_<wbr>TRIG</a></div><div class="desc docblock-short">CH_AL1_TRANS_COUNT_TRIG (rw) register accessor: Alias for channel 0 TRANS_COUNT register<br />
This is a trigger register (0xc). Writing a nonzero value will<br />
reload the channel counter and start the channel.</div></li><li><div class="item-name"><a class="type" href="type.CH_AL1_WRITE_ADDR.html" title="type rp2040_pac::dma::ch::CH_AL1_WRITE_ADDR">CH_<wbr>AL1_<wbr>WRITE_<wbr>ADDR</a></div><div class="desc docblock-short">CH_AL1_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register</div></li><li><div class="item-name"><a class="type" href="type.CH_AL2_CTRL.html" title="type rp2040_pac::dma::ch::CH_AL2_CTRL">CH_<wbr>AL2_<wbr>CTRL</a></div><div class="desc docblock-short">CH_AL2_CTRL (rw) register accessor: DMA Channel 0 Control and Status</div></li><li><div class="item-name"><a class="type" href="type.CH_AL2_READ_ADDR.html" title="type rp2040_pac::dma::ch::CH_AL2_READ_ADDR">CH_<wbr>AL2_<wbr>READ_<wbr>ADDR</a></div><div class="desc docblock-short">CH_AL2_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register</div></li><li><div class="item-name"><a class="type" href="type.CH_AL2_TRANS_COUNT.html" title="type rp2040_pac::dma::ch::CH_AL2_TRANS_COUNT">CH_<wbr>AL2_<wbr>TRANS_<wbr>COUNT</a></div><div class="desc docblock-short">CH_AL2_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register</div></li><li><div class="item-name"><a class="type" href="type.CH_AL2_WRITE_ADDR_TRIG.html" title="type rp2040_pac::dma::ch::CH_AL2_WRITE_ADDR_TRIG">CH_<wbr>AL2_<wbr>WRITE_<wbr>ADDR_<wbr>TRIG</a></div><div class="desc docblock-short">CH_AL2_WRITE_ADDR_TRIG (rw) register accessor: Alias for channel 0 WRITE_ADDR register<br />
This is a trigger register (0xc). Writing a nonzero value will<br />
reload the channel counter and start the channel.</div></li><li><div class="item-name"><a class="type" href="type.CH_AL3_CTRL.html" title="type rp2040_pac::dma::ch::CH_AL3_CTRL">CH_<wbr>AL3_<wbr>CTRL</a></div><div class="desc docblock-short">CH_AL3_CTRL (rw) register accessor: DMA Channel 0 Control and Status</div></li><li><div class="item-name"><a class="type" href="type.CH_AL3_READ_ADDR_TRIG.html" title="type rp2040_pac::dma::ch::CH_AL3_READ_ADDR_TRIG">CH_<wbr>AL3_<wbr>READ_<wbr>ADDR_<wbr>TRIG</a></div><div class="desc docblock-short">CH_AL3_READ_ADDR_TRIG (rw) register accessor: Alias for channel 0 READ_ADDR register<br />
This is a trigger register (0xc). Writing a nonzero value will<br />
reload the channel counter and start the channel.</div></li><li><div class="item-name"><a class="type" href="type.CH_AL3_TRANS_COUNT.html" title="type rp2040_pac::dma::ch::CH_AL3_TRANS_COUNT">CH_<wbr>AL3_<wbr>TRANS_<wbr>COUNT</a></div><div class="desc docblock-short">CH_AL3_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register</div></li><li><div class="item-name"><a class="type" href="type.CH_AL3_WRITE_ADDR.html" title="type rp2040_pac::dma::ch::CH_AL3_WRITE_ADDR">CH_<wbr>AL3_<wbr>WRITE_<wbr>ADDR</a></div><div class="desc docblock-short">CH_AL3_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register</div></li><li><div class="item-name"><a class="type" href="type.CH_CTRL_TRIG.html" title="type rp2040_pac::dma::ch::CH_CTRL_TRIG">CH_<wbr>CTRL_<wbr>TRIG</a></div><div class="desc docblock-short">CH_CTRL_TRIG (rw) register accessor: DMA Channel 0 Control and Status</div></li><li><div class="item-name"><a class="type" href="type.CH_READ_ADDR.html" title="type rp2040_pac::dma::ch::CH_READ_ADDR">CH_<wbr>READ_<wbr>ADDR</a></div><div class="desc docblock-short">CH_READ_ADDR (rw) register accessor: DMA Channel 0 Read Address pointer<br />
This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</div></li><li><div class="item-name"><a class="type" href="type.CH_TRANS_COUNT.html" title="type rp2040_pac::dma::ch::CH_TRANS_COUNT">CH_<wbr>TRANS_<wbr>COUNT</a></div><div class="desc docblock-short">CH_TRANS_COUNT (rw) register accessor: DMA Channel 0 Transfer Count<br />
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).</div></li><li><div class="item-name"><a class="type" href="type.CH_WRITE_ADDR.html" title="type rp2040_pac::dma::ch::CH_WRITE_ADDR">CH_<wbr>WRITE_<wbr>ADDR</a></div><div class="desc docblock-short">CH_WRITE_ADDR (rw) register accessor: DMA Channel 0 Write Address pointer<br />
This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</div></li></ul></section></div></main></body></html>
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