Module ch

Cluster Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG

Modules

• ch_al1_ctrl
  DMA Channel 0 Control and Status
• ch_al1_read_addr
  Alias for channel 0 READ_ADDR register
• ch_al1_trans_count_trig
  Alias for channel 0 TRANS_COUNT register
  This is a trigger register (0xc). Writing a nonzero value will
  reload the channel counter and start the channel.
• ch_al1_write_addr
  Alias for channel 0 WRITE_ADDR register
• ch_al2_ctrl
  DMA Channel 0 Control and Status
• ch_al2_read_addr
  Alias for channel 0 READ_ADDR register
• ch_al2_trans_count
  Alias for channel 0 TRANS_COUNT register
• ch_al2_write_addr_trig
  Alias for channel 0 WRITE_ADDR register
  This is a trigger register (0xc). Writing a nonzero value will
  reload the channel counter and start the channel.
• ch_al3_ctrl
  DMA Channel 0 Control and Status
• ch_al3_read_addr_trig
  Alias for channel 0 READ_ADDR register
  This is a trigger register (0xc). Writing a nonzero value will
  reload the channel counter and start the channel.
• ch_al3_trans_count
  Alias for channel 0 TRANS_COUNT register
• ch_al3_write_addr
  Alias for channel 0 WRITE_ADDR register
• ch_ctrl_trig
  DMA Channel 0 Control and Status
• ch_read_addr
  DMA Channel 0 Read Address pointer
  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
• ch_trans_count
  DMA Channel 0 Transfer Count
  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
• ch_write_addr
  DMA Channel 0 Write Address pointer
  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.

Structs

• CH
  Register block

Type Aliases

• CH_AL1_CTRL
  CH_AL1_CTRL (rw) register accessor: DMA Channel 0 Control and Status
• CH_AL1_READ_ADDR
  CH_AL1_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register
• CH_AL1_TRANS_COUNT_TRIG
  CH_AL1_TRANS_COUNT_TRIG (rw) register accessor: Alias for channel 0 TRANS_COUNT register
  This is a trigger register (0xc). Writing a nonzero value will
  reload the channel counter and start the channel.
• CH_AL1_WRITE_ADDR
  CH_AL1_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register
• CH_AL2_CTRL
  CH_AL2_CTRL (rw) register accessor: DMA Channel 0 Control and Status
• CH_AL2_READ_ADDR
  CH_AL2_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register
• CH_AL2_TRANS_COUNT
  CH_AL2_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register
• CH_AL2_WRITE_ADDR_TRIG
  CH_AL2_WRITE_ADDR_TRIG (rw) register accessor: Alias for channel 0 WRITE_ADDR register
  This is a trigger register (0xc). Writing a nonzero value will
  reload the channel counter and start the channel.
• CH_AL3_CTRL
  CH_AL3_CTRL (rw) register accessor: DMA Channel 0 Control and Status
• CH_AL3_READ_ADDR_TRIG
  CH_AL3_READ_ADDR_TRIG (rw) register accessor: Alias for channel 0 READ_ADDR register
  This is a trigger register (0xc). Writing a nonzero value will
  reload the channel counter and start the channel.
• CH_AL3_TRANS_COUNT
  CH_AL3_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register
• CH_AL3_WRITE_ADDR
  CH_AL3_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register
• CH_CTRL_TRIG
  CH_CTRL_TRIG (rw) register accessor: DMA Channel 0 Control and Status
• CH_READ_ADDR
  CH_READ_ADDR (rw) register accessor: DMA Channel 0 Read Address pointer
  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
• CH_TRANS_COUNT
  CH_TRANS_COUNT (rw) register accessor: DMA Channel 0 Transfer Count
  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
• CH_WRITE_ADDR
  CH_WRITE_ADDR (rw) register accessor: DMA Channel 0 Write Address pointer
  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.