Module ctrl

Cache control

Structs

• CTRL_SPEC
  Cache control

Type Aliases

• EN_R
  Field EN reader - When 1, enable the cache. When the cache is disabled, all XIP accesses
  will go straight to the flash, without querying the cache. When enabled,
  cacheable XIP accesses will query the cache, and the flash will
  not be accessed if the tag matches and the valid bit is set.
• EN_W
  Field EN writer - When 1, enable the cache. When the cache is disabled, all XIP accesses
  will go straight to the flash, without querying the cache. When enabled,
  cacheable XIP accesses will query the cache, and the flash will
  not be accessed if the tag matches and the valid bit is set.
• ERR_BADWRITE_R
  Field ERR_BADWRITE reader - When 1, writes to any alias other than 0x0 (caching, allocating)
  will produce a bus fault. When 0, these writes are silently ignored.
  In either case, writes to the 0x0 alias will deallocate on tag match,
  as usual.
• ERR_BADWRITE_W
  Field ERR_BADWRITE writer - When 1, writes to any alias other than 0x0 (caching, allocating)
  will produce a bus fault. When 0, these writes are silently ignored.
  In either case, writes to the 0x0 alias will deallocate on tag match,
  as usual.
• POWER_DOWN_R
  Field POWER_DOWN reader - When 1, the cache memories are powered down. They retain state,
  but can not be accessed. This reduces static power dissipation.
  Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot
  be enabled when powered down.
  Cache-as-SRAM accesses will produce a bus error response when
  the cache is powered down.
• POWER_DOWN_W
  Field POWER_DOWN writer - When 1, the cache memories are powered down. They retain state,
  but can not be accessed. This reduces static power dissipation.
  Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot
  be enabled when powered down.
  Cache-as-SRAM accesses will produce a bus error response when
  the cache is powered down.
• R
  Register CTRL reader
• W
  Register CTRL writer