pub struct XIP_CTRL { /* private fields */ }
Expand description
QSPI flash execute-in-place block
Implementations§
source§impl XIP_CTRL
impl XIP_CTRL
sourcepub const PTR: *const RegisterBlock = {0x14000000 as *const xip_ctrl::RegisterBlock}
pub const PTR: *const RegisterBlock = {0x14000000 as *const xip_ctrl::RegisterBlock}
Pointer to the register block
sourcepub const fn ptr() -> *const RegisterBlock
pub const fn ptr() -> *const RegisterBlock
Return the pointer to the register block
sourcepub unsafe fn steal() -> Self
pub unsafe fn steal() -> Self
Steal an instance of this peripheral
§Safety
Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.
Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.
Methods from Deref<Target = RegisterBlock>§
sourcepub fn ctr_hit(&self) -> &CTR_HIT
pub fn ctr_hit(&self) -> &CTR_HIT
0x0c - Cache Hit counter
A 32 bit saturating counter that increments upon each cache hit,
i.e. when an XIP access is serviced directly from cached data.
Write any value to clear.
sourcepub fn ctr_acc(&self) -> &CTR_ACC
pub fn ctr_acc(&self) -> &CTR_ACC
0x10 - Cache Access counter
A 32 bit saturating counter that increments upon each XIP access,
whether the cache is hit or not. This includes noncacheable accesses.
Write any value to clear.
sourcepub fn stream_addr(&self) -> &STREAM_ADDR
pub fn stream_addr(&self) -> &STREAM_ADDR
0x14 - FIFO stream address
sourcepub fn stream_ctr(&self) -> &STREAM_CTR
pub fn stream_ctr(&self) -> &STREAM_CTR
0x18 - FIFO stream control
sourcepub fn stream_fifo(&self) -> &STREAM_FIFO
pub fn stream_fifo(&self) -> &STREAM_FIFO
0x1c - FIFO stream data
Streamed data is buffered here, for retrieval by the system DMA.
This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing
the DMA to bus stalls caused by other XIP traffic.