pub struct CPUID { /* private fields */ }
Expand description
CPUID
Implementations§
source§impl CPUID
impl CPUID
sourcepub fn select_cache(&mut self, level: u8, ind: CsselrCacheType)
pub fn select_cache(&mut self, level: u8, ind: CsselrCacheType)
Selects the current CCSIDR
level
: the required cache level minus 1, e.g. 0 for L1, 1 for L2ind
: select instruction cache or data/unified cache
level
is masked to be between 0 and 7.
sourcepub fn cache_num_sets_ways(
&mut self,
level: u8,
ind: CsselrCacheType,
) -> (u16, u16)
pub fn cache_num_sets_ways( &mut self, level: u8, ind: CsselrCacheType, ) -> (u16, u16)
Returns the number of sets and ways in the selected cache
sourcepub fn cache_dminline() -> u32
pub fn cache_dminline() -> u32
Returns log2 of the number of words in the smallest cache line of all the data cache and unified caches that are controlled by the processor.
This is the DminLine
field of the CTR register.
sourcepub fn cache_iminline() -> u32
pub fn cache_iminline() -> u32
Returns log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor.
This is the IminLine
field of the CTR register.
source§impl CPUID
impl CPUID
sourcepub const PTR: *const RegisterBlock = {0xe000ed00 as *const cortex_m::peripheral::cpuid::RegisterBlock}
pub const PTR: *const RegisterBlock = {0xe000ed00 as *const cortex_m::peripheral::cpuid::RegisterBlock}
Pointer to the register block
sourcepub const fn ptr() -> *const RegisterBlock
👎Deprecated since 0.7.5: Use the associated constant PTR
instead
pub const fn ptr() -> *const RegisterBlock
PTR
insteadReturns a pointer to the register block
Trait Implementations§
Auto Trait Implementations§
impl Freeze for CPUID
impl RefUnwindSafe for CPUID
impl !Sync for CPUID
impl Unpin for CPUID
impl UnwindSafe for CPUID
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more