Module dma

DMA with separate read and write masters

Re-exports

• pub use self::ch::CH;

Modules

• ch
  Cluster Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG
• ch0_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch0_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch1_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch1_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch2_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch2_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch3_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch3_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch4_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch4_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch5_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch5_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch6_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch6_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch7_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch7_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch8_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch8_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch9_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch9_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch10_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch10_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• ch11_dbg_ctdreq
  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• ch11_dbg_tcr
  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• chan_abort
  Abort an in-progress transfer sequence on one or more channels
• fifo_levels
  Debug RAF, WAF, TDF levels
• inte0
  Interrupt Enables for IRQ 0
• inte1
  Interrupt Enables for IRQ 1
• intf0
  Force Interrupts
• intf1
  Force Interrupts for IRQ 1
• intr
  Interrupt Status (raw)
• ints0
  Interrupt Status for IRQ 0
• ints1
  Interrupt Status (masked) for IRQ 1
• multi_chan_trigger
  Trigger one or more channels simultaneously
• n_channels
  The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
• sniff_ctrl
  Sniffer Control
• sniff_data
  Data accumulator for sniff hardware
  Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
• timer0
  Pacing (X/Y) Fractional Timer
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
• timer1
  Pacing (X/Y) Fractional Timer
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
• timer2
  Pacing (X/Y) Fractional Timer
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
• timer3
  Pacing (X/Y) Fractional Timer
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

Structs

• RegisterBlock
  Register block

Type Aliases

• CH0_DBG_CTDREQ
  CH0_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH0_DBG_TCR
  CH0_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH1_DBG_CTDREQ
  CH1_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH1_DBG_TCR
  CH1_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH2_DBG_CTDREQ
  CH2_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH2_DBG_TCR
  CH2_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH3_DBG_CTDREQ
  CH3_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH3_DBG_TCR
  CH3_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH4_DBG_CTDREQ
  CH4_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH4_DBG_TCR
  CH4_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH5_DBG_CTDREQ
  CH5_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH5_DBG_TCR
  CH5_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH6_DBG_CTDREQ
  CH6_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH6_DBG_TCR
  CH6_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH7_DBG_CTDREQ
  CH7_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH7_DBG_TCR
  CH7_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH8_DBG_CTDREQ
  CH8_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH8_DBG_TCR
  CH8_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH9_DBG_CTDREQ
  CH9_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH9_DBG_TCR
  CH9_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH10_DBG_CTDREQ
  CH10_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH10_DBG_TCR
  CH10_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CH11_DBG_CTDREQ
  CH11_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
• CH11_DBG_TCR
  CH11_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
• CHAN_ABORT
  CHAN_ABORT (rw) register accessor: Abort an in-progress transfer sequence on one or more channels
• FIFO_LEVELS
  FIFO_LEVELS (r) register accessor: Debug RAF, WAF, TDF levels
• INTE0
  INTE0 (rw) register accessor: Interrupt Enables for IRQ 0
• INTE1
  INTE1 (rw) register accessor: Interrupt Enables for IRQ 1
• INTF0
  INTF0 (rw) register accessor: Force Interrupts
• INTF1
  INTF1 (rw) register accessor: Force Interrupts for IRQ 1
• INTR
  INTR (rw) register accessor: Interrupt Status (raw)
• INTS0
  INTS0 (rw) register accessor: Interrupt Status for IRQ 0
• INTS1
  INTS1 (rw) register accessor: Interrupt Status (masked) for IRQ 1
• MULTI_CHAN_TRIGGER
  MULTI_CHAN_TRIGGER (rw) register accessor: Trigger one or more channels simultaneously
• N_CHANNELS
  N_CHANNELS (r) register accessor: The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
• SNIFF_CTRL
  SNIFF_CTRL (rw) register accessor: Sniffer Control
• SNIFF_DATA
  SNIFF_DATA (rw) register accessor: Data accumulator for sniff hardware
  Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
• TIMER0
  TIMER0 (rw) register accessor: Pacing (X/Y) Fractional Timer
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
• TIMER1
  TIMER1 (rw) register accessor: Pacing (X/Y) Fractional Timer
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
• TIMER2
  TIMER2 (rw) register accessor: Pacing (X/Y) Fractional Timer
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
• TIMER3
  TIMER3 (rw) register accessor: Pacing (X/Y) Fractional Timer
  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.