Struct Wptcr
#[repr(transparent)]pub struct Wptcr(pub u32);Expand description
wrap timing configuration register
Tuple Fields§
§0: u32Implementations§
§impl Wptcr
impl Wptcr
pub const fn dcyc(&self) -> u8
pub const fn dcyc(&self) -> u8
Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.
pub fn set_dcyc(&mut self, val: u8)
pub fn set_dcyc(&mut self, val: u8)
Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.
pub const fn dhqc(&self) -> bool
pub const fn dhqc(&self) -> bool
Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.
pub fn set_dhqc(&mut self, val: bool)
pub fn set_dhqc(&mut self, val: bool)
Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.
pub const fn sshift(&self) -> SampleShift
pub const fn sshift(&self) -> SampleShift
Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1).
pub fn set_sshift(&mut self, val: SampleShift)
pub fn set_sshift(&mut self, val: SampleShift)
Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1).