rtic/macros/src/codegen/util.rs

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use core::sync::atomic::{AtomicUsize, Ordering};
use crate::syntax::{ast::App, Context};
use proc_macro2::{Span, TokenStream as TokenStream2};
use quote::quote;
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use syn::{Attribute, Ident};
const RTIC_INTERNAL: &str = "__rtic_internal";
/// Generates a `Mutex` implementation
pub fn impl_mutex(
app: &App,
cfgs: &[Attribute],
resources_prefix: bool,
name: &Ident,
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ty: &TokenStream2,
ceiling: u8,
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ptr: &TokenStream2,
) -> TokenStream2 {
let path = if resources_prefix {
quote!(shared_resources::#name)
} else {
quote!(#name)
};
let device = &app.args.device;
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let masks_name = priority_masks_ident();
quote!(
#(#cfgs)*
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impl<'a> rtic::Mutex for #path<'a> {
type T = #ty;
#[inline(always)]
fn lock<RTIC_INTERNAL_R>(&mut self, f: impl FnOnce(&mut #ty) -> RTIC_INTERNAL_R) -> RTIC_INTERNAL_R {
/// Priority ceiling
const CEILING: u8 = #ceiling;
unsafe {
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rtic::export::lock(
#ptr,
CEILING,
#device::NVIC_PRIO_BITS,
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&#masks_name,
f,
)
}
}
}
)
}
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pub fn interrupt_ident() -> Ident {
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let span = Span::call_site();
Ident::new("interrupt", span)
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}
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/// Whether `name` is an exception with configurable priority
pub fn is_exception(name: &Ident) -> bool {
let s = name.to_string();
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matches!(
&*s,
"MemoryManagement"
| "BusFault"
| "UsageFault"
| "SecureFault"
| "SVCall"
| "DebugMonitor"
| "PendSV"
| "SysTick"
)
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}
/// Mark a name as internal
pub fn mark_internal_name(name: &str) -> Ident {
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Ident::new(&format!("{RTIC_INTERNAL}_{name}"), Span::call_site())
}
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/// Generate an internal identifier for tasks
pub fn internal_task_ident(task: &Ident, ident_name: &str) -> Ident {
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mark_internal_name(&format!("{task}_{ident_name}"))
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}
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fn link_section_index() -> usize {
static INDEX: AtomicUsize = AtomicUsize::new(0);
INDEX.fetch_add(1, Ordering::Relaxed)
}
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/// Add `link_section` attribute
pub fn link_section_uninit() -> TokenStream2 {
let section = format!(".uninit.rtic{}", link_section_index());
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quote!(#[link_section = #section])
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}
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/// Get the ident for the name of the task
pub fn get_task_name(ctxt: Context, app: &App) -> Ident {
let s = match ctxt {
Context::Init => app.init.name.to_string(),
Context::Idle => app
.idle
.as_ref()
.expect("RTIC-ICE: unable to find idle name")
.name
.to_string(),
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Context::HardwareTask(ident) | Context::SoftwareTask(ident) => ident.to_string(),
};
Ident::new(&s, Span::call_site())
}
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/// Generates a pre-reexport identifier for the "shared resources" struct
pub fn shared_resources_ident(ctxt: Context, app: &App) -> Ident {
let mut s = match ctxt {
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Context::Init => app.init.name.to_string(),
Context::Idle => app
.idle
.as_ref()
.expect("RTIC-ICE: unable to find idle name")
.name
.to_string(),
Context::HardwareTask(ident) | Context::SoftwareTask(ident) => ident.to_string(),
};
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s.push_str("SharedResources");
mark_internal_name(&s)
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}
/// Generates a pre-reexport identifier for the "local resources" struct
pub fn local_resources_ident(ctxt: Context, app: &App) -> Ident {
let mut s = match ctxt {
Context::Init => app.init.name.to_string(),
Context::Idle => app
.idle
.as_ref()
.expect("RTIC-ICE: unable to find idle name")
.name
.to_string(),
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Context::HardwareTask(ident) | Context::SoftwareTask(ident) => ident.to_string(),
};
s.push_str("LocalResources");
mark_internal_name(&s)
}
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/// Suffixed identifier
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pub fn suffixed(name: &str) -> Ident {
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let span = Span::call_site();
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Ident::new(name, span)
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}
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pub fn static_shared_resource_ident(name: &Ident) -> Ident {
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mark_internal_name(&format!("shared_resource_{name}"))
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}
Remove use of basepri register on thumbv8m.base The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
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/// Generates an Ident for the number of 32 bit chunks used for Mask storage.
pub fn priority_mask_chunks_ident() -> Ident {
mark_internal_name("MASK_CHUNKS")
}
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pub fn priority_masks_ident() -> Ident {
mark_internal_name("MASKS")
}
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pub fn static_local_resource_ident(name: &Ident) -> Ident {
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mark_internal_name(&format!("local_resource_{name}"))
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}
pub fn declared_static_local_resource_ident(name: &Ident, task_name: &Ident) -> Ident {
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mark_internal_name(&format!("local_{task_name}_{name}"))
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}
pub fn need_to_lock_ident(name: &Ident) -> Ident {
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Ident::new(&format!("{name}_that_needs_to_be_locked"), name.span())
}
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pub fn zero_prio_dispatcher_ident() -> Ident {
Ident::new("__rtic_internal_async_0_prio_dispatcher", Span::call_site())
}
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/// The name to get better RT flag errors
pub fn rt_err_ident() -> Ident {
Ident::new(
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"you_must_enable_the_rt_feature_for_the_pac_in_your_cargo_toml",
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Span::call_site(),
)
}