rtic/macros/src/codegen/shared_resources.rs

197 lines
6.2 KiB
Rust
Raw Normal View History

2022-04-20 10:46:03 +02:00
use crate::{analyze::Analysis, check::Extra, codegen::util};
use proc_macro2::TokenStream as TokenStream2;
use quote::quote;
2020-09-01 16:39:05 +02:00
use rtic_syntax::{analyze::Ownership, ast::App};
2022-04-20 10:46:03 +02:00
use std::collections::HashMap;
2021-07-05 21:40:01 +02:00
/// Generates `static` variables and shared resource proxies
pub fn codegen(
app: &App,
analysis: &Analysis,
extra: &Extra,
) -> (
2021-04-08 18:25:09 +02:00
// mod_app -- the `static` variables behind the proxies
Vec<TokenStream2>,
// mod_resources -- the `resources` module
TokenStream2,
) {
2020-10-01 18:17:15 +02:00
let mut mod_app = vec![];
let mut mod_resources = vec![];
2021-07-06 22:47:48 +02:00
for (name, res) in &app.shared_resources {
let cfgs = &res.cfgs;
let ty = &res.ty;
2021-12-25 13:17:16 +01:00
let mangled_name = &util::static_shared_resource_ident(name);
2021-07-06 22:47:48 +02:00
let attrs = &res.attrs;
2021-04-08 18:25:09 +02:00
// late resources in `util::link_section_uninit`
// unless user specifies custom link section
let section = if attrs.iter().any(|attr| attr.path.is_ident("link_section")) {
None
2022-07-27 20:25:34 +02:00
} else {
Some(util::link_section_uninit())
};
2021-07-06 22:47:48 +02:00
// For future use
// let doc = format!(" RTIC internal: {}:{}", file!(), line!());
mod_app.push(quote!(
#[allow(non_camel_case_types)]
2021-07-06 22:47:48 +02:00
#[allow(non_upper_case_globals)]
// #[doc = #doc]
#[doc(hidden)]
#(#attrs)*
#(#cfgs)*
#section
static #mangled_name: rtic::RacyCell<core::mem::MaybeUninit<#ty>> = rtic::RacyCell::new(core::mem::MaybeUninit::uninit());
));
2021-04-22 18:38:42 +02:00
// For future use
2021-04-08 18:25:09 +02:00
// let doc = format!(" RTIC internal: {}:{}", file!(), line!());
let shared_name = util::need_to_lock_ident(name);
2021-07-06 22:47:48 +02:00
if !res.properties.lock_free {
2019-07-10 22:42:44 +02:00
mod_resources.push(quote!(
2021-04-08 18:25:09 +02:00
// #[doc = #doc]
#[doc(hidden)]
2019-07-10 22:42:44 +02:00
#[allow(non_camel_case_types)]
#(#cfgs)*
pub struct #shared_name<'a> {
2019-07-10 22:42:44 +02:00
priority: &'a Priority,
}
#(#cfgs)*
impl<'a> #shared_name<'a> {
2019-07-10 22:42:44 +02:00
#[inline(always)]
pub unsafe fn new(priority: &'a Priority) -> Self {
#shared_name { priority }
}
2019-07-10 22:42:44 +02:00
#[inline(always)]
pub unsafe fn priority(&self) -> &Priority {
self.priority
}
2019-07-10 22:42:44 +02:00
}
));
2021-07-06 22:47:48 +02:00
let ptr = quote!(
#(#cfgs)*
2021-11-03 08:27:05 +01:00
#mangled_name.get_mut() as *mut _
2021-07-06 22:47:48 +02:00
);
2019-07-10 22:42:44 +02:00
let ceiling = match analysis.ownerships.get(name) {
2022-02-18 19:38:48 +01:00
Some(Ownership::Owned { priority } | Ownership::CoOwned { priority }) => *priority,
Some(Ownership::Contended { ceiling }) => *ceiling,
None => 0,
};
2021-04-22 18:38:42 +02:00
// For future use
2021-04-08 18:25:09 +02:00
// let doc = format!(" RTIC internal ({} resource): {}:{}", doc, file!(), line!());
2020-10-01 18:17:15 +02:00
mod_app.push(util::impl_mutex(
2019-07-10 22:42:44 +02:00
extra,
cfgs,
true,
&shared_name,
2022-02-18 19:38:48 +01:00
&quote!(#ty),
ceiling,
2022-02-18 19:38:48 +01:00
&ptr,
2019-07-10 22:42:44 +02:00
));
}
}
let mod_resources = if mod_resources.is_empty() {
quote!()
} else {
2021-07-06 22:47:48 +02:00
quote!(mod shared_resources {
2020-06-11 19:18:29 +02:00
use rtic::export::Priority;
#(#mod_resources)*
})
};
// Computing mapping of used interrupts to masks
let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id));
2022-04-20 10:46:03 +02:00
let mut prio_to_masks = HashMap::new();
let device = &extra.device;
let mut uses_exceptions_with_resources = false;
Remove use of basepri register on thumbv8m.base The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-03 18:24:11 +02:00
let mut mask_ids = Vec::new();
for (&priority, name) in interrupt_ids.chain(app.hardware_tasks.values().flat_map(|task| {
if !util::is_exception(&task.args.binds) {
Some((&task.args.priority, &task.args.binds))
} else {
// If any resource to the exception uses non-lock-free or non-local resources this is
// not allwed on thumbv6.
uses_exceptions_with_resources = uses_exceptions_with_resources
|| task
.args
.shared_resources
.iter()
.map(|(ident, access)| {
if access.is_exclusive() {
if let Some(r) = app.shared_resources.get(ident) {
!r.properties.lock_free
} else {
false
}
} else {
false
}
})
.any(|v| v);
None
}
})) {
#[allow(clippy::or_fun_call)]
2022-04-20 10:46:03 +02:00
let v = prio_to_masks.entry(priority - 1).or_insert(Vec::new());
v.push(quote!(#device::Interrupt::#name as u32));
Remove use of basepri register on thumbv8m.base The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-03 18:24:11 +02:00
mask_ids.push(quote!(#device::Interrupt::#name as u32));
}
Remove use of basepri register on thumbv8m.base The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-03 18:24:11 +02:00
// Call rtic::export::create_mask([Mask; N]), where the array is the list of shifts
2022-04-20 10:46:03 +02:00
let mut mask_arr = Vec::new();
Remove use of basepri register on thumbv8m.base The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-03 18:24:11 +02:00
// NOTE: 0..3 assumes max 4 priority levels according to M0, M23 spec
2022-04-20 10:46:03 +02:00
for i in 0..3 {
let v = if let Some(v) = prio_to_masks.get(&i) {
v.clone()
} else {
Vec::new()
};
mask_arr.push(quote!(
rtic::export::create_mask([#(#v),*])
));
}
Remove use of basepri register on thumbv8m.base The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-03 18:24:11 +02:00
// Generate a constant for the number of chunks needed by Mask.
let chunks_name = util::priority_mask_chunks_ident();
mod_app.push(quote!(
#[doc(hidden)]
#[allow(non_upper_case_globals)]
const #chunks_name: usize = rtic::export::compute_mask_chunks([#(#mask_ids),*]);
));
2022-04-20 10:46:03 +02:00
let masks_name = util::priority_masks_ident();
mod_app.push(quote!(
2022-04-20 10:46:03 +02:00
#[doc(hidden)]
2022-05-10 13:38:23 +02:00
#[allow(non_upper_case_globals)]
Remove use of basepri register on thumbv8m.base The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-03 18:24:11 +02:00
const #masks_name: [rtic::export::Mask<#chunks_name>; 3] = [#(#mask_arr),*];
));
if uses_exceptions_with_resources {
mod_app.push(quote!(
#[doc(hidden)]
2022-05-10 13:38:23 +02:00
#[allow(non_upper_case_globals)]
Remove use of basepri register on thumbv8m.base The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-03 18:24:11 +02:00
const __rtic_internal_V6_ERROR: () = rtic::export::no_basepri_panic();
));
}
2020-10-21 20:20:26 +02:00
(mod_app, mod_resources)
}