mirror of
https://github.com/rtic-rs/rtic.git
synced 2025-12-21 07:15:32 +01:00
1 line
No EOL
5.7 KiB
HTML
1 line
No EOL
5.7 KiB
HTML
<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="API documentation for the Rust `regs` mod in crate `stm32_metapac`."><title>stm32_metapac::pwr::regs - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="stm32_metapac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module regs</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../stm32_metapac/index.html">stm32_<wbr>metapac</a><span class="version">15.0.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module regs</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In stm32_<wbr>metapac::<wbr>pwr</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../../index.html">stm32_metapac</a>::<wbr><a href="../index.html">pwr</a></div><h1>Module <span>regs</span> <button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"></span></div><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><dl class="item-table"><dt><a class="struct" href="struct.Cpucr.html" title="struct stm32_metapac::pwr::regs::Cpucr">Cpucr</a></dt><dd>This register allows controlling CPU1 power.</dd><dt><a class="struct" href="struct.Cr1.html" title="struct stm32_metapac::pwr::regs::Cr1">Cr1</a></dt><dd>PWR control register 1</dd><dt><a class="struct" href="struct.Cr2.html" title="struct stm32_metapac::pwr::regs::Cr2">Cr2</a></dt><dd>This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.</dd><dt><a class="struct" href="struct.Cr3.html" title="struct stm32_metapac::pwr::regs::Cr3">Cr3</a></dt><dd>Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.</dd><dt><a class="struct" href="struct.Csr1.html" title="struct stm32_metapac::pwr::regs::Csr1">Csr1</a></dt><dd>PWR control status register 1</dd><dt><a class="struct" href="struct.D3cr.html" title="struct stm32_metapac::pwr::regs::D3cr">D3cr</a></dt><dd>This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software</dd><dt><a class="struct" href="struct.Wkupcr.html" title="struct stm32_metapac::pwr::regs::Wkupcr">Wkupcr</a></dt><dd>reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).</dd><dt><a class="struct" href="struct.Wkupepr.html" title="struct stm32_metapac::pwr::regs::Wkupepr">Wkupepr</a></dt><dd>Reset only by system reset, not reset by wakeup from Standby mode</dd><dt><a class="struct" href="struct.Wkupfr.html" title="struct stm32_metapac::pwr::regs::Wkupfr">Wkupfr</a></dt><dd>reset only by system reset, not reset by wakeup from Standby mode</dd></dl></section></div></main></body></html> |