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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="API documentation for the Rust `regs` mod in crate `stm32_metapac`."><title>stm32_metapac::eth::regs - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="stm32_metapac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module regs</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../stm32_metapac/index.html">stm32_<wbr>metapac</a><span class="version">15.0.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module regs</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In stm32_<wbr>metapac::<wbr>eth</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../../index.html">stm32_metapac</a>::<wbr><a href="../index.html">eth</a></div><h1>Module <span>regs</span> <button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"></span></div><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><dl class="item-table"><dt><a class="struct" href="struct.DmaccarxBr.html" title="struct stm32_metapac::eth::regs::DmaccarxBr">Dmaccarx<wbr>Br</a></dt><dd>Channel current application receive buffer register</dd><dt><a class="struct" href="struct.DmaccarxDr.html" title="struct stm32_metapac::eth::regs::DmaccarxDr">Dmaccarx<wbr>Dr</a></dt><dd>Channel current application receive descriptor register</dd><dt><a class="struct" href="struct.DmaccatxBr.html" title="struct stm32_metapac::eth::regs::DmaccatxBr">Dmaccatx<wbr>Br</a></dt><dd>Channel current application transmit buffer register</dd><dt><a class="struct" href="struct.DmaccatxDr.html" title="struct stm32_metapac::eth::regs::DmaccatxDr">Dmaccatx<wbr>Dr</a></dt><dd>Channel current application transmit descriptor register</dd><dt><a class="struct" href="struct.Dmaccr.html" title="struct stm32_metapac::eth::regs::Dmaccr">Dmaccr</a></dt><dd>Channel control register</dd><dt><a class="struct" href="struct.Dmacier.html" title="struct stm32_metapac::eth::regs::Dmacier">Dmacier</a></dt><dd>Channel interrupt enable register</dd><dt><a class="struct" href="struct.Dmacmfcr.html" title="struct stm32_metapac::eth::regs::Dmacmfcr">Dmacmfcr</a></dt><dd>Channel missed frame count register</dd><dt><a class="struct" href="struct.DmacrxCr.html" title="struct stm32_metapac::eth::regs::DmacrxCr">Dmacrx<wbr>Cr</a></dt><dd>Channel receive control register</dd><dt><a class="struct" href="struct.DmacrxDlar.html" title="struct stm32_metapac::eth::regs::DmacrxDlar">Dmacrx<wbr>Dlar</a></dt><dd>Channel Rx descriptor list address register</dd><dt><a class="struct" href="struct.DmacrxDtpr.html" title="struct stm32_metapac::eth::regs::DmacrxDtpr">Dmacrx<wbr>Dtpr</a></dt><dd>Channel Rx descriptor tail pointer register</dd><dt><a class="struct" href="struct.DmacrxIwtr.html" title="struct stm32_metapac::eth::regs::DmacrxIwtr">Dmacrx<wbr>Iwtr</a></dt><dd>Channel Rx interrupt watchdog timer register</dd><dt><a class="struct" href="struct.DmacrxRlr.html" title="struct stm32_metapac::eth::regs::DmacrxRlr">Dmacrx<wbr>Rlr</a></dt><dd>Channel Rx descriptor ring length register</dd><dt><a class="struct" href="struct.Dmacsr.html" title="struct stm32_metapac::eth::regs::Dmacsr">Dmacsr</a></dt><dd>Channel status register</dd><dt><a class="struct" href="struct.DmactxCr.html" title="struct stm32_metapac::eth::regs::DmactxCr">Dmactx<wbr>Cr</a></dt><dd>Channel transmit control register</dd><dt><a class="struct" href="struct.DmactxDlar.html" title="struct stm32_metapac::eth::regs::DmactxDlar">Dmactx<wbr>Dlar</a></dt><dd>Channel Tx descriptor list address register</dd><dt><a class="struct" href="struct.DmactxDtpr.html" title="struct stm32_metapac::eth::regs::DmactxDtpr">Dmactx<wbr>Dtpr</a></dt><dd>Channel Tx descriptor tail pointer register</dd><dt><a class="struct" href="struct.DmactxRlr.html" title="struct stm32_metapac::eth::regs::DmactxRlr">Dmactx<wbr>Rlr</a></dt><dd>Channel Tx descriptor ring length register</dd><dt><a class="struct" href="struct.Dmadsr.html" title="struct stm32_metapac::eth::regs::Dmadsr">Dmadsr</a></dt><dd>Debug status register</dd><dt><a class="struct" href="struct.Dmaisr.html" title="struct stm32_metapac::eth::regs::Dmaisr">Dmaisr</a></dt><dd>Interrupt status register</dd><dt><a class="struct" href="struct.Dmamr.html" title="struct stm32_metapac::eth::regs::Dmamr">Dmamr</a></dt><dd>DMA mode register</dd><dt><a class="struct" href="struct.Dmasbmr.html" title="struct stm32_metapac::eth::regs::Dmasbmr">Dmasbmr</a></dt><dd>System bus mode register</dd><dt><a class="struct" href="struct.Mac1ustcr.html" title="struct stm32_metapac::eth::regs::Mac1ustcr">Mac1ustcr</a></dt><dd>1-microsecond-tick counter register</dd><dt><a class="struct" href="struct.Maca0hr.html" title="struct stm32_metapac::eth::regs::Maca0hr">Maca0hr</a></dt><dd>Address 0 high register</dd><dt><a class="struct" href="struct.Maca0lr.html" title="struct stm32_metapac::eth::regs::Maca0lr">Maca0lr</a></dt><dd>Address 0 low register</dd><dt><a class="struct" href="struct.Macacr.html" title="struct stm32_metapac::eth::regs::Macacr">Macacr</a></dt><dd>Auxiliary control register</dd><dt><a class="struct" href="struct.Macahr.html" title="struct stm32_metapac::eth::regs::Macahr">Macahr</a></dt><dd>Address 1/2/3 high register</dd><dt><a class="struct" href="struct.Macalr.html" title="struct stm32_metapac::eth::regs::Macalr">Macalr</a></dt><dd>Address 1/2/3 low register</dd><dt><a class="struct" href="struct.Macarpar.html" title="struct stm32_metapac::eth::regs::Macarpar">Macarpar</a></dt><dd>ARP address register</dd><dt><a class="struct" href="struct.Macatsnr.html" title="struct stm32_metapac::eth::regs::Macatsnr">Macatsnr</a></dt><dd>Auxiliary timestamp nanoseconds register</dd><dt><a class="struct" href="struct.Macatssr.html" title="struct stm32_metapac::eth::regs::Macatssr">Macatssr</a></dt><dd>Auxiliary timestamp seconds register</dd><dt><a class="struct" href="struct.Maccr.html" title="struct stm32_metapac::eth::regs::Maccr">Maccr</a></dt><dd>Operating mode configuration register</dd><dt><a class="struct" href="struct.Macdr.html" title="struct stm32_metapac::eth::regs::Macdr">Macdr</a></dt><dd>Debug register</dd><dt><a class="struct" href="struct.Macecr.html" title="struct stm32_metapac::eth::regs::Macecr">Macecr</a></dt><dd>Extended operating mode configuration register</dd><dt><a class="struct" href="struct.Machtr.html" title="struct stm32_metapac::eth::regs::Machtr">Machtr</a></dt><dd>Hash Table 0/1 register</dd><dt><a class="struct" href="struct.Machwf1r.html" title="struct stm32_metapac::eth::regs::Machwf1r">Machwf1r</a></dt><dd>HW feature 1 register</dd><dt><a class="struct" href="struct.Machwf2r.html" title="struct stm32_metapac::eth::regs::Machwf2r">Machwf2r</a></dt><dd>HW feature 2 register</dd><dt><a class="struct" href="struct.Macier.html" title="struct stm32_metapac::eth::regs::Macier">Macier</a></dt><dd>Interrupt enable register</dd><dt><a class="struct" href="struct.Macisr.html" title="struct stm32_metapac::eth::regs::Macisr">Macisr</a></dt><dd>Interrupt status register</dd><dt><a class="struct" href="struct.Macivir.html" title="struct stm32_metapac::eth::regs::Macivir">Macivir</a></dt><dd>Inner VLAN inclusion register</dd><dt><a class="struct" href="struct.Macl3a00r.html" title="struct stm32_metapac::eth::regs::Macl3a00r">Macl3a00r</a></dt><dd>MACL3A00R</dd><dt><a class="struct" href="struct.Macl3a01r.html" title="struct stm32_metapac::eth::regs::Macl3a01r">Macl3a01r</a></dt><dd>Layer3 address 0 filter 1 Register</dd><dt><a class="struct" href="struct.Macl3a20.html" title="struct stm32_metapac::eth::regs::Macl3a20">Macl3a20</a></dt><dd>Layer3 Address 2 filter 0 register</dd><dt><a class="struct" href="struct.Macl3a30.html" title="struct stm32_metapac::eth::regs::Macl3a30">Macl3a30</a></dt><dd>Layer3 Address 3 filter 0 register</dd><dt><a class="struct" href="struct.Macl3a10r.html" title="struct stm32_metapac::eth::regs::Macl3a10r">Macl3a10r</a></dt><dd>Layer3 address 1 filter 0 register</dd><dt><a class="struct" href="struct.Macl3a11r.html" title="struct stm32_metapac::eth::regs::Macl3a11r">Macl3a11r</a></dt><dd>Layer3 address 1 filter 1 register</dd><dt><a class="struct" href="struct.Macl3a21r.html" title="struct stm32_metapac::eth::regs::Macl3a21r">Macl3a21r</a></dt><dd>Layer3 address 2 filter 1 Register</dd><dt><a class="struct" href="struct.Macl3a31r.html" title="struct stm32_metapac::eth::regs::Macl3a31r">Macl3a31r</a></dt><dd>Layer3 address 3 filter 1 register</dd><dt><a class="struct" href="struct.Macl3l4c0r.html" title="struct stm32_metapac::eth::regs::Macl3l4c0r">Macl3l4c0r</a></dt><dd>L3 and L4 control 0 register</dd><dt><a class="struct" href="struct.Macl3l4c1r.html" title="struct stm32_metapac::eth::regs::Macl3l4c1r">Macl3l4c1r</a></dt><dd>L3 and L4 control 1 register</dd><dt><a class="struct" href="struct.Macl4a0r.html" title="struct stm32_metapac::eth::regs::Macl4a0r">Macl4a0r</a></dt><dd>Layer4 address filter 0 register</dd><dt><a class="struct" href="struct.Macl4a1r.html" title="struct stm32_metapac::eth::regs::Macl4a1r">Macl4a1r</a></dt><dd>Layer 4 address filter 1 register</dd><dt><a class="struct" href="struct.Maclcsr.html" title="struct stm32_metapac::eth::regs::Maclcsr">Maclcsr</a></dt><dd>LPI control status register</dd><dt><a class="struct" href="struct.Macletr.html" title="struct stm32_metapac::eth::regs::Macletr">Macletr</a></dt><dd>LPI entry timer register</dd><dt><a class="struct" href="struct.Maclmir.html" title="struct stm32_metapac::eth::regs::Maclmir">Maclmir</a></dt><dd>Log message interval register</dd><dt><a class="struct" href="struct.Macltcr.html" title="struct stm32_metapac::eth::regs::Macltcr">Macltcr</a></dt><dd>LPI timers control register</dd><dt><a class="struct" href="struct.Macmdioar.html" title="struct stm32_metapac::eth::regs::Macmdioar">Macmdioar</a></dt><dd>MDIO address register</dd><dt><a class="struct" href="struct.Macmdiodr.html" title="struct stm32_metapac::eth::regs::Macmdiodr">Macmdiodr</a></dt><dd>MDIO data register</dd><dt><a class="struct" href="struct.Macpcsr.html" title="struct stm32_metapac::eth::regs::Macpcsr">Macpcsr</a></dt><dd>PMT control status register</dd><dt><a class="struct" href="struct.Macpfr.html" title="struct stm32_metapac::eth::regs::Macpfr">Macpfr</a></dt><dd>Packet filtering control register</dd><dt><a class="struct" href="struct.Macpocr.html" title="struct stm32_metapac::eth::regs::Macpocr">Macpocr</a></dt><dd>PTP Offload control register</dd><dt><a class="struct" href="struct.Macppscr.html" title="struct stm32_metapac::eth::regs::Macppscr">Macppscr</a></dt><dd>PPS control register</dd><dt><a class="struct" href="struct.Macppsir.html" title="struct stm32_metapac::eth::regs::Macppsir">Macppsir</a></dt><dd>PPS interval register</dd><dt><a class="struct" href="struct.Macppsttnr.html" title="struct stm32_metapac::eth::regs::Macppsttnr">Macppsttnr</a></dt><dd>PPS target time nanoseconds register</dd><dt><a class="struct" href="struct.Macppsttsr.html" title="struct stm32_metapac::eth::regs::Macppsttsr">Macppsttsr</a></dt><dd>PPS target time seconds register</dd><dt><a class="struct" href="struct.Macppswr.html" title="struct stm32_metapac::eth::regs::Macppswr">Macppswr</a></dt><dd>PPS width register</dd><dt><a class="struct" href="struct.MacqtxFcr.html" title="struct stm32_metapac::eth::regs::MacqtxFcr">Macqtx<wbr>Fcr</a></dt><dd>Tx Queue flow control register</dd><dt><a class="struct" href="struct.Macrwkpfr.html" title="struct stm32_metapac::eth::regs::Macrwkpfr">Macrwkpfr</a></dt><dd>Remove wakeup packet filter register</dd><dt><a class="struct" href="struct.MacrxFcr.html" title="struct stm32_metapac::eth::regs::MacrxFcr">Macrx<wbr>Fcr</a></dt><dd>Rx flow control register</dd><dt><a class="struct" href="struct.MacrxTxSr.html" title="struct stm32_metapac::eth::regs::MacrxTxSr">Macrx<wbr>TxSr</a></dt><dd>Rx Tx status register</dd><dt><a class="struct" href="struct.Macspi0r.html" title="struct stm32_metapac::eth::regs::Macspi0r">Macspi0r</a></dt><dd>PTP Source Port Identity 0 Register</dd><dt><a class="struct" href="struct.Macspi1r.html" title="struct stm32_metapac::eth::regs::Macspi1r">Macspi1r</a></dt><dd>PTP Source port identity 1 register</dd><dt><a class="struct" href="struct.Macspi2r.html" title="struct stm32_metapac::eth::regs::Macspi2r">Macspi2r</a></dt><dd>PTP Source port identity 2 register</dd><dt><a class="struct" href="struct.Macssir.html" title="struct stm32_metapac::eth::regs::Macssir">Macssir</a></dt><dd>Sub-second increment register</dd><dt><a class="struct" href="struct.Macstnr.html" title="struct stm32_metapac::eth::regs::Macstnr">Macstnr</a></dt><dd>System time nanoseconds register</dd><dt><a class="struct" href="struct.Macstnur.html" title="struct stm32_metapac::eth::regs::Macstnur">Macstnur</a></dt><dd>System time nanoseconds update register</dd><dt><a class="struct" href="struct.Macstsr.html" title="struct stm32_metapac::eth::regs::Macstsr">Macstsr</a></dt><dd>System time seconds register</dd><dt><a class="struct" href="struct.Macstsur.html" title="struct stm32_metapac::eth::regs::Macstsur">Macstsur</a></dt><dd>System time seconds update register</dd><dt><a class="struct" href="struct.Mactsar.html" title="struct stm32_metapac::eth::regs::Mactsar">Mactsar</a></dt><dd>Timestamp addend register</dd><dt><a class="struct" href="struct.Mactscr.html" title="struct stm32_metapac::eth::regs::Mactscr">Mactscr</a></dt><dd>Timestamp control Register</dd><dt><a class="struct" href="struct.Mactseacr.html" title="struct stm32_metapac::eth::regs::Mactseacr">Mactseacr</a></dt><dd>Timestamp Egress asymmetric correction register</dd><dt><a class="struct" href="struct.Mactsecnr.html" title="struct stm32_metapac::eth::regs::Mactsecnr">Mactsecnr</a></dt><dd>Timestamp Egress correction nanosecond register</dd><dt><a class="struct" href="struct.Mactsiacr.html" title="struct stm32_metapac::eth::regs::Mactsiacr">Mactsiacr</a></dt><dd>Timestamp Ingress asymmetric correction register</dd><dt><a class="struct" href="struct.Mactsicnr.html" title="struct stm32_metapac::eth::regs::Mactsicnr">Mactsicnr</a></dt><dd>Timestamp Ingress correction nanosecond register</dd><dt><a class="struct" href="struct.Mactssr.html" title="struct stm32_metapac::eth::regs::Mactssr">Mactssr</a></dt><dd>Timestamp status register</dd><dt><a class="struct" href="struct.MactxTssnr.html" title="struct stm32_metapac::eth::regs::MactxTssnr">Mactx<wbr>Tssnr</a></dt><dd>Tx timestamp status nanoseconds register</dd><dt><a class="struct" href="struct.MactxTsssr.html" title="struct stm32_metapac::eth::regs::MactxTsssr">Mactx<wbr>Tsssr</a></dt><dd>Tx timestamp status seconds register</dd><dt><a class="struct" href="struct.Macvhtr.html" title="struct stm32_metapac::eth::regs::Macvhtr">Macvhtr</a></dt><dd>VLAN Hash table register</dd><dt><a class="struct" href="struct.Macvir.html" title="struct stm32_metapac::eth::regs::Macvir">Macvir</a></dt><dd>VLAN inclusion register</dd><dt><a class="struct" href="struct.Macvr.html" title="struct stm32_metapac::eth::regs::Macvr">Macvr</a></dt><dd>Version register</dd><dt><a class="struct" href="struct.Macvtr.html" title="struct stm32_metapac::eth::regs::Macvtr">Macvtr</a></dt><dd>VLAN tag register</dd><dt><a class="struct" href="struct.Macwtr.html" title="struct stm32_metapac::eth::regs::Macwtr">Macwtr</a></dt><dd>Watchdog timeout register</dd><dt><a class="struct" href="struct.MmcControl.html" title="struct stm32_metapac::eth::regs::MmcControl">MmcControl</a></dt><dd>MMC control register</dd><dt><a class="struct" href="struct.MmcRxInterrupt.html" title="struct stm32_metapac::eth::regs::MmcRxInterrupt">MmcRx<wbr>Interrupt</a></dt><dd>MMC Rx interrupt register</dd><dt><a class="struct" href="struct.MmcRxInterruptMask.html" title="struct stm32_metapac::eth::regs::MmcRxInterruptMask">MmcRx<wbr>Interrupt<wbr>Mask</a></dt><dd>MMC Rx interrupt mask register</dd><dt><a class="struct" href="struct.MmcTxInterrupt.html" title="struct stm32_metapac::eth::regs::MmcTxInterrupt">MmcTx<wbr>Interrupt</a></dt><dd>MMC Tx interrupt register</dd><dt><a class="struct" href="struct.MmcTxInterruptMask.html" title="struct stm32_metapac::eth::regs::MmcTxInterruptMask">MmcTx<wbr>Interrupt<wbr>Mask</a></dt><dd>MMC Tx interrupt mask register</dd><dt><a class="struct" href="struct.Mtlisr.html" title="struct stm32_metapac::eth::regs::Mtlisr">Mtlisr</a></dt><dd>Interrupt status Register</dd><dt><a class="struct" href="struct.Mtlomr.html" title="struct stm32_metapac::eth::regs::Mtlomr">Mtlomr</a></dt><dd>Operating mode Register</dd><dt><a class="struct" href="struct.Mtlqicsr.html" title="struct stm32_metapac::eth::regs::Mtlqicsr">Mtlqicsr</a></dt><dd>Queue interrupt control status Register</dd><dt><a class="struct" href="struct.MtlrxQdr.html" title="struct stm32_metapac::eth::regs::MtlrxQdr">Mtlrx<wbr>Qdr</a></dt><dd>Rx queue debug register</dd><dt><a class="struct" href="struct.MtlrxQmpocr.html" title="struct stm32_metapac::eth::regs::MtlrxQmpocr">Mtlrx<wbr>Qmpocr</a></dt><dd>Rx queue missed packet and overflow counter register</dd><dt><a class="struct" href="struct.MtlrxQomr.html" title="struct stm32_metapac::eth::regs::MtlrxQomr">Mtlrx<wbr>Qomr</a></dt><dd>Rx queue operating mode register</dd><dt><a class="struct" href="struct.MtltxQdr.html" title="struct stm32_metapac::eth::regs::MtltxQdr">Mtltx<wbr>Qdr</a></dt><dd>Tx queue debug Register</dd><dt><a class="struct" href="struct.MtltxQomr.html" title="struct stm32_metapac::eth::regs::MtltxQomr">Mtltx<wbr>Qomr</a></dt><dd>Tx queue operating mode Register</dd><dt><a class="struct" href="struct.MtltxQur.html" title="struct stm32_metapac::eth::regs::MtltxQur">Mtltx<wbr>Qur</a></dt><dd>Tx queue underflow register</dd><dt><a class="struct" href="struct.RxAlignmentErrorPackets.html" title="struct stm32_metapac::eth::regs::RxAlignmentErrorPackets">RxAlignment<wbr>Error<wbr>Packets</a></dt><dd>Rx alignment error packets register</dd><dt><a class="struct" href="struct.RxCrcErrorPackets.html" title="struct stm32_metapac::eth::regs::RxCrcErrorPackets">RxCrc<wbr>Error<wbr>Packets</a></dt><dd>Rx CRC error packets register</dd><dt><a class="struct" href="struct.RxLpiTranCntr.html" title="struct stm32_metapac::eth::regs::RxLpiTranCntr">RxLpi<wbr>Tran<wbr>Cntr</a></dt><dd>Rx LPI transition counter register</dd><dt><a class="struct" href="struct.RxLpiUsecCntr.html" title="struct stm32_metapac::eth::regs::RxLpiUsecCntr">RxLpi<wbr>Usec<wbr>Cntr</a></dt><dd>Rx LPI microsecond counter register</dd><dt><a class="struct" href="struct.RxUnicastPacketsGood.html" title="struct stm32_metapac::eth::regs::RxUnicastPacketsGood">RxUnicast<wbr>Packets<wbr>Good</a></dt><dd>Rx unicast packets good register</dd><dt><a class="struct" href="struct.TxLpiTranCntr.html" title="struct stm32_metapac::eth::regs::TxLpiTranCntr">TxLpi<wbr>Tran<wbr>Cntr</a></dt><dd>Tx LPI transition counter register</dd><dt><a class="struct" href="struct.TxLpiUsecCntr.html" title="struct stm32_metapac::eth::regs::TxLpiUsecCntr">TxLpi<wbr>Usec<wbr>Cntr</a></dt><dd>Tx LPI microsecond timer register</dd><dt><a class="struct" href="struct.TxMultipleCollisionGoodPackets.html" title="struct stm32_metapac::eth::regs::TxMultipleCollisionGoodPackets">TxMultiple<wbr>Collision<wbr>Good<wbr>Packets</a></dt><dd>Tx multiple collision good packets register</dd><dt><a class="struct" href="struct.TxPacketCountGood.html" title="struct stm32_metapac::eth::regs::TxPacketCountGood">TxPacket<wbr>Count<wbr>Good</a></dt><dd>Tx packet count good register</dd><dt><a class="struct" href="struct.TxSingleCollisionGoodPackets.html" title="struct stm32_metapac::eth::regs::TxSingleCollisionGoodPackets">TxSingle<wbr>Collision<wbr>Good<wbr>Packets</a></dt><dd>Tx single collision good packets register</dd></dl></section></div></main></body></html> |