rtic/2/api/rp2040_pac/syscfg/index.html
github-merge-queue[bot] e04fb16c1b deploy: bbc37ca3fe
2025-11-12 19:06:49 +00:00

24 lines
No EOL
8 KiB
HTML
Raw Blame History

This file contains ambiguous Unicode characters

This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Register block for various chip control signals"><title>rp2040_pac::syscfg - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module syscfg</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module syscfg</a></h2><h3><a href="#modules">Module Items</a></h3><ul class="block"><li><a href="#modules" title="Modules">Modules</a></li><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2 class="in-crate"><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../index.html">rp2040_pac</a></div><h1>Module <span>syscfg</span>&nbsp;<button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../src/rp2040_pac/syscfg.rs.html#1-144">Source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Register block for various chip control signals</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><dl class="item-table"><dt><a class="mod" href="dbgforce/index.html" title="mod rp2040_pac::syscfg::dbgforce">dbgforce</a></dt><dd>Directly control the SWD debug port of either processor</dd><dt><a class="mod" href="mempowerdown/index.html" title="mod rp2040_pac::syscfg::mempowerdown">mempowerdown</a></dt><dd>Control power downs to memories. Set high to power down memories.<br />
Use with extreme caution</dd><dt><a class="mod" href="proc0_nmi_mask/index.html" title="mod rp2040_pac::syscfg::proc0_nmi_mask">proc0_<wbr>nmi_<wbr>mask</a></dt><dd>Processor core 0 NMI source mask<br />
Set a bit high to enable NMI from that IRQ</dd><dt><a class="mod" href="proc1_nmi_mask/index.html" title="mod rp2040_pac::syscfg::proc1_nmi_mask">proc1_<wbr>nmi_<wbr>mask</a></dt><dd>Processor core 1 NMI source mask<br />
Set a bit high to enable NMI from that IRQ</dd><dt><a class="mod" href="proc_config/index.html" title="mod rp2040_pac::syscfg::proc_config">proc_<wbr>config</a></dt><dd>Configuration for processors</dd><dt><a class="mod" href="proc_in_sync_bypass/index.html" title="mod rp2040_pac::syscfg::proc_in_sync_bypass">proc_<wbr>in_<wbr>sync_<wbr>bypass</a></dt><dd>For each bit, if 1, bypass the input synchronizer between that GPIO<br />
and the GPIO input register in the SIO. The input synchronizers should<br />
generally be unbypassed, to avoid injecting metastabilities into processors.<br />
If youre feeling brave, you can bypass to save two cycles of input<br />
latency. This register applies to GPIO 0…29.</dd><dt><a class="mod" href="proc_in_sync_bypass_hi/index.html" title="mod rp2040_pac::syscfg::proc_in_sync_bypass_hi">proc_<wbr>in_<wbr>sync_<wbr>bypass_<wbr>hi</a></dt><dd>For each bit, if 1, bypass the input synchronizer between that GPIO<br />
and the GPIO input register in the SIO. The input synchronizers should<br />
generally be unbypassed, to avoid injecting metastabilities into processors.<br />
If youre feeling brave, you can bypass to save two cycles of input<br />
latency. This register applies to GPIO 30…35 (the QSPI IOs).</dd></dl><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><dl class="item-table"><dt><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::syscfg::RegisterBlock">Register<wbr>Block</a></dt><dd>Register block</dd></dl><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><dl class="item-table"><dt><a class="type" href="type.DBGFORCE.html" title="type rp2040_pac::syscfg::DBGFORCE">DBGFORCE</a></dt><dd>DBGFORCE (rw) register accessor: Directly control the SWD debug port of either processor</dd><dt><a class="type" href="type.MEMPOWERDOWN.html" title="type rp2040_pac::syscfg::MEMPOWERDOWN">MEMPOWERDOWN</a></dt><dd>MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories.<br />
Use with extreme caution</dd><dt><a class="type" href="type.PROC0_NMI_MASK.html" title="type rp2040_pac::syscfg::PROC0_NMI_MASK">PROC0_<wbr>NMI_<wbr>MASK</a></dt><dd>PROC0_NMI_MASK (rw) register accessor: Processor core 0 NMI source mask<br />
Set a bit high to enable NMI from that IRQ</dd><dt><a class="type" href="type.PROC1_NMI_MASK.html" title="type rp2040_pac::syscfg::PROC1_NMI_MASK">PROC1_<wbr>NMI_<wbr>MASK</a></dt><dd>PROC1_NMI_MASK (rw) register accessor: Processor core 1 NMI source mask<br />
Set a bit high to enable NMI from that IRQ</dd><dt><a class="type" href="type.PROC_CONFIG.html" title="type rp2040_pac::syscfg::PROC_CONFIG">PROC_<wbr>CONFIG</a></dt><dd>PROC_CONFIG (rw) register accessor: Configuration for processors</dd><dt><a class="type" href="type.PROC_IN_SYNC_BYPASS.html" title="type rp2040_pac::syscfg::PROC_IN_SYNC_BYPASS">PROC_<wbr>IN_<wbr>SYNC_<wbr>BYPASS</a></dt><dd>PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO<br />
and the GPIO input register in the SIO. The input synchronizers should<br />
generally be unbypassed, to avoid injecting metastabilities into processors.<br />
If youre feeling brave, you can bypass to save two cycles of input<br />
latency. This register applies to GPIO 0…29.</dd><dt><a class="type" href="type.PROC_IN_SYNC_BYPASS_HI.html" title="type rp2040_pac::syscfg::PROC_IN_SYNC_BYPASS_HI">PROC_<wbr>IN_<wbr>SYNC_<wbr>BYPASS_<wbr>HI</a></dt><dd>PROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO<br />
and the GPIO input register in the SIO. The input synchronizers should<br />
generally be unbypassed, to avoid injecting metastabilities into processors.<br />
If youre feeling brave, you can bypass to save two cycles of input<br />
latency. This register applies to GPIO 30…35 (the QSPI IOs).</dd></dl></section></div></main></body></html>