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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."><title>rp2040_pac::sio - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module sio</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module sio</a></h2><h3><a href="#modules">Module Items</a></h3><ul class="block"><li><a href="#modules" title="Modules">Modules</a></li><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2 class="in-crate"><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../index.html">rp2040_pac</a></div><h1>Module <span>sio</span>&nbsp;<button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../src/rp2040_pac/sio.rs.html#1-1082">Source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Single-cycle IO block<br />
Provides core-local and inter-core hardware for the two processors, with single-cycle access.</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><dl class="item-table"><dt><a class="mod" href="cpuid/index.html" title="mod rp2040_pac::sio::cpuid">cpuid</a></dt><dd>Processor core identifier<br />
Value is 0 when read from processor core 0, and 1 when read from processor core 1.</dd><dt><a class="mod" href="div_csr/index.html" title="mod rp2040_pac::sio::div_csr">div_csr</a></dt><dd>Control and status register for divider.</dd><dt><a class="mod" href="div_quotient/index.html" title="mod rp2040_pac::sio::div_quotient">div_<wbr>quotient</a></dt><dd>Divider result quotient<br />
The result of <code>DIVIDEND / DIVISOR</code> (division). Contents undefined while CSR_READY is low.<br />
For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.<br />
This register can be written to directly, for context save/restore purposes. This halts any<br />
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.<br />
Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order<br />
REMAINDER, QUOTIENT if CSR_DIRTY is used.</dd><dt><a class="mod" href="div_remainder/index.html" title="mod rp2040_pac::sio::div_remainder">div_<wbr>remainder</a></dt><dd>Divider result remainder<br />
The result of <code>DIVIDEND % DIVISOR</code> (modulo). Contents undefined while CSR_READY is low.<br />
For signed calculations, REMAINDER is negative only when DIVIDEND is negative.<br />
This register can be written to directly, for context save/restore purposes. This halts any<br />
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.</dd><dt><a class="mod" href="div_sdividend/index.html" title="mod rp2040_pac::sio::div_sdividend">div_<wbr>sdividend</a></dt><dd>Divider signed dividend<br />
The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.</dd><dt><a class="mod" href="div_sdivisor/index.html" title="mod rp2040_pac::sio::div_sdivisor">div_<wbr>sdivisor</a></dt><dd>Divider signed divisor<br />
The same as UDIVISOR, but starts a signed calculation, rather than unsigned.</dd><dt><a class="mod" href="div_udividend/index.html" title="mod rp2040_pac::sio::div_udividend">div_<wbr>udividend</a></dt><dd>Divider unsigned dividend<br />
Write to the DIVIDEND operand of the divider, i.e. the p in <code>p / q</code>.<br />
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.<br />
UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an<br />
unsigned calculation, and the S alias starts a signed calculation.</dd><dt><a class="mod" href="div_udivisor/index.html" title="mod rp2040_pac::sio::div_udivisor">div_<wbr>udivisor</a></dt><dd>Divider unsigned divisor<br />
Write to the DIVISOR operand of the divider, i.e. the q in <code>p / q</code>.<br />
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.<br />
UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an<br />
unsigned calculation, and the S alias starts a signed calculation.</dd><dt><a class="mod" href="fifo_rd/index.html" title="mod rp2040_pac::sio::fifo_rd">fifo_rd</a></dt><dd>Read access to this core’s RX FIFO</dd><dt><a class="mod" href="fifo_st/index.html" title="mod rp2040_pac::sio::fifo_st">fifo_st</a></dt><dd>Status register for inter-core FIFOs (mailboxes).<br />
There is one FIFO in the core 0 -&gt; core 1 direction, and one core 1 -&gt; core 0. Both are 32 bits wide and 8 words deep.<br />
Core 0 can see the read side of the 1-&gt;0 FIFO (RX), and the write side of 0-&gt;1 FIFO (TX).<br />
Core 1 can see the read side of the 0-&gt;1 FIFO (RX), and the write side of 1-&gt;0 FIFO (TX).<br />
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</dd><dt><a class="mod" href="fifo_wr/index.html" title="mod rp2040_pac::sio::fifo_wr">fifo_wr</a></dt><dd>Write access to this core’s TX FIFO</dd><dt><a class="mod" href="gpio_hi_in/index.html" title="mod rp2040_pac::sio::gpio_hi_in">gpio_<wbr>hi_<wbr>in</a></dt><dd>Input value for QSPI pins</dd><dt><a class="mod" href="gpio_hi_oe/index.html" title="mod rp2040_pac::sio::gpio_hi_oe">gpio_<wbr>hi_<wbr>oe</a></dt><dd>QSPI output enable</dd><dt><a class="mod" href="gpio_hi_oe_clr/index.html" title="mod rp2040_pac::sio::gpio_hi_oe_clr">gpio_<wbr>hi_<wbr>oe_<wbr>clr</a></dt><dd>QSPI output enable clear</dd><dt><a class="mod" href="gpio_hi_oe_set/index.html" title="mod rp2040_pac::sio::gpio_hi_oe_set">gpio_<wbr>hi_<wbr>oe_<wbr>set</a></dt><dd>QSPI output enable set</dd><dt><a class="mod" href="gpio_hi_oe_xor/index.html" title="mod rp2040_pac::sio::gpio_hi_oe_xor">gpio_<wbr>hi_<wbr>oe_<wbr>xor</a></dt><dd>QSPI output enable XOR</dd><dt><a class="mod" href="gpio_hi_out/index.html" title="mod rp2040_pac::sio::gpio_hi_out">gpio_<wbr>hi_<wbr>out</a></dt><dd>QSPI output value</dd><dt><a class="mod" href="gpio_hi_out_clr/index.html" title="mod rp2040_pac::sio::gpio_hi_out_clr">gpio_<wbr>hi_<wbr>out_<wbr>clr</a></dt><dd>QSPI output value clear</dd><dt><a class="mod" href="gpio_hi_out_set/index.html" title="mod rp2040_pac::sio::gpio_hi_out_set">gpio_<wbr>hi_<wbr>out_<wbr>set</a></dt><dd>QSPI output value set</dd><dt><a class="mod" href="gpio_hi_out_xor/index.html" title="mod rp2040_pac::sio::gpio_hi_out_xor">gpio_<wbr>hi_<wbr>out_<wbr>xor</a></dt><dd>QSPI output value XOR</dd><dt><a class="mod" href="gpio_in/index.html" title="mod rp2040_pac::sio::gpio_in">gpio_in</a></dt><dd>Input value for GPIO pins</dd><dt><a class="mod" href="gpio_oe/index.html" title="mod rp2040_pac::sio::gpio_oe">gpio_oe</a></dt><dd>GPIO output enable</dd><dt><a class="mod" href="gpio_oe_clr/index.html" title="mod rp2040_pac::sio::gpio_oe_clr">gpio_<wbr>oe_<wbr>clr</a></dt><dd>GPIO output enable clear</dd><dt><a class="mod" href="gpio_oe_set/index.html" title="mod rp2040_pac::sio::gpio_oe_set">gpio_<wbr>oe_<wbr>set</a></dt><dd>GPIO output enable set</dd><dt><a class="mod" href="gpio_oe_xor/index.html" title="mod rp2040_pac::sio::gpio_oe_xor">gpio_<wbr>oe_<wbr>xor</a></dt><dd>GPIO output enable XOR</dd><dt><a class="mod" href="gpio_out/index.html" title="mod rp2040_pac::sio::gpio_out">gpio_<wbr>out</a></dt><dd>GPIO output value</dd><dt><a class="mod" href="gpio_out_clr/index.html" title="mod rp2040_pac::sio::gpio_out_clr">gpio_<wbr>out_<wbr>clr</a></dt><dd>GPIO output value clear</dd><dt><a class="mod" href="gpio_out_set/index.html" title="mod rp2040_pac::sio::gpio_out_set">gpio_<wbr>out_<wbr>set</a></dt><dd>GPIO output value set</dd><dt><a class="mod" href="gpio_out_xor/index.html" title="mod rp2040_pac::sio::gpio_out_xor">gpio_<wbr>out_<wbr>xor</a></dt><dd>GPIO output value XOR</dd><dt><a class="mod" href="interp0_accum0/index.html" title="mod rp2040_pac::sio::interp0_accum0">interp0_<wbr>accum0</a></dt><dd>Read/write access to accumulator 0</dd><dt><a class="mod" href="interp0_accum0_add/index.html" title="mod rp2040_pac::sio::interp0_accum0_add">interp0_<wbr>accum0_<wbr>add</a></dt><dd>Values written here are atomically added to ACCUM0<br />
Reading yields lane 0’s raw shift and mask value (BASE0 not added).</dd><dt><a class="mod" href="interp0_accum1/index.html" title="mod rp2040_pac::sio::interp0_accum1">interp0_<wbr>accum1</a></dt><dd>Read/write access to accumulator 1</dd><dt><a class="mod" href="interp0_accum1_add/index.html" title="mod rp2040_pac::sio::interp0_accum1_add">interp0_<wbr>accum1_<wbr>add</a></dt><dd>Values written here are atomically added to ACCUM1<br />
Reading yields lane 1’s raw shift and mask value (BASE1 not added).</dd><dt><a class="mod" href="interp0_base0/index.html" title="mod rp2040_pac::sio::interp0_base0">interp0_<wbr>base0</a></dt><dd>Read/write access to BASE0 register.</dd><dt><a class="mod" href="interp0_base1/index.html" title="mod rp2040_pac::sio::interp0_base1">interp0_<wbr>base1</a></dt><dd>Read/write access to BASE1 register.</dd><dt><a class="mod" href="interp0_base2/index.html" title="mod rp2040_pac::sio::interp0_base2">interp0_<wbr>base2</a></dt><dd>Read/write access to BASE2 register.</dd><dt><a class="mod" href="interp0_base_1and0/index.html" title="mod rp2040_pac::sio::interp0_base_1and0">interp0_<wbr>base_<wbr>1and0</a></dt><dd>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.<br />
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.</dd><dt><a class="mod" href="interp0_ctrl_lane0/index.html" title="mod rp2040_pac::sio::interp0_ctrl_lane0">interp0_<wbr>ctrl_<wbr>lane0</a></dt><dd>Control register for lane 0</dd><dt><a class="mod" href="interp0_ctrl_lane1/index.html" title="mod rp2040_pac::sio::interp0_ctrl_lane1">interp0_<wbr>ctrl_<wbr>lane1</a></dt><dd>Control register for lane 1</dd><dt><a class="mod" href="interp0_peek_full/index.html" title="mod rp2040_pac::sio::interp0_peek_full">interp0_<wbr>peek_<wbr>full</a></dt><dd>Read FULL result, without altering any internal state (PEEK).</dd><dt><a class="mod" href="interp0_peek_lane0/index.html" title="mod rp2040_pac::sio::interp0_peek_lane0">interp0_<wbr>peek_<wbr>lane0</a></dt><dd>Read LANE0 result, without altering any internal state (PEEK).</dd><dt><a class="mod" href="interp0_peek_lane1/index.html" title="mod rp2040_pac::sio::interp0_peek_lane1">interp0_<wbr>peek_<wbr>lane1</a></dt><dd>Read LANE1 result, without altering any internal state (PEEK).</dd><dt><a class="mod" href="interp0_pop_full/index.html" title="mod rp2040_pac::sio::interp0_pop_full">interp0_<wbr>pop_<wbr>full</a></dt><dd>Read FULL result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="mod" href="interp0_pop_lane0/index.html" title="mod rp2040_pac::sio::interp0_pop_lane0">interp0_<wbr>pop_<wbr>lane0</a></dt><dd>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="mod" href="interp0_pop_lane1/index.html" title="mod rp2040_pac::sio::interp0_pop_lane1">interp0_<wbr>pop_<wbr>lane1</a></dt><dd>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="mod" href="interp1_accum0/index.html" title="mod rp2040_pac::sio::interp1_accum0">interp1_<wbr>accum0</a></dt><dd>Read/write access to accumulator 0</dd><dt><a class="mod" href="interp1_accum0_add/index.html" title="mod rp2040_pac::sio::interp1_accum0_add">interp1_<wbr>accum0_<wbr>add</a></dt><dd>Values written here are atomically added to ACCUM0<br />
Reading yields lane 0’s raw shift and mask value (BASE0 not added).</dd><dt><a class="mod" href="interp1_accum1/index.html" title="mod rp2040_pac::sio::interp1_accum1">interp1_<wbr>accum1</a></dt><dd>Read/write access to accumulator 1</dd><dt><a class="mod" href="interp1_accum1_add/index.html" title="mod rp2040_pac::sio::interp1_accum1_add">interp1_<wbr>accum1_<wbr>add</a></dt><dd>Values written here are atomically added to ACCUM1<br />
Reading yields lane 1’s raw shift and mask value (BASE1 not added).</dd><dt><a class="mod" href="interp1_base0/index.html" title="mod rp2040_pac::sio::interp1_base0">interp1_<wbr>base0</a></dt><dd>Read/write access to BASE0 register.</dd><dt><a class="mod" href="interp1_base1/index.html" title="mod rp2040_pac::sio::interp1_base1">interp1_<wbr>base1</a></dt><dd>Read/write access to BASE1 register.</dd><dt><a class="mod" href="interp1_base2/index.html" title="mod rp2040_pac::sio::interp1_base2">interp1_<wbr>base2</a></dt><dd>Read/write access to BASE2 register.</dd><dt><a class="mod" href="interp1_base_1and0/index.html" title="mod rp2040_pac::sio::interp1_base_1and0">interp1_<wbr>base_<wbr>1and0</a></dt><dd>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.<br />
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.</dd><dt><a class="mod" href="interp1_ctrl_lane0/index.html" title="mod rp2040_pac::sio::interp1_ctrl_lane0">interp1_<wbr>ctrl_<wbr>lane0</a></dt><dd>Control register for lane 0</dd><dt><a class="mod" href="interp1_ctrl_lane1/index.html" title="mod rp2040_pac::sio::interp1_ctrl_lane1">interp1_<wbr>ctrl_<wbr>lane1</a></dt><dd>Control register for lane 1</dd><dt><a class="mod" href="interp1_peek_full/index.html" title="mod rp2040_pac::sio::interp1_peek_full">interp1_<wbr>peek_<wbr>full</a></dt><dd>Read FULL result, without altering any internal state (PEEK).</dd><dt><a class="mod" href="interp1_peek_lane0/index.html" title="mod rp2040_pac::sio::interp1_peek_lane0">interp1_<wbr>peek_<wbr>lane0</a></dt><dd>Read LANE0 result, without altering any internal state (PEEK).</dd><dt><a class="mod" href="interp1_peek_lane1/index.html" title="mod rp2040_pac::sio::interp1_peek_lane1">interp1_<wbr>peek_<wbr>lane1</a></dt><dd>Read LANE1 result, without altering any internal state (PEEK).</dd><dt><a class="mod" href="interp1_pop_full/index.html" title="mod rp2040_pac::sio::interp1_pop_full">interp1_<wbr>pop_<wbr>full</a></dt><dd>Read FULL result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="mod" href="interp1_pop_lane0/index.html" title="mod rp2040_pac::sio::interp1_pop_lane0">interp1_<wbr>pop_<wbr>lane0</a></dt><dd>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="mod" href="interp1_pop_lane1/index.html" title="mod rp2040_pac::sio::interp1_pop_lane1">interp1_<wbr>pop_<wbr>lane1</a></dt><dd>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="mod" href="spinlock/index.html" title="mod rp2040_pac::sio::spinlock">spinlock</a></dt><dd>Reading from a spinlock address will:</dd><dt><a class="mod" href="spinlock_st/index.html" title="mod rp2040_pac::sio::spinlock_st">spinlock_<wbr>st</a></dt><dd>Spinlock state<br />
A bitmap containing the state of all 32 spinlocks (1=locked).<br />
Mainly intended for debugging.</dd></dl><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><dl class="item-table"><dt><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::sio::RegisterBlock">Register<wbr>Block</a></dt><dd>Register block</dd></dl><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><dl class="item-table"><dt><a class="type" href="type.CPUID.html" title="type rp2040_pac::sio::CPUID">CPUID</a></dt><dd>CPUID (r) register accessor: Processor core identifier<br />
Value is 0 when read from processor core 0, and 1 when read from processor core 1.</dd><dt><a class="type" href="type.DIV_CSR.html" title="type rp2040_pac::sio::DIV_CSR">DIV_CSR</a></dt><dd>DIV_CSR (r) register accessor: Control and status register for divider.</dd><dt><a class="type" href="type.DIV_QUOTIENT.html" title="type rp2040_pac::sio::DIV_QUOTIENT">DIV_<wbr>QUOTIENT</a></dt><dd>DIV_QUOTIENT (rw) register accessor: Divider result quotient<br />
The result of <code>DIVIDEND / DIVISOR</code> (division). Contents undefined while CSR_READY is low.<br />
For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.<br />
This register can be written to directly, for context save/restore purposes. This halts any<br />
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.<br />
Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order<br />
REMAINDER, QUOTIENT if CSR_DIRTY is used.</dd><dt><a class="type" href="type.DIV_REMAINDER.html" title="type rp2040_pac::sio::DIV_REMAINDER">DIV_<wbr>REMAINDER</a></dt><dd>DIV_REMAINDER (rw) register accessor: Divider result remainder<br />
The result of <code>DIVIDEND % DIVISOR</code> (modulo). Contents undefined while CSR_READY is low.<br />
For signed calculations, REMAINDER is negative only when DIVIDEND is negative.<br />
This register can be written to directly, for context save/restore purposes. This halts any<br />
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.</dd><dt><a class="type" href="type.DIV_SDIVIDEND.html" title="type rp2040_pac::sio::DIV_SDIVIDEND">DIV_<wbr>SDIVIDEND</a></dt><dd>DIV_SDIVIDEND (rw) register accessor: Divider signed dividend<br />
The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.</dd><dt><a class="type" href="type.DIV_SDIVISOR.html" title="type rp2040_pac::sio::DIV_SDIVISOR">DIV_<wbr>SDIVISOR</a></dt><dd>DIV_SDIVISOR (rw) register accessor: Divider signed divisor<br />
The same as UDIVISOR, but starts a signed calculation, rather than unsigned.</dd><dt><a class="type" href="type.DIV_UDIVIDEND.html" title="type rp2040_pac::sio::DIV_UDIVIDEND">DIV_<wbr>UDIVIDEND</a></dt><dd>DIV_UDIVIDEND (rw) register accessor: Divider unsigned dividend<br />
Write to the DIVIDEND operand of the divider, i.e. the p in <code>p / q</code>.<br />
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.<br />
UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an<br />
unsigned calculation, and the S alias starts a signed calculation.</dd><dt><a class="type" href="type.DIV_UDIVISOR.html" title="type rp2040_pac::sio::DIV_UDIVISOR">DIV_<wbr>UDIVISOR</a></dt><dd>DIV_UDIVISOR (rw) register accessor: Divider unsigned divisor<br />
Write to the DIVISOR operand of the divider, i.e. the q in <code>p / q</code>.<br />
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.<br />
UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an<br />
unsigned calculation, and the S alias starts a signed calculation.</dd><dt><a class="type" href="type.FIFO_RD.html" title="type rp2040_pac::sio::FIFO_RD">FIFO_RD</a></dt><dd>FIFO_RD (r) register accessor: Read access to this core’s RX FIFO</dd><dt><a class="type" href="type.FIFO_ST.html" title="type rp2040_pac::sio::FIFO_ST">FIFO_ST</a></dt><dd>FIFO_ST (rw) register accessor: Status register for inter-core FIFOs (mailboxes).<br />
There is one FIFO in the core 0 -&gt; core 1 direction, and one core 1 -&gt; core 0. Both are 32 bits wide and 8 words deep.<br />
Core 0 can see the read side of the 1-&gt;0 FIFO (RX), and the write side of 0-&gt;1 FIFO (TX).<br />
Core 1 can see the read side of the 0-&gt;1 FIFO (RX), and the write side of 1-&gt;0 FIFO (TX).<br />
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</dd><dt><a class="type" href="type.FIFO_WR.html" title="type rp2040_pac::sio::FIFO_WR">FIFO_WR</a></dt><dd>FIFO_WR (w) register accessor: Write access to this core’s TX FIFO</dd><dt><a class="type" href="type.GPIO_HI_IN.html" title="type rp2040_pac::sio::GPIO_HI_IN">GPIO_<wbr>HI_<wbr>IN</a></dt><dd>GPIO_HI_IN (r) register accessor: Input value for QSPI pins</dd><dt><a class="type" href="type.GPIO_HI_OE.html" title="type rp2040_pac::sio::GPIO_HI_OE">GPIO_<wbr>HI_<wbr>OE</a></dt><dd>GPIO_HI_OE (rw) register accessor: QSPI output enable</dd><dt><a class="type" href="type.GPIO_HI_OE_CLR.html" title="type rp2040_pac::sio::GPIO_HI_OE_CLR">GPIO_<wbr>HI_<wbr>OE_<wbr>CLR</a></dt><dd>GPIO_HI_OE_CLR (w) register accessor: QSPI output enable clear</dd><dt><a class="type" href="type.GPIO_HI_OE_SET.html" title="type rp2040_pac::sio::GPIO_HI_OE_SET">GPIO_<wbr>HI_<wbr>OE_<wbr>SET</a></dt><dd>GPIO_HI_OE_SET (w) register accessor: QSPI output enable set</dd><dt><a class="type" href="type.GPIO_HI_OE_XOR.html" title="type rp2040_pac::sio::GPIO_HI_OE_XOR">GPIO_<wbr>HI_<wbr>OE_<wbr>XOR</a></dt><dd>GPIO_HI_OE_XOR (w) register accessor: QSPI output enable XOR</dd><dt><a class="type" href="type.GPIO_HI_OUT.html" title="type rp2040_pac::sio::GPIO_HI_OUT">GPIO_<wbr>HI_<wbr>OUT</a></dt><dd>GPIO_HI_OUT (rw) register accessor: QSPI output value</dd><dt><a class="type" href="type.GPIO_HI_OUT_CLR.html" title="type rp2040_pac::sio::GPIO_HI_OUT_CLR">GPIO_<wbr>HI_<wbr>OUT_<wbr>CLR</a></dt><dd>GPIO_HI_OUT_CLR (w) register accessor: QSPI output value clear</dd><dt><a class="type" href="type.GPIO_HI_OUT_SET.html" title="type rp2040_pac::sio::GPIO_HI_OUT_SET">GPIO_<wbr>HI_<wbr>OUT_<wbr>SET</a></dt><dd>GPIO_HI_OUT_SET (w) register accessor: QSPI output value set</dd><dt><a class="type" href="type.GPIO_HI_OUT_XOR.html" title="type rp2040_pac::sio::GPIO_HI_OUT_XOR">GPIO_<wbr>HI_<wbr>OUT_<wbr>XOR</a></dt><dd>GPIO_HI_OUT_XOR (w) register accessor: QSPI output value XOR</dd><dt><a class="type" href="type.GPIO_IN.html" title="type rp2040_pac::sio::GPIO_IN">GPIO_IN</a></dt><dd>GPIO_IN (r) register accessor: Input value for GPIO pins</dd><dt><a class="type" href="type.GPIO_OE.html" title="type rp2040_pac::sio::GPIO_OE">GPIO_OE</a></dt><dd>GPIO_OE (rw) register accessor: GPIO output enable</dd><dt><a class="type" href="type.GPIO_OE_CLR.html" title="type rp2040_pac::sio::GPIO_OE_CLR">GPIO_<wbr>OE_<wbr>CLR</a></dt><dd>GPIO_OE_CLR (w) register accessor: GPIO output enable clear</dd><dt><a class="type" href="type.GPIO_OE_SET.html" title="type rp2040_pac::sio::GPIO_OE_SET">GPIO_<wbr>OE_<wbr>SET</a></dt><dd>GPIO_OE_SET (w) register accessor: GPIO output enable set</dd><dt><a class="type" href="type.GPIO_OE_XOR.html" title="type rp2040_pac::sio::GPIO_OE_XOR">GPIO_<wbr>OE_<wbr>XOR</a></dt><dd>GPIO_OE_XOR (w) register accessor: GPIO output enable XOR</dd><dt><a class="type" href="type.GPIO_OUT.html" title="type rp2040_pac::sio::GPIO_OUT">GPIO_<wbr>OUT</a></dt><dd>GPIO_OUT (rw) register accessor: GPIO output value</dd><dt><a class="type" href="type.GPIO_OUT_CLR.html" title="type rp2040_pac::sio::GPIO_OUT_CLR">GPIO_<wbr>OUT_<wbr>CLR</a></dt><dd>GPIO_OUT_CLR (w) register accessor: GPIO output value clear</dd><dt><a class="type" href="type.GPIO_OUT_SET.html" title="type rp2040_pac::sio::GPIO_OUT_SET">GPIO_<wbr>OUT_<wbr>SET</a></dt><dd>GPIO_OUT_SET (w) register accessor: GPIO output value set</dd><dt><a class="type" href="type.GPIO_OUT_XOR.html" title="type rp2040_pac::sio::GPIO_OUT_XOR">GPIO_<wbr>OUT_<wbr>XOR</a></dt><dd>GPIO_OUT_XOR (w) register accessor: GPIO output value XOR</dd><dt><a class="type" href="type.INTERP0_ACCUM0.html" title="type rp2040_pac::sio::INTERP0_ACCUM0">INTER<wbr>P0_<wbr>ACCU<wbr>M0</a></dt><dd>INTERP0_ACCUM0 (rw) register accessor: Read/write access to accumulator 0</dd><dt><a class="type" href="type.INTERP0_ACCUM0_ADD.html" title="type rp2040_pac::sio::INTERP0_ACCUM0_ADD">INTER<wbr>P0_<wbr>ACCU<wbr>M0_<wbr>ADD</a></dt><dd>INTERP0_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0<br />
Reading yields lane 0’s raw shift and mask value (BASE0 not added).</dd><dt><a class="type" href="type.INTERP0_ACCUM1.html" title="type rp2040_pac::sio::INTERP0_ACCUM1">INTER<wbr>P0_<wbr>ACCU<wbr>M1</a></dt><dd>INTERP0_ACCUM1 (rw) register accessor: Read/write access to accumulator 1</dd><dt><a class="type" href="type.INTERP0_ACCUM1_ADD.html" title="type rp2040_pac::sio::INTERP0_ACCUM1_ADD">INTER<wbr>P0_<wbr>ACCU<wbr>M1_<wbr>ADD</a></dt><dd>INTERP0_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1<br />
Reading yields lane 1’s raw shift and mask value (BASE1 not added).</dd><dt><a class="type" href="type.INTERP0_BASE0.html" title="type rp2040_pac::sio::INTERP0_BASE0">INTER<wbr>P0_<wbr>BASE0</a></dt><dd>INTERP0_BASE0 (rw) register accessor: Read/write access to BASE0 register.</dd><dt><a class="type" href="type.INTERP0_BASE1.html" title="type rp2040_pac::sio::INTERP0_BASE1">INTER<wbr>P0_<wbr>BASE1</a></dt><dd>INTERP0_BASE1 (rw) register accessor: Read/write access to BASE1 register.</dd><dt><a class="type" href="type.INTERP0_BASE2.html" title="type rp2040_pac::sio::INTERP0_BASE2">INTER<wbr>P0_<wbr>BASE2</a></dt><dd>INTERP0_BASE2 (rw) register accessor: Read/write access to BASE2 register.</dd><dt><a class="type" href="type.INTERP0_BASE_1AND0.html" title="type rp2040_pac::sio::INTERP0_BASE_1AND0">INTER<wbr>P0_<wbr>BASE_<wbr>1AND0</a></dt><dd>INTERP0_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.<br />
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.</dd><dt><a class="type" href="type.INTERP0_CTRL_LANE0.html" title="type rp2040_pac::sio::INTERP0_CTRL_LANE0">INTER<wbr>P0_<wbr>CTRL_<wbr>LANE0</a></dt><dd>INTERP0_CTRL_LANE0 (rw) register accessor: Control register for lane 0</dd><dt><a class="type" href="type.INTERP0_CTRL_LANE1.html" title="type rp2040_pac::sio::INTERP0_CTRL_LANE1">INTER<wbr>P0_<wbr>CTRL_<wbr>LANE1</a></dt><dd>INTERP0_CTRL_LANE1 (rw) register accessor: Control register for lane 1</dd><dt><a class="type" href="type.INTERP0_PEEK_FULL.html" title="type rp2040_pac::sio::INTERP0_PEEK_FULL">INTER<wbr>P0_<wbr>PEEK_<wbr>FULL</a></dt><dd>INTERP0_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK).</dd><dt><a class="type" href="type.INTERP0_PEEK_LANE0.html" title="type rp2040_pac::sio::INTERP0_PEEK_LANE0">INTER<wbr>P0_<wbr>PEEK_<wbr>LANE0</a></dt><dd>INTERP0_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK).</dd><dt><a class="type" href="type.INTERP0_PEEK_LANE1.html" title="type rp2040_pac::sio::INTERP0_PEEK_LANE1">INTER<wbr>P0_<wbr>PEEK_<wbr>LANE1</a></dt><dd>INTERP0_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK).</dd><dt><a class="type" href="type.INTERP0_POP_FULL.html" title="type rp2040_pac::sio::INTERP0_POP_FULL">INTER<wbr>P0_<wbr>POP_<wbr>FULL</a></dt><dd>INTERP0_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="type" href="type.INTERP0_POP_LANE0.html" title="type rp2040_pac::sio::INTERP0_POP_LANE0">INTER<wbr>P0_<wbr>POP_<wbr>LANE0</a></dt><dd>INTERP0_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="type" href="type.INTERP0_POP_LANE1.html" title="type rp2040_pac::sio::INTERP0_POP_LANE1">INTER<wbr>P0_<wbr>POP_<wbr>LANE1</a></dt><dd>INTERP0_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="type" href="type.INTERP1_ACCUM0.html" title="type rp2040_pac::sio::INTERP1_ACCUM0">INTER<wbr>P1_<wbr>ACCU<wbr>M0</a></dt><dd>INTERP1_ACCUM0 (rw) register accessor: Read/write access to accumulator 0</dd><dt><a class="type" href="type.INTERP1_ACCUM0_ADD.html" title="type rp2040_pac::sio::INTERP1_ACCUM0_ADD">INTER<wbr>P1_<wbr>ACCU<wbr>M0_<wbr>ADD</a></dt><dd>INTERP1_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0<br />
Reading yields lane 0’s raw shift and mask value (BASE0 not added).</dd><dt><a class="type" href="type.INTERP1_ACCUM1.html" title="type rp2040_pac::sio::INTERP1_ACCUM1">INTER<wbr>P1_<wbr>ACCU<wbr>M1</a></dt><dd>INTERP1_ACCUM1 (rw) register accessor: Read/write access to accumulator 1</dd><dt><a class="type" href="type.INTERP1_ACCUM1_ADD.html" title="type rp2040_pac::sio::INTERP1_ACCUM1_ADD">INTER<wbr>P1_<wbr>ACCU<wbr>M1_<wbr>ADD</a></dt><dd>INTERP1_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1<br />
Reading yields lane 1’s raw shift and mask value (BASE1 not added).</dd><dt><a class="type" href="type.INTERP1_BASE0.html" title="type rp2040_pac::sio::INTERP1_BASE0">INTER<wbr>P1_<wbr>BASE0</a></dt><dd>INTERP1_BASE0 (rw) register accessor: Read/write access to BASE0 register.</dd><dt><a class="type" href="type.INTERP1_BASE1.html" title="type rp2040_pac::sio::INTERP1_BASE1">INTER<wbr>P1_<wbr>BASE1</a></dt><dd>INTERP1_BASE1 (rw) register accessor: Read/write access to BASE1 register.</dd><dt><a class="type" href="type.INTERP1_BASE2.html" title="type rp2040_pac::sio::INTERP1_BASE2">INTER<wbr>P1_<wbr>BASE2</a></dt><dd>INTERP1_BASE2 (rw) register accessor: Read/write access to BASE2 register.</dd><dt><a class="type" href="type.INTERP1_BASE_1AND0.html" title="type rp2040_pac::sio::INTERP1_BASE_1AND0">INTER<wbr>P1_<wbr>BASE_<wbr>1AND0</a></dt><dd>INTERP1_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.<br />
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.</dd><dt><a class="type" href="type.INTERP1_CTRL_LANE0.html" title="type rp2040_pac::sio::INTERP1_CTRL_LANE0">INTER<wbr>P1_<wbr>CTRL_<wbr>LANE0</a></dt><dd>INTERP1_CTRL_LANE0 (rw) register accessor: Control register for lane 0</dd><dt><a class="type" href="type.INTERP1_CTRL_LANE1.html" title="type rp2040_pac::sio::INTERP1_CTRL_LANE1">INTER<wbr>P1_<wbr>CTRL_<wbr>LANE1</a></dt><dd>INTERP1_CTRL_LANE1 (rw) register accessor: Control register for lane 1</dd><dt><a class="type" href="type.INTERP1_PEEK_FULL.html" title="type rp2040_pac::sio::INTERP1_PEEK_FULL">INTER<wbr>P1_<wbr>PEEK_<wbr>FULL</a></dt><dd>INTERP1_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK).</dd><dt><a class="type" href="type.INTERP1_PEEK_LANE0.html" title="type rp2040_pac::sio::INTERP1_PEEK_LANE0">INTER<wbr>P1_<wbr>PEEK_<wbr>LANE0</a></dt><dd>INTERP1_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK).</dd><dt><a class="type" href="type.INTERP1_PEEK_LANE1.html" title="type rp2040_pac::sio::INTERP1_PEEK_LANE1">INTER<wbr>P1_<wbr>PEEK_<wbr>LANE1</a></dt><dd>INTERP1_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK).</dd><dt><a class="type" href="type.INTERP1_POP_FULL.html" title="type rp2040_pac::sio::INTERP1_POP_FULL">INTER<wbr>P1_<wbr>POP_<wbr>FULL</a></dt><dd>INTERP1_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="type" href="type.INTERP1_POP_LANE0.html" title="type rp2040_pac::sio::INTERP1_POP_LANE0">INTER<wbr>P1_<wbr>POP_<wbr>LANE0</a></dt><dd>INTERP1_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="type" href="type.INTERP1_POP_LANE1.html" title="type rp2040_pac::sio::INTERP1_POP_LANE1">INTER<wbr>P1_<wbr>POP_<wbr>LANE1</a></dt><dd>INTERP1_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</dd><dt><a class="type" href="type.SPINLOCK.html" title="type rp2040_pac::sio::SPINLOCK">SPINLOCK</a></dt><dd>SPINLOCK (rw) register accessor: Reading from a spinlock address will:</dd><dt><a class="type" href="type.SPINLOCK_ST.html" title="type rp2040_pac::sio::SPINLOCK_ST">SPINLOCK_<wbr>ST</a></dt><dd>SPINLOCK_ST (r) register accessor: Spinlock state<br />
A bitmap containing the state of all 32 spinlocks (1=locked).<br />
Mainly intended for debugging.</dd></dl></section></div></main></body></html>
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