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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"><title>rp2040_pac::pll_sys::cs - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module cs</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module cs</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>pll_<wbr>sys</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">pll_sys</a></div><h1>Module <span>cs</span> <button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/rp2040_pac/pll_sys/cs.rs.html#1-85">Source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Control and Status<br />
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GENERAL CONSTRAINTS:<br />
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Reference clock frequency min=5MHz, max=800MHz<br />
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Feedback divider min=16, max=320<br />
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VCO frequency min=750MHz, max=1600MHz</p>
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</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><dl class="item-table"><dt><a class="struct" href="struct.CS_SPEC.html" title="struct rp2040_pac::pll_sys::cs::CS_SPEC">CS_SPEC</a></dt><dd>Control and Status<br />
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GENERAL CONSTRAINTS:<br />
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Reference clock frequency min=5MHz, max=800MHz<br />
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Feedback divider min=16, max=320<br />
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VCO frequency min=750MHz, max=1600MHz</dd></dl><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><dl class="item-table"><dt><a class="type" href="type.BYPASS_R.html" title="type rp2040_pac::pll_sys::cs::BYPASS_R">BYPASS_<wbr>R</a></dt><dd>Field <code>BYPASS</code> reader - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</dd><dt><a class="type" href="type.BYPASS_W.html" title="type rp2040_pac::pll_sys::cs::BYPASS_W">BYPASS_<wbr>W</a></dt><dd>Field <code>BYPASS</code> writer - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</dd><dt><a class="type" href="type.LOCK_R.html" title="type rp2040_pac::pll_sys::cs::LOCK_R">LOCK_R</a></dt><dd>Field <code>LOCK</code> reader - PLL is locked</dd><dt><a class="type" href="type.R.html" title="type rp2040_pac::pll_sys::cs::R">R</a></dt><dd>Register <code>CS</code> reader</dd><dt><a class="type" href="type.REFDIV_R.html" title="type rp2040_pac::pll_sys::cs::REFDIV_R">REFDIV_<wbr>R</a></dt><dd>Field <code>REFDIV</code> reader - Divides the PLL input reference clock.<br />
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Behaviour is undefined for div=0.<br />
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PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</dd><dt><a class="type" href="type.REFDIV_W.html" title="type rp2040_pac::pll_sys::cs::REFDIV_W">REFDIV_<wbr>W</a></dt><dd>Field <code>REFDIV</code> writer - Divides the PLL input reference clock.<br />
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Behaviour is undefined for div=0.<br />
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PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</dd><dt><a class="type" href="type.W.html" title="type rp2040_pac::pll_sys::cs::W">W</a></dt><dd>Register <code>CS</code> writer</dd></dl></section></div></main></body></html> |