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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Programmable IO block"><title>rp2040_pac::pio0 - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module pio0</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module pio0</a></h2><h3><a href="#reexports">Module Items</a></h3><ul class="block"><li><a href="#reexports" title="Re-exports">Re-exports</a></li><li><a href="#modules" title="Modules">Modules</a></li><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2 class="in-crate"><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../index.html">rp2040_pac</a></div><h1>Module <span>pio0</span> <button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../src/rp2040_pac/pio0.rs.html#1-286">Source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Programmable IO block</p>
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</div></details><h2 id="reexports" class="section-header">Re-exports<a href="#reexports" class="anchor">§</a></h2><dl class="item-table reexports"><dt id="reexport.SM"><code>pub use self::sm::<a class="struct" href="sm/struct.SM.html" title="struct rp2040_pac::pio0::sm::SM">SM</a>;</code></dt><dt id="reexport.SM_IRQ"><code>pub use self::sm_irq::<a class="struct" href="sm_irq/struct.SM_IRQ.html" title="struct rp2040_pac::pio0::sm_irq::SM_IRQ">SM_IRQ</a>;</code></dt></dl><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><dl class="item-table"><dt><a class="mod" href="ctrl/index.html" title="mod rp2040_pac::pio0::ctrl">ctrl</a></dt><dd>PIO control register</dd><dt><a class="mod" href="dbg_cfginfo/index.html" title="mod rp2040_pac::pio0::dbg_cfginfo">dbg_<wbr>cfginfo</a></dt><dd>The PIO hardware has some free parameters that may vary between chip products.<br />
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These should be provided in the chip datasheet, but are also exposed here.</dd><dt><a class="mod" href="dbg_padoe/index.html" title="mod rp2040_pac::pio0::dbg_padoe">dbg_<wbr>padoe</a></dt><dd>Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</dd><dt><a class="mod" href="dbg_padout/index.html" title="mod rp2040_pac::pio0::dbg_padout">dbg_<wbr>padout</a></dt><dd>Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</dd><dt><a class="mod" href="fdebug/index.html" title="mod rp2040_pac::pio0::fdebug">fdebug</a></dt><dd>FIFO debug register</dd><dt><a class="mod" href="flevel/index.html" title="mod rp2040_pac::pio0::flevel">flevel</a></dt><dd>FIFO levels</dd><dt><a class="mod" href="fstat/index.html" title="mod rp2040_pac::pio0::fstat">fstat</a></dt><dd>FIFO status register</dd><dt><a class="mod" href="input_sync_bypass/index.html" title="mod rp2040_pac::pio0::input_sync_bypass">input_<wbr>sync_<wbr>bypass</a></dt><dd>There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.<br />
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0 -> input is synchronized (default)<br />
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1 -> synchronizer is bypassed<br />
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If in doubt, leave this register as all zeroes.</dd><dt><a class="mod" href="instr_mem/index.html" title="mod rp2040_pac::pio0::instr_mem">instr_<wbr>mem</a></dt><dd>Write-only access to instruction memory location %s</dd><dt><a class="mod" href="intr/index.html" title="mod rp2040_pac::pio0::intr">intr</a></dt><dd>Raw Interrupts</dd><dt><a class="mod" href="irq/index.html" title="mod rp2040_pac::pio0::irq">irq</a></dt><dd>State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There’s no fixed association between flags and state machines – any state machine can use any flag.</dd><dt><a class="mod" href="irq_force/index.html" title="mod rp2040_pac::pio0::irq_force">irq_<wbr>force</a></dt><dd>Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.</dd><dt><a class="mod" href="rxf/index.html" title="mod rp2040_pac::pio0::rxf">rxf</a></dt><dd>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</dd><dt><a class="mod" href="sm/index.html" title="mod rp2040_pac::pio0::sm">sm</a></dt><dd>Cluster
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Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL</dd><dt><a class="mod" href="sm_irq/index.html" title="mod rp2040_pac::pio0::sm_irq">sm_irq</a></dt><dd>Cluster
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Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS</dd><dt><a class="mod" href="txf/index.html" title="mod rp2040_pac::pio0::txf">txf</a></dt><dd>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</dd></dl><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><dl class="item-table"><dt><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::pio0::RegisterBlock">Register<wbr>Block</a></dt><dd>Register block</dd></dl><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><dl class="item-table"><dt><a class="type" href="type.CTRL.html" title="type rp2040_pac::pio0::CTRL">CTRL</a></dt><dd>CTRL (rw) register accessor: PIO control register</dd><dt><a class="type" href="type.DBG_CFGINFO.html" title="type rp2040_pac::pio0::DBG_CFGINFO">DBG_<wbr>CFGINFO</a></dt><dd>DBG_CFGINFO (r) register accessor: The PIO hardware has some free parameters that may vary between chip products.<br />
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These should be provided in the chip datasheet, but are also exposed here.</dd><dt><a class="type" href="type.DBG_PADOE.html" title="type rp2040_pac::pio0::DBG_PADOE">DBG_<wbr>PADOE</a></dt><dd>DBG_PADOE (r) register accessor: Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</dd><dt><a class="type" href="type.DBG_PADOUT.html" title="type rp2040_pac::pio0::DBG_PADOUT">DBG_<wbr>PADOUT</a></dt><dd>DBG_PADOUT (r) register accessor: Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</dd><dt><a class="type" href="type.FDEBUG.html" title="type rp2040_pac::pio0::FDEBUG">FDEBUG</a></dt><dd>FDEBUG (rw) register accessor: FIFO debug register</dd><dt><a class="type" href="type.FLEVEL.html" title="type rp2040_pac::pio0::FLEVEL">FLEVEL</a></dt><dd>FLEVEL (r) register accessor: FIFO levels</dd><dt><a class="type" href="type.FSTAT.html" title="type rp2040_pac::pio0::FSTAT">FSTAT</a></dt><dd>FSTAT (r) register accessor: FIFO status register</dd><dt><a class="type" href="type.INPUT_SYNC_BYPASS.html" title="type rp2040_pac::pio0::INPUT_SYNC_BYPASS">INPUT_<wbr>SYNC_<wbr>BYPASS</a></dt><dd>INPUT_SYNC_BYPASS (rw) register accessor: There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.<br />
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0 -> input is synchronized (default)<br />
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1 -> synchronizer is bypassed<br />
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If in doubt, leave this register as all zeroes.</dd><dt><a class="type" href="type.INSTR_MEM.html" title="type rp2040_pac::pio0::INSTR_MEM">INSTR_<wbr>MEM</a></dt><dd>INSTR_MEM (w) register accessor: Write-only access to instruction memory location %s</dd><dt><a class="type" href="type.INTR.html" title="type rp2040_pac::pio0::INTR">INTR</a></dt><dd>INTR (r) register accessor: Raw Interrupts</dd><dt><a class="type" href="type.IRQ.html" title="type rp2040_pac::pio0::IRQ">IRQ</a></dt><dd>IRQ (rw) register accessor: State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There’s no fixed association between flags and state machines – any state machine can use any flag.</dd><dt><a class="type" href="type.IRQ_FORCE.html" title="type rp2040_pac::pio0::IRQ_FORCE">IRQ_<wbr>FORCE</a></dt><dd>IRQ_FORCE (w) register accessor: Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.</dd><dt><a class="type" href="type.RXF.html" title="type rp2040_pac::pio0::RXF">RXF</a></dt><dd>RXF (r) register accessor: Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</dd><dt><a class="type" href="type.TXF.html" title="type rp2040_pac::pio0::TXF">TXF</a></dt><dd>TXF (w) register accessor: Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</dd></dl></section></div></main></body></html> |