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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="I2C Status Register"><title>rp2040_pac::i2c0::ic_status - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module ic_status</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module ic_<wbr>status</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#enums" title="Enums">Enums</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>i2c0</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">i2c0</a></div><h1>Module <span>ic_<wbr>status</span> <button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/rp2040_pac/i2c0/ic_status.rs.html#1-328">Source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>I2C Status Register</p>
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<p>This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.</p>
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<p>When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0</p>
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</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><dl class="item-table"><dt><a class="struct" href="struct.IC_STATUS_SPEC.html" title="struct rp2040_pac::i2c0::ic_status::IC_STATUS_SPEC">IC_<wbr>STATUS_<wbr>SPEC</a></dt><dd>I2C Status Register</dd></dl><h2 id="enums" class="section-header">Enums<a href="#enums" class="anchor">§</a></h2><dl class="item-table"><dt><a class="enum" href="enum.ACTIVITY_A.html" title="enum rp2040_pac::i2c0::ic_status::ACTIVITY_A">ACTIVITY_<wbr>A</a></dt><dd>I2C Activity Status. Reset value: 0x0</dd><dt><a class="enum" href="enum.MST_ACTIVITY_A.html" title="enum rp2040_pac::i2c0::ic_status::MST_ACTIVITY_A">MST_<wbr>ACTIVITY_<wbr>A</a></dt><dd>Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.</dd><dt><a class="enum" href="enum.RFF_A.html" title="enum rp2040_pac::i2c0::ic_status::RFF_A">RFF_A</a></dt><dd>Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0</dd><dt><a class="enum" href="enum.RFNE_A.html" title="enum rp2040_pac::i2c0::ic_status::RFNE_A">RFNE_A</a></dt><dd>Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0</dd><dt><a class="enum" href="enum.SLV_ACTIVITY_A.html" title="enum rp2040_pac::i2c0::ic_status::SLV_ACTIVITY_A">SLV_<wbr>ACTIVITY_<wbr>A</a></dt><dd>Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0</dd><dt><a class="enum" href="enum.TFE_A.html" title="enum rp2040_pac::i2c0::ic_status::TFE_A">TFE_A</a></dt><dd>Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1</dd><dt><a class="enum" href="enum.TFNF_A.html" title="enum rp2040_pac::i2c0::ic_status::TFNF_A">TFNF_A</a></dt><dd>Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1</dd></dl><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><dl class="item-table"><dt><a class="type" href="type.ACTIVITY_R.html" title="type rp2040_pac::i2c0::ic_status::ACTIVITY_R">ACTIVITY_<wbr>R</a></dt><dd>Field <code>ACTIVITY</code> reader - I2C Activity Status. Reset value: 0x0</dd><dt><a class="type" href="type.MST_ACTIVITY_R.html" title="type rp2040_pac::i2c0::ic_status::MST_ACTIVITY_R">MST_<wbr>ACTIVITY_<wbr>R</a></dt><dd>Field <code>MST_ACTIVITY</code> reader - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.</dd><dt><a class="type" href="type.R.html" title="type rp2040_pac::i2c0::ic_status::R">R</a></dt><dd>Register <code>IC_STATUS</code> reader</dd><dt><a class="type" href="type.RFF_R.html" title="type rp2040_pac::i2c0::ic_status::RFF_R">RFF_R</a></dt><dd>Field <code>RFF</code> reader - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0</dd><dt><a class="type" href="type.RFNE_R.html" title="type rp2040_pac::i2c0::ic_status::RFNE_R">RFNE_R</a></dt><dd>Field <code>RFNE</code> reader - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0</dd><dt><a class="type" href="type.SLV_ACTIVITY_R.html" title="type rp2040_pac::i2c0::ic_status::SLV_ACTIVITY_R">SLV_<wbr>ACTIVITY_<wbr>R</a></dt><dd>Field <code>SLV_ACTIVITY</code> reader - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0</dd><dt><a class="type" href="type.TFE_R.html" title="type rp2040_pac::i2c0::ic_status::TFE_R">TFE_R</a></dt><dd>Field <code>TFE</code> reader - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1</dd><dt><a class="type" href="type.TFNF_R.html" title="type rp2040_pac::i2c0::ic_status::TFNF_R">TFNF_R</a></dt><dd>Field <code>TFNF</code> reader - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1</dd></dl></section></div></main></body></html> |