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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="CLOCKS"><title>rp2040_pac::clocks - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module clocks</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module clocks</a></h2><h3><a href="#modules">Module Items</a></h3><ul class="block"><li><a href="#modules" title="Modules">Modules</a></li><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2 class="in-crate"><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../index.html">rp2040_pac</a></div><h1>Module <span>clocks</span>&nbsp;<button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../src/rp2040_pac/clocks.rs.html#1-781">Source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>CLOCKS</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><dl class="item-table"><dt><a class="mod" href="clk_adc_ctrl/index.html" title="mod rp2040_pac::clocks::clk_adc_ctrl">clk_<wbr>adc_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_adc_div/index.html" title="mod rp2040_pac::clocks::clk_adc_div">clk_<wbr>adc_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_adc_selected/index.html" title="mod rp2040_pac::clocks::clk_adc_selected">clk_<wbr>adc_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="mod" href="clk_gpout0_ctrl/index.html" title="mod rp2040_pac::clocks::clk_gpout0_ctrl">clk_<wbr>gpout0_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_gpout0_div/index.html" title="mod rp2040_pac::clocks::clk_gpout0_div">clk_<wbr>gpout0_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_gpout0_selected/index.html" title="mod rp2040_pac::clocks::clk_gpout0_selected">clk_<wbr>gpout0_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="mod" href="clk_gpout1_ctrl/index.html" title="mod rp2040_pac::clocks::clk_gpout1_ctrl">clk_<wbr>gpout1_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_gpout1_div/index.html" title="mod rp2040_pac::clocks::clk_gpout1_div">clk_<wbr>gpout1_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_gpout1_selected/index.html" title="mod rp2040_pac::clocks::clk_gpout1_selected">clk_<wbr>gpout1_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="mod" href="clk_gpout2_ctrl/index.html" title="mod rp2040_pac::clocks::clk_gpout2_ctrl">clk_<wbr>gpout2_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_gpout2_div/index.html" title="mod rp2040_pac::clocks::clk_gpout2_div">clk_<wbr>gpout2_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_gpout2_selected/index.html" title="mod rp2040_pac::clocks::clk_gpout2_selected">clk_<wbr>gpout2_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="mod" href="clk_gpout3_ctrl/index.html" title="mod rp2040_pac::clocks::clk_gpout3_ctrl">clk_<wbr>gpout3_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_gpout3_div/index.html" title="mod rp2040_pac::clocks::clk_gpout3_div">clk_<wbr>gpout3_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_gpout3_selected/index.html" title="mod rp2040_pac::clocks::clk_gpout3_selected">clk_<wbr>gpout3_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="mod" href="clk_peri_ctrl/index.html" title="mod rp2040_pac::clocks::clk_peri_ctrl">clk_<wbr>peri_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_peri_selected/index.html" title="mod rp2040_pac::clocks::clk_peri_selected">clk_<wbr>peri_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="mod" href="clk_ref_ctrl/index.html" title="mod rp2040_pac::clocks::clk_ref_ctrl">clk_<wbr>ref_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_ref_div/index.html" title="mod rp2040_pac::clocks::clk_ref_div">clk_<wbr>ref_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_ref_selected/index.html" title="mod rp2040_pac::clocks::clk_ref_selected">clk_<wbr>ref_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</dd><dt><a class="mod" href="clk_rtc_ctrl/index.html" title="mod rp2040_pac::clocks::clk_rtc_ctrl">clk_<wbr>rtc_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_rtc_div/index.html" title="mod rp2040_pac::clocks::clk_rtc_div">clk_<wbr>rtc_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_rtc_selected/index.html" title="mod rp2040_pac::clocks::clk_rtc_selected">clk_<wbr>rtc_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="mod" href="clk_sys_ctrl/index.html" title="mod rp2040_pac::clocks::clk_sys_ctrl">clk_<wbr>sys_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_sys_div/index.html" title="mod rp2040_pac::clocks::clk_sys_div">clk_<wbr>sys_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_sys_resus_ctrl/index.html" title="mod rp2040_pac::clocks::clk_sys_resus_ctrl">clk_<wbr>sys_<wbr>resus_<wbr>ctrl</a></dt><dt><a class="mod" href="clk_sys_resus_status/index.html" title="mod rp2040_pac::clocks::clk_sys_resus_status">clk_<wbr>sys_<wbr>resus_<wbr>status</a></dt><dt><a class="mod" href="clk_sys_selected/index.html" title="mod rp2040_pac::clocks::clk_sys_selected">clk_<wbr>sys_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</dd><dt><a class="mod" href="clk_usb_ctrl/index.html" title="mod rp2040_pac::clocks::clk_usb_ctrl">clk_<wbr>usb_<wbr>ctrl</a></dt><dd>Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="mod" href="clk_usb_div/index.html" title="mod rp2040_pac::clocks::clk_usb_div">clk_<wbr>usb_<wbr>div</a></dt><dd>Clock divisor, can be changed on-the-fly</dd><dt><a class="mod" href="clk_usb_selected/index.html" title="mod rp2040_pac::clocks::clk_usb_selected">clk_<wbr>usb_<wbr>selected</a></dt><dd>Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="mod" href="enabled0/index.html" title="mod rp2040_pac::clocks::enabled0">enabled0</a></dt><dd>indicates the state of the clock enable</dd><dt><a class="mod" href="enabled1/index.html" title="mod rp2040_pac::clocks::enabled1">enabled1</a></dt><dd>indicates the state of the clock enable</dd><dt><a class="mod" href="fc0_delay/index.html" title="mod rp2040_pac::clocks::fc0_delay">fc0_<wbr>delay</a></dt><dd>Delays the start of frequency counting to allow the mux to settle<br />
Delay is measured in multiples of the reference clock period</dd><dt><a class="mod" href="fc0_interval/index.html" title="mod rp2040_pac::clocks::fc0_interval">fc0_<wbr>interval</a></dt><dd>The test interval is 0.98us * 2<strong>interval, but let’s call it 1us * 2</strong>interval<br />
The default gives a test interval of 250us</dd><dt><a class="mod" href="fc0_max_khz/index.html" title="mod rp2040_pac::clocks::fc0_max_khz">fc0_<wbr>max_<wbr>khz</a></dt><dd>Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</dd><dt><a class="mod" href="fc0_min_khz/index.html" title="mod rp2040_pac::clocks::fc0_min_khz">fc0_<wbr>min_<wbr>khz</a></dt><dd>Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</dd><dt><a class="mod" href="fc0_ref_khz/index.html" title="mod rp2040_pac::clocks::fc0_ref_khz">fc0_<wbr>ref_<wbr>khz</a></dt><dd>Reference clock frequency in kHz</dd><dt><a class="mod" href="fc0_result/index.html" title="mod rp2040_pac::clocks::fc0_result">fc0_<wbr>result</a></dt><dd>Result of frequency measurement, only valid when status_done=1</dd><dt><a class="mod" href="fc0_src/index.html" title="mod rp2040_pac::clocks::fc0_src">fc0_src</a></dt><dd>Clock sent to frequency counter, set to 0 when not required<br />
Writing to this register initiates the frequency count</dd><dt><a class="mod" href="fc0_status/index.html" title="mod rp2040_pac::clocks::fc0_status">fc0_<wbr>status</a></dt><dd>Frequency counter status</dd><dt><a class="mod" href="inte/index.html" title="mod rp2040_pac::clocks::inte">inte</a></dt><dd>Interrupt Enable</dd><dt><a class="mod" href="intf/index.html" title="mod rp2040_pac::clocks::intf">intf</a></dt><dd>Interrupt Force</dd><dt><a class="mod" href="intr/index.html" title="mod rp2040_pac::clocks::intr">intr</a></dt><dd>Raw Interrupts</dd><dt><a class="mod" href="ints/index.html" title="mod rp2040_pac::clocks::ints">ints</a></dt><dd>Interrupt status after masking &amp; forcing</dd><dt><a class="mod" href="sleep_en0/index.html" title="mod rp2040_pac::clocks::sleep_en0">sleep_<wbr>en0</a></dt><dd>enable clock in sleep mode</dd><dt><a class="mod" href="sleep_en1/index.html" title="mod rp2040_pac::clocks::sleep_en1">sleep_<wbr>en1</a></dt><dd>enable clock in sleep mode</dd><dt><a class="mod" href="wake_en0/index.html" title="mod rp2040_pac::clocks::wake_en0">wake_<wbr>en0</a></dt><dd>enable clock in wake mode</dd><dt><a class="mod" href="wake_en1/index.html" title="mod rp2040_pac::clocks::wake_en1">wake_<wbr>en1</a></dt><dd>enable clock in wake mode</dd></dl><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><dl class="item-table"><dt><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::clocks::RegisterBlock">Register<wbr>Block</a></dt><dd>Register block</dd></dl><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><dl class="item-table"><dt><a class="type" href="type.CLK_ADC_CTRL.html" title="type rp2040_pac::clocks::CLK_ADC_CTRL">CLK_<wbr>ADC_<wbr>CTRL</a></dt><dd>CLK_ADC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_ADC_DIV.html" title="type rp2040_pac::clocks::CLK_ADC_DIV">CLK_<wbr>ADC_<wbr>DIV</a></dt><dd>CLK_ADC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_ADC_SELECTED.html" title="type rp2040_pac::clocks::CLK_ADC_SELECTED">CLK_<wbr>ADC_<wbr>SELECTED</a></dt><dd>CLK_ADC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="type" href="type.CLK_GPOUT0_CTRL.html" title="type rp2040_pac::clocks::CLK_GPOUT0_CTRL">CLK_<wbr>GPOU<wbr>T0_<wbr>CTRL</a></dt><dd>CLK_GPOUT0_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_GPOUT0_DIV.html" title="type rp2040_pac::clocks::CLK_GPOUT0_DIV">CLK_<wbr>GPOU<wbr>T0_<wbr>DIV</a></dt><dd>CLK_GPOUT0_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_GPOUT0_SELECTED.html" title="type rp2040_pac::clocks::CLK_GPOUT0_SELECTED">CLK_<wbr>GPOU<wbr>T0_<wbr>SELECTED</a></dt><dd>CLK_GPOUT0_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="type" href="type.CLK_GPOUT1_CTRL.html" title="type rp2040_pac::clocks::CLK_GPOUT1_CTRL">CLK_<wbr>GPOU<wbr>T1_<wbr>CTRL</a></dt><dd>CLK_GPOUT1_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_GPOUT1_DIV.html" title="type rp2040_pac::clocks::CLK_GPOUT1_DIV">CLK_<wbr>GPOU<wbr>T1_<wbr>DIV</a></dt><dd>CLK_GPOUT1_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_GPOUT1_SELECTED.html" title="type rp2040_pac::clocks::CLK_GPOUT1_SELECTED">CLK_<wbr>GPOU<wbr>T1_<wbr>SELECTED</a></dt><dd>CLK_GPOUT1_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="type" href="type.CLK_GPOUT2_CTRL.html" title="type rp2040_pac::clocks::CLK_GPOUT2_CTRL">CLK_<wbr>GPOU<wbr>T2_<wbr>CTRL</a></dt><dd>CLK_GPOUT2_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_GPOUT2_DIV.html" title="type rp2040_pac::clocks::CLK_GPOUT2_DIV">CLK_<wbr>GPOU<wbr>T2_<wbr>DIV</a></dt><dd>CLK_GPOUT2_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_GPOUT2_SELECTED.html" title="type rp2040_pac::clocks::CLK_GPOUT2_SELECTED">CLK_<wbr>GPOU<wbr>T2_<wbr>SELECTED</a></dt><dd>CLK_GPOUT2_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="type" href="type.CLK_GPOUT3_CTRL.html" title="type rp2040_pac::clocks::CLK_GPOUT3_CTRL">CLK_<wbr>GPOU<wbr>T3_<wbr>CTRL</a></dt><dd>CLK_GPOUT3_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_GPOUT3_DIV.html" title="type rp2040_pac::clocks::CLK_GPOUT3_DIV">CLK_<wbr>GPOU<wbr>T3_<wbr>DIV</a></dt><dd>CLK_GPOUT3_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_GPOUT3_SELECTED.html" title="type rp2040_pac::clocks::CLK_GPOUT3_SELECTED">CLK_<wbr>GPOU<wbr>T3_<wbr>SELECTED</a></dt><dd>CLK_GPOUT3_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="type" href="type.CLK_PERI_CTRL.html" title="type rp2040_pac::clocks::CLK_PERI_CTRL">CLK_<wbr>PERI_<wbr>CTRL</a></dt><dd>CLK_PERI_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_PERI_SELECTED.html" title="type rp2040_pac::clocks::CLK_PERI_SELECTED">CLK_<wbr>PERI_<wbr>SELECTED</a></dt><dd>CLK_PERI_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="type" href="type.CLK_REF_CTRL.html" title="type rp2040_pac::clocks::CLK_REF_CTRL">CLK_<wbr>REF_<wbr>CTRL</a></dt><dd>CLK_REF_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_REF_DIV.html" title="type rp2040_pac::clocks::CLK_REF_DIV">CLK_<wbr>REF_<wbr>DIV</a></dt><dd>CLK_REF_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_REF_SELECTED.html" title="type rp2040_pac::clocks::CLK_REF_SELECTED">CLK_<wbr>REF_<wbr>SELECTED</a></dt><dd>CLK_REF_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</dd><dt><a class="type" href="type.CLK_RTC_CTRL.html" title="type rp2040_pac::clocks::CLK_RTC_CTRL">CLK_<wbr>RTC_<wbr>CTRL</a></dt><dd>CLK_RTC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_RTC_DIV.html" title="type rp2040_pac::clocks::CLK_RTC_DIV">CLK_<wbr>RTC_<wbr>DIV</a></dt><dd>CLK_RTC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_RTC_SELECTED.html" title="type rp2040_pac::clocks::CLK_RTC_SELECTED">CLK_<wbr>RTC_<wbr>SELECTED</a></dt><dd>CLK_RTC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="type" href="type.CLK_SYS_CTRL.html" title="type rp2040_pac::clocks::CLK_SYS_CTRL">CLK_<wbr>SYS_<wbr>CTRL</a></dt><dd>CLK_SYS_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_SYS_DIV.html" title="type rp2040_pac::clocks::CLK_SYS_DIV">CLK_<wbr>SYS_<wbr>DIV</a></dt><dd>CLK_SYS_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_SYS_RESUS_CTRL.html" title="type rp2040_pac::clocks::CLK_SYS_RESUS_CTRL">CLK_<wbr>SYS_<wbr>RESUS_<wbr>CTRL</a></dt><dd>CLK_SYS_RESUS_CTRL (rw) register accessor:</dd><dt><a class="type" href="type.CLK_SYS_RESUS_STATUS.html" title="type rp2040_pac::clocks::CLK_SYS_RESUS_STATUS">CLK_<wbr>SYS_<wbr>RESUS_<wbr>STATUS</a></dt><dd>CLK_SYS_RESUS_STATUS (r) register accessor:</dd><dt><a class="type" href="type.CLK_SYS_SELECTED.html" title="type rp2040_pac::clocks::CLK_SYS_SELECTED">CLK_<wbr>SYS_<wbr>SELECTED</a></dt><dd>CLK_SYS_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</dd><dt><a class="type" href="type.CLK_USB_CTRL.html" title="type rp2040_pac::clocks::CLK_USB_CTRL">CLK_<wbr>USB_<wbr>CTRL</a></dt><dd>CLK_USB_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</dd><dt><a class="type" href="type.CLK_USB_DIV.html" title="type rp2040_pac::clocks::CLK_USB_DIV">CLK_<wbr>USB_<wbr>DIV</a></dt><dd>CLK_USB_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</dd><dt><a class="type" href="type.CLK_USB_SELECTED.html" title="type rp2040_pac::clocks::CLK_USB_SELECTED">CLK_<wbr>USB_<wbr>SELECTED</a></dt><dd>CLK_USB_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</dd><dt><a class="type" href="type.ENABLED0.html" title="type rp2040_pac::clocks::ENABLED0">ENABLE<wbr>D0</a></dt><dd>ENABLED0 (r) register accessor: indicates the state of the clock enable</dd><dt><a class="type" href="type.ENABLED1.html" title="type rp2040_pac::clocks::ENABLED1">ENABLE<wbr>D1</a></dt><dd>ENABLED1 (r) register accessor: indicates the state of the clock enable</dd><dt><a class="type" href="type.FC0_DELAY.html" title="type rp2040_pac::clocks::FC0_DELAY">FC0_<wbr>DELAY</a></dt><dd>FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle<br />
Delay is measured in multiples of the reference clock period</dd><dt><a class="type" href="type.FC0_INTERVAL.html" title="type rp2040_pac::clocks::FC0_INTERVAL">FC0_<wbr>INTERVAL</a></dt><dd>FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2<strong>interval, but let’s call it 1us * 2</strong>interval<br />
The default gives a test interval of 250us</dd><dt><a class="type" href="type.FC0_MAX_KHZ.html" title="type rp2040_pac::clocks::FC0_MAX_KHZ">FC0_<wbr>MAX_<wbr>KHZ</a></dt><dd>FC0_MAX_KHZ (rw) register accessor: Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</dd><dt><a class="type" href="type.FC0_MIN_KHZ.html" title="type rp2040_pac::clocks::FC0_MIN_KHZ">FC0_<wbr>MIN_<wbr>KHZ</a></dt><dd>FC0_MIN_KHZ (rw) register accessor: Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</dd><dt><a class="type" href="type.FC0_REF_KHZ.html" title="type rp2040_pac::clocks::FC0_REF_KHZ">FC0_<wbr>REF_<wbr>KHZ</a></dt><dd>FC0_REF_KHZ (rw) register accessor: Reference clock frequency in kHz</dd><dt><a class="type" href="type.FC0_RESULT.html" title="type rp2040_pac::clocks::FC0_RESULT">FC0_<wbr>RESULT</a></dt><dd>FC0_RESULT (r) register accessor: Result of frequency measurement, only valid when status_done=1</dd><dt><a class="type" href="type.FC0_SRC.html" title="type rp2040_pac::clocks::FC0_SRC">FC0_SRC</a></dt><dd>FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required<br />
Writing to this register initiates the frequency count</dd><dt><a class="type" href="type.FC0_STATUS.html" title="type rp2040_pac::clocks::FC0_STATUS">FC0_<wbr>STATUS</a></dt><dd>FC0_STATUS (r) register accessor: Frequency counter status</dd><dt><a class="type" href="type.INTE.html" title="type rp2040_pac::clocks::INTE">INTE</a></dt><dd>INTE (rw) register accessor: Interrupt Enable</dd><dt><a class="type" href="type.INTF.html" title="type rp2040_pac::clocks::INTF">INTF</a></dt><dd>INTF (rw) register accessor: Interrupt Force</dd><dt><a class="type" href="type.INTR.html" title="type rp2040_pac::clocks::INTR">INTR</a></dt><dd>INTR (r) register accessor: Raw Interrupts</dd><dt><a class="type" href="type.INTS.html" title="type rp2040_pac::clocks::INTS">INTS</a></dt><dd>INTS (r) register accessor: Interrupt status after masking &amp; forcing</dd><dt><a class="type" href="type.SLEEP_EN0.html" title="type rp2040_pac::clocks::SLEEP_EN0">SLEEP_<wbr>EN0</a></dt><dd>SLEEP_EN0 (rw) register accessor: enable clock in sleep mode</dd><dt><a class="type" href="type.SLEEP_EN1.html" title="type rp2040_pac::clocks::SLEEP_EN1">SLEEP_<wbr>EN1</a></dt><dd>SLEEP_EN1 (rw) register accessor: enable clock in sleep mode</dd><dt><a class="type" href="type.WAKE_EN0.html" title="type rp2040_pac::clocks::WAKE_EN0">WAKE_<wbr>EN0</a></dt><dd>WAKE_EN0 (rw) register accessor: enable clock in wake mode</dd><dt><a class="type" href="type.WAKE_EN1.html" title="type rp2040_pac::clocks::WAKE_EN1">WAKE_<wbr>EN1</a></dt><dd>WAKE_EN1 (rw) register accessor: enable clock in wake mode</dd></dl></section></div></main></body></html>
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