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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Miscellaneous Register 0"><title>imxrt_ral::xtalosc24m::MISC0_CLR - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-6b053e98.ttf.woff2,FiraSans-Italic-81dc35de.woff2,FiraSans-Regular-0fe48ade.woff2,FiraSans-MediumItalic-ccf7e434.woff2,FiraSans-Medium-e1aa3f0a.woff2,SourceCodePro-Regular-8badfe75.ttf.woff2,SourceCodePro-Semibold-aa29a496.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2"href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-9960930a.css"><link rel="stylesheet" href="../../../static.files/rustdoc-e56847b5.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="imxrt_ral" data-themes="" data-resource-suffix="" data-rustdoc-version="1.91.1 (ed61e7d7e 2025-11-07)" data-channel="1.91.1" data-search-js="search-e256b49e.js" data-stringdex-js="stringdex-c3e638e9.js" data-settings-js="settings-c38705f0.js" ><script src="../../../static.files/storage-e2aeef58.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-6dc2a7f3.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-263c88ec.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-eab170b8.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-044be391.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><rustdoc-topbar><h2><a href="#">Module MISC0_CLR</a></h2></rustdoc-topbar><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../imxrt_ral/index.html">imxrt_<wbr>ral</a><span class="version">0.6.1</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module MISC0_<wbr>CLR</a></h2><h3><a href="#modules">Module Items</a></h3><ul class="block"><li><a href="#modules" title="Modules">Modules</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In imxrt_<wbr>ral::<wbr>xtalosc24m</a></h2></div></div></nav><div class="sidebar-resizer" title="Drag to resize sidebar"></div><main><div class="width-limiter"><section id="main-content" class="content"><div class="main-heading"><div class="rustdoc-breadcrumbs"><a href="../../index.html">imxrt_ral</a>::<wbr><a href="../index.html">xtalosc24m</a></div><h1>Module <span>MISC0_<wbr>CLR</span>&nbsp;<button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/imxrt_ral/blocks/imxrt1011/xtalosc24m.rs.html#433">Source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Miscellaneous Register 0</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><dl class="item-table"><dt><a class="mod" href="CLKGATE_CTRL/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::CLKGATE_CTRL">CLKGATE_<wbr>CTRL</a></dt><dd>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</dd><dt><a class="mod" href="CLKGATE_DELAY/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::CLKGATE_DELAY">CLKGATE_<wbr>DELAY</a></dt><dd>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</dd><dt><a class="mod" href="DISCON_HIGH_SNVS/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::DISCON_HIGH_SNVS">DISCON_<wbr>HIGH_<wbr>SNVS</a></dt><dd>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</dd><dt><a class="mod" href="OSC_I/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::OSC_I">OSC_I</a></dt><dd>This field determines the bias current in the 24MHz oscillator</dd><dt><a class="mod" href="OSC_XTALOK/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::OSC_XTALOK">OSC_<wbr>XTALOK</a></dt><dd>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</dd><dt><a class="mod" href="OSC_XTALOK_EN/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::OSC_XTALOK_EN">OSC_<wbr>XTALOK_<wbr>EN</a></dt><dd>This bit enables the detector that signals when the 24MHz crystal oscillator is stable.</dd><dt><a class="mod" href="REFTOP_PWD/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::REFTOP_PWD">REFTOP_<wbr>PWD</a></dt><dd>Control bit to power-down the analog bandgap reference circuitry</dd><dt><a class="mod" href="REFTOP_SELFBIASOFF/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::REFTOP_SELFBIASOFF">REFTOP_<wbr>SELFBIASOFF</a></dt><dd>Control bit to disable the self-bias circuit in the analog bandgap</dd><dt><a class="mod" href="REFTOP_VBGADJ/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::REFTOP_VBGADJ">REFTOP_<wbr>VBGADJ</a></dt><dd>Not related to oscillator.</dd><dt><a class="mod" href="REFTOP_VBGUP/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::REFTOP_VBGUP">REFTOP_<wbr>VBGUP</a></dt><dd>Status bit that signals the analog bandgap voltage is up and stable</dd><dt><a class="mod" href="RTC_XTAL_SOURCE/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::RTC_XTAL_SOURCE">RTC_<wbr>XTAL_<wbr>SOURCE</a></dt><dd>This field indicates which chip source is being used for the rtc clock.</dd><dt><a class="mod" href="STOP_MODE_CONFIG/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::STOP_MODE_CONFIG">STOP_<wbr>MODE_<wbr>CONFIG</a></dt><dd>Configure the analog behavior in stop mode.Not related to oscillator.</dd><dt><a class="mod" href="VID_PLL_PREDIV/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::VID_PLL_PREDIV">VID_<wbr>PLL_<wbr>PREDIV</a></dt><dd>Predivider for the source clock of the PLL’s. Not related to oscillator.</dd><dt><a class="mod" href="XTAL_24M_PWD/index.html" title="mod imxrt_ral::xtalosc24m::MISC0_CLR::XTAL_24M_PWD">XTAL_<wbr>24M_<wbr>PWD</a></dt><dd>This field powers down the 24M crystal oscillator if set true.</dd></dl></section></div></main></body></html>
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