rtic/2/api/search.desc/stm32_metapac/stm32_metapac-desc-1-.js

searchState.loadedDescShard("stm32_metapac", 1, "Bank 1 inconsistency error flag\nBank 1 inconsistency error interrupt enable bit\nI/O high-speed at low-voltage status bit …\nI/O high-speed at low-voltage (PRODUCT_BELOW_25V)\nIWDG1 control option status bit\nIWDG1 option configuration bit\nRead latency\nBank 1 configuration lock bit\nFlash mass erase enable bit\nD1 DStandby entry reset option status bit\nOption byte erase after D1 DStandby option configuration …\nD1 DStop entry reset option status bit\nOption byte erase after D1 DStop option configuration bit\nBank 1 write/erase error flag\nBank 1 write/erase error interrupt enable bit\nOption byte change ongoing flag\nOption byte change error flag\nOption byte change error interrupt enable bit\nFLASH_OPTCR lock option configuration bit\nOption byte start change option configuration bit\nDevice personalization status bit\nBank 1 program enable bit\nBank 1 programming sequence error flag\nBank 1 programming sequence error interrupt enable bit\nBank 1 highest PCROP protected address\nBank 1 highest PCROP protected address configuration\nBank 1 lowest PCROP protected address\nBank 1 lowest PCROP protected address configuration\nBank 1 program size\nBank 1 wait queue flag\nReadout protection level option status byte\nReadout protection level option configuration byte\nBank 1 read protection error flag\nBank 1 read protection error interrupt enable bit\nBank 1 secure error flag\nBank 1 secure error interrupt enable bit\nUser option bit 1\nUser option configuration bit 1\nUser option configuration bit 2\nBank 1 highest secure protected address\nBank 1 highest secure protected address configuration\nBank 1 lowest secure protected address\nBank 1 lowest secure protected address configuration\nSecurity enable option status bit\nSecurity option configuration bit\nBank 1 sector erase request\nBank 1 sector erase selection number\nBank 1 single correction error flag\nBank 1 ECC single correction error interrupt enable bit\nDTCM RAM size option status\nDTCM size select option configuration bits\nBank 1 bank or sector erase start control bit\nBank 1 CRC start bit\nBank 1 strobe error flag\nBank 1 strobe error interrupt enable bit\nBank swapping configuration bit\nBank swapping option status bit\nBank swapping option configuration bit\nBank 1 write buffer not empty flag\nFlash signal delay\nBank 1 write protection error flag\nBank 1 write protection error interrupt enable bit\nBank 1 sector write protection option status byte\nBank 1 sector write protection configuration byte\nBank 1 sector erase selection number\nBank 1 single correction error flag\nBank 1 ECC single correction error interrupt enable bit\nDTCM RAM size option status\nDTCM size select option configuration bits\nBank 1 bank or sector erase start control bit\nBank 1 CRC start bit\nBank 1 strobe error flag\nBank 1 strobe error interrupt enable bit\nBank swapping configuration bit\nBank swapping option status bit\nBank swapping option configuration bit\nBank 1 write buffer not empty flag\nFlash signal delay\nBank 1 write protection error flag\nBank 1 write protection error interrupt enable bit\nBank 1 sector write protection option status byte\nBank 1 sector write protection configuration byte\nFilter math accelerator\nControl register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nParameter register\nRead data register\nStatus register\nWrite data register\nX1 buffer configuration register\nX2 buffer configuration register\nY buffer configuration register\nControl register\nParameter register\nRead data register\nStatus register\nWrite data register\nX1 buffer configuration register\nX2 buffer configuration register\nY buffer configuration register\nEnable clipping\nEnable DMA read channel requests\nEnable DMA write channel requests\nWatermark for buffer empty flag\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nWatermark for buffer full flag\nFunction\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nOverflow error flag\nEnable overflow error interrupts\nInput parameter P\nInput parameter Q\nInput parameter R\nRead data (contents of the Y output buffer at the address …\nReset FMAC unit\nEnable read interrupt\nSaturation error flag\nEnable saturation error interrupts\nEnable clipping\nEnable DMA read channel requests\nEnable DMA write channel requests\nWatermark for buffer empty flag\nWatermark for buffer full flag\nFunction\nOverflow error flag\nEnable overflow error interrupts\nInput parameter P\nInput parameter Q\nInput parameter R\nRead data (contents of the Y output buffer at the address …\nReset FMAC unit\nEnable read interrupt\nSaturation error flag\nEnable saturation error interrupts\nEnable execution\nUnderflow error flag\nEnable underflow error interrupts\nWrite data (write data are transferred to the address …\nEnable write interrupt\nBase address of X1 buffer\nAllocated size of X1 buffer in 16-bit words\nX1 buffer full flag\nBase address of X2 buffer\nSize of X2 buffer in 16-bit words\nBase address of Y buffer\nSize of Y buffer in 16-bit words\nY buffer empty flag\nEnable execution\nUnderflow error flag\nEnable underflow error interrupts\nWrite data (write data are transferred to the address …\nEnable write interrupt\nBase address of X1 buffer\nAllocated size of X1 buffer in 16-bit words\nX1 buffer full flag\nBase address of X2 buffer\nSize of X2 buffer in 16-bit words\nBase address of Y buffer\nSize of Y buffer in 16-bit words\nY buffer empty flag\nFlexible memory controller\nSRAM/NOR-Flash chip-select control register 2-4\nSRAM/NOR-Flash chip-select control register 1\nSRAM/NOR-Flash chip-select timing register 1-4\nSRAM/NOR-Flash write timing registers 1-4\nECC result register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nAttribute memory space timing register\nPC Card/NAND Flash control register\nCommon memory space timing register\nSDRAM Command Mode register\nSDRAM Control Register 1-2\nSDRAM Refresh Timer register\nSDRAM Status register\nSDRAM Timing register 1-2\nFIFO status and interrupt register\nSRAM/NOR-Flash chip-select control register 2-4\nSRAM/NOR-Flash chip-select control register 1\nSRAM/NOR-Flash chip-select timing register\nSRAM/NOR-Flash write timing registers\nECC result register\nAttribute memory space timing register\nPC Card/NAND Flash control register\nCommon memory space timing register\nSDRAM Command Mode register\nSDRAM Control Register\nSDRAM Refresh Timer register\nSDRAM Status register\nSDRAM Timing register\nFIFO status and interrupt register\nAccess mode\nAccess mode\nAddress-hold phase duration\nAddress-hold phase duration\nAddress setup phase duration\nAddress setup phase duration\nWait signal during asynchronous transfers\nWait signal during asynchronous transfers\nAttribute memory data bus Hi-Z time\nAttribute memory hold time\nAttribute memory setup time\nAttribute memory wait time\nFMC bank mapping These bits allows different to remap …\nBurst enable bit\nBurst enable bit\nBus turnaround phase duration\nBus turnaround phase duration\nCAS latency\nWrite burst enable\nWrite burst enable\nContinuous clock enable\nClock divide ratio (for FMC_CLK signal)\nRefresh Timer Count\nCRAM page size\nCRAM page size\nClear Refresh error flag\nCommand target bank 1\nCommand target bank 2\nData-phase duration\nData-phase duration\nData latency for synchronous memory\nECC computation result value\nECC computation logic enable bit\nECC page size\nExtended mode enable\nExtended mode enable\nFlash access enable\nFlash access enable\nFIFO empty status\nFMC controller enable\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nInterrupt falling edge detection enable bit\nInterrupt falling edge status\nInterrupt high-level detection enable bit\nInterrupt high-level status\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nInterrupt rising edge detection enable bit\nInterrupt rising edge status\nMemory bank enable bit\nMemory bank enable bit\nCommon memory x data bus Hi-Z time\nCommon memory hold time\nCommon memory x setup time\nCommon memory wait time\nCommand mode\nStatus Mode for Bank 1\nStatus Mode for Bank 2\nMode Register definition\nMemory type\nMemory type\nAddress/data multiplexing enable bit\nAddress/data multiplexing enable bit\nMemory data bus width\nMemory data bus width\nMemory data bus width\nNumber of internal banks\nNumber of column address bits\nNumber of row address bits\nNumber of Auto-refresh\nNAND Flash memory bank enable bit\nWait feature enable bit\nData bus width\nBurst read\nRefresh error flag\nRES Interrupt Enable\nRead pipe\nSDRAM clock configuration\nAccess mode\nAccess mode\nAddress-hold phase duration\nAddress-hold phase duration\nAddress setup phase duration\nAddress setup phase duration\nWait signal during asynchronous transfers\nWait signal during asynchronous transfers\nAttribute memory data bus Hi-Z time\nAttribute memory hold time\nAttribute memory setup time\nAttribute memory wait time\nFMC bank mapping These bits allows different to remap …\nBurst enable bit\nBurst enable bit\nBus turnaround phase duration\nBus turnaround phase duration\nCAS latency\nWrite burst enable\nWrite burst enable\nContinuous clock enable\nClock divide ratio (for FMC_CLK signal)\nRefresh Timer Count\nCRAM page size\nCRAM page size\nClear Refresh error flag\nCommand target bank 1\nCommand target bank 2\nData-phase duration\nData-phase duration\nData latency for synchronous memory\nECC computation result value\nECC computation logic enable bit\nECC page size\nExtended mode enable\nExtended mode enable\nFlash access enable\nFlash access enable\nFIFO empty status\nFMC controller enable\nInterrupt falling edge detection enable bit\nInterrupt falling edge status\nInterrupt high-level detection enable bit\nInterrupt high-level status\nInterrupt rising edge detection enable bit\nInterrupt rising edge status\nMemory bank enable bit\nMemory bank enable bit\nCommon memory x data bus Hi-Z time\nCommon memory hold time\nCommon memory x setup time\nCommon memory wait time\nCommand mode\nStatus Mode for Bank 1\nStatus Mode for Bank 2\nMode Register definition\nMemory type\nMemory type\nAddress/data multiplexing enable bit\nAddress/data multiplexing enable bit\nMemory data bus width\nMemory data bus width\nMemory data bus width\nNumber of internal banks\nNumber of column address bits\nNumber of row address bits\nNumber of Auto-refresh\nNAND Flash memory bank enable bit\nWait feature enable bit\nData bus width\nBurst read\nRefresh error flag\nRES Interrupt Enable\nRead pipe\nSDRAM clock configuration\nALE to RE delay\nCLE to RE delay\nLoad Mode Register to Active\nSelf refresh time\nRow cycle delay\nRow to column delay\nRow precharge delay\nRecovery delay\nExit self-refresh delay\nWait timing configuration\nWait timing configuration\nWait enable bit\nWait enable bit\nWait signal polarity bit\nWait signal polarity bit\nWrite FIFO disable\nWrite protection\nWrite enable bit\nWrite enable bit\nALE to RE delay\nCLE to RE delay\nLoad Mode Register to Active\nSelf refresh time\nRow cycle delay\nRow to column delay\nRow precharge delay\nRecovery delay\nExit self-refresh delay\nWait timing configuration\nWait timing configuration\nWait enable bit\nWait enable bit\nWait signal polarity bit\nWait signal polarity bit\nWrite FIFO disable\nWrite protection\nWrite enable bit\nWrite enable bit\nAccess mode A\nNWAIT active high\nNWAIT active low\nAuto-refresh command\nAccess mode B\nNWAIT signal is active one data cycle before wait state\n10 bits\n11 bits\n11 bits\n12 bits\n13 bits\nMemory data bus width 16 bits\nExternal memory device width 16 bits\nMemory data bus width 32 bits\nMemory data bus width 8 bits\n8 bits\nExternal memory device width 8 bits\n9 bits\n1024 bytes CRAM page size\nECC page size 1024 bytes\n128 bytes CRAM page size\nECC page size 2048 bytes\n256 bytes CRAM page size\nECC page size 256 bytes\nECC page size 4096 bytes\n512 bytes CRAM page size\nECC page size 512 bytes\nECC page size 8192 bytes\nAccess mode C\nClock Configuration Enable\n1 cycle\nOne clock cycle delay\n2 cycles\nTwo clock cycles delay\n3 cycles\nAccess mode D\nSDCLK clock disabled\nSDCLK period = 2 x HCLK period\nSDCLK period = 3 x HCLK period\nNWAIT signal is active during wait state\nNOR Flash/OneNAND Flash\nLoad Mode Resgier\nTwo internal Banks\nFour internal Banks\nNo burst split when crossing page boundary\nNo clock cycle delay\nNormal Mode\nNormal Mode\nPALL (All Bank Precharge) command\nPower-down mode\nPower-down command\nPSRAM (CRAM) memory type\nSelf-refresh mode\nSelf-refresh command\nSRAM memory type\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nGeneral-purpose I/Os\nGPIO alternate function registers. The register described …\nGPIO port bit set/reset register\nReturns the argument unchanged.\nGPIO port input data register\nCalls <code>U::from(self)</code>.\nGPIO port configuration lock register\nGPIO port mode register\nGPIO port output data register\nGPIO port output speed register\nGPIO port output type register\nGPIO port pull-up/pull-down register\nGPIO alternate function register. This contains an array …\nGPIO port bit set/reset register\nGPIO port input data register\nGPIO port configuration lock register\nGPIO port mode register\nGPIO port output data register\nGPIO port output speed register\nGPIO port output type register\nGPIO port pull-up/pull-down register\nAlternate function selection for one of the pins …\nPort x set bit y (y= 0..15)\nPort x set bit y (y= 0..15)\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nPort input data (y = 0..15)\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nPort configuration locked\nPort configuration lock key active\nPort x configuration bits (y = 0..15)\nPort output data (y = 0..15)\nPort x configuration bits (y = 0..15)\nPort x configuration bits (y = 0..15)\nPort x configuration bits (y = 0..15)\nAlternate function selection for one of the pins …\nPort x set bit y (y= 0..15)\nPort x set bit y (y= 0..15)\nPort input data (y = 0..15)\nPort configuration locked\nPort configuration lock key active\nPort x configuration bits (y = 0..15)\nPort output data (y = 0..15)\nPort x configuration bits (y = 0..15)\nPort x configuration bits (y = 0..15)\nPort x configuration bits (y = 0..15)\nAlternate function mode\nAnalog mode\nNo pull-up, pull-down\nInput is logic high\nSet output to logic high\nHigh speed\nInput mode (reset state)\nInput is logic low\nSet output to logic low\nLow speed\nMedium speed\nOutput open-drain\nGeneral purpose output mode\nPull-down\nPull-up\nOutput push-pull (reset state)\nVery high speed\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nInter-integrated circuit\nControl register 1\nControl register 2\nReturns the argument unchanged.\nInterrupt clear register\nCalls <code>U::from(self)</code>.\nInterrupt and Status register\nOwn address register 1\nOwn address register 2\nPEC register\nReceive data register\nTimeout register\nTiming register\nTransmit data register\nControl register 1\nControl register 2\nInterrupt clear register\nInterrupt and Status register\nOwn address register 1\nOwn address register 2\nPEC register\nReceive data register\nTimeout register\nTiming register\nTransmit data register\n10-bit addressing mode (master mode)\nAddress match code (Slave mode)\nAddress matched (slave mode)\nAddress Matched flag clear\nAddress match interrupt enable (slave only)\nSMBus alert\nAlert flag clear\nSMBUS alert enable\nAnalog noise filter OFF\nArbitration lost\nArbitration lost flag clear\nAutomatic end mode (master mode)\nBus error\nBus error flag clear\nBus busy\nTransfer direction (master mode)\nTransfer direction (Slave mode)\nDigital noise filter\nError interrupts enable\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nGeneral call enable\n10-bit address header only read direction (master receiver …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nNACK generation (slave mode)\nNot Acknowledge flag clear\nNot acknowledge received flag\nNot acknowledge received interrupt enable\nNumber of bytes\nClock stretching disable\nInterface address\nOwn Address 1 enable\nOwn Address 1 10-bit mode\nInterface address\nOwn Address 2 enable\nOwn Address 2 masks\nOverrun/Underrun (slave mode)\nOverrun/Underrun flag clear\nPeripheral enable\nPacket error checking register\nPacket error checking byte\nPEC Error flag clear\nPEC enable\nPEC Error in reception\nTiming prescaler\nNBYTES reload mode\n8-bit receive data\nDMA reception requests enable\nRX Interrupt enable\nReceive data register not empty (receivers)\nSlave address bit (master mode)\nSlave byte control\nData setup time\nSCL high period (master mode)\nSCL low period (master mode)\nData hold time\n10-bit addressing mode (master mode)\nAddress match code (Slave mode)\nAddress matched (slave mode)\nAddress Matched flag clear\nAddress match interrupt enable (slave only)\nSMBus alert\nAlert flag clear\nSMBUS alert enable\nAnalog noise filter OFF\nArbitration lost\nArbitration lost flag clear\nAutomatic end mode (master mode)\nBus error\nBus error flag clear\nBus busy\nTransfer direction (master mode)\nTransfer direction (Slave mode)\nDigital noise filter\nError interrupts enable\nGeneral call enable\n10-bit address header only read direction (master receiver …\nNACK generation (slave mode)\nNot Acknowledge flag clear\nNot acknowledge received flag\nNot acknowledge received interrupt enable\nNumber of bytes\nClock stretching disable\nInterface address\nOwn Address 1 enable\nOwn Address 1 10-bit mode\nInterface address\nOwn Address 2 enable\nOwn Address 2 masks\nOverrun/Underrun (slave mode)\nOverrun/Underrun flag clear\nPeripheral enable\nPacket error checking register\nPacket error checking byte\nPEC Error flag clear\nPEC enable\nPEC Error in reception\nTiming prescaler\nNBYTES reload mode\n8-bit receive data\nDMA reception requests enable\nRX Interrupt enable\nReceive data register not empty (receivers)\nSlave address bit (master mode)\nSlave byte control\nData setup time\nSCL high period (master mode)\nSCL low period (master mode)\nData hold time\nSMBus Device Default address enable\nSMBus Host address enable\nStart generation\nStop generation (master mode)\nStop detection flag clear\nStop detection flag\nSTOP detection Interrupt enable\nTransfer Complete (master mode)\nTransfer Complete interrupt enable\nTransfer Complete Reload\nExtended clock timeout enable\nIdle clock timeout detection\nTimeout or t_low detection flag\nBus timeout A\nBus timeout B\nTimeout detection flag clear\nClock timeout enable\n8-bit transmit data\nDMA transmission requests enable\nTransmit data register empty (transmitters)\nTX Interrupt enable\nTransmit interrupt status (transmitters)\nSMBus Device Default address enable\nSMBus Host address enable\nStart generation\nStop generation (master mode)\nStop detection flag clear\nStop detection flag\nSTOP detection Interrupt enable\nTransfer Complete (master mode)\nTransfer Complete interrupt enable\nTransfer Complete Reload\nExtended clock timeout enable\nIdle clock timeout detection\nTimeout or t_low detection flag\nBus timeout A\nBus timeout B\nTimeout detection flag clear\nClock timeout enable\n8-bit transmit data\nDMA transmission requests enable\nTransmit data register empty (transmitters)\nTX Interrupt enable\nTransmit interrupt status (transmitters)\nAutomatic end mode: a STOP condition is automatically sent …\n10-bit addressing mode\n7-bit addressing mode\nThe master sends the complete 10 bit slave address read …\nThe transfer is completed after the NBYTES data transfer …\nDigital filter enabled and filtering capability up to 1 …\nDigital filter enabled and filtering capability up to 10 …\nDigital filter enabled and filtering capability up to 11 …\nDigital filter enabled and filtering capability up to 12 …\nDigital filter enabled and filtering capability up to 13 …\nDigital filter enabled and filtering capability up to 14 …\nDigital filter enabled and filtering capability up to 15 …\nDigital filter enabled and filtering capability up to 2 …\nDigital filter enabled and filtering capability up to 3 …\nDigital filter enabled and filtering capability up to 4 …\nDigital filter enabled and filtering capability up to 5 …\nDigital filter enabled and filtering capability up to 6 …\nDigital filter enabled and filtering capability up to 7 …\nDigital filter enabled and filtering capability up to 8 …\nDigital filter enabled and filtering capability up to 9 …\nOA2[1] is masked and don’t care. Only OA2[7:2] are …\nOA2[2:1] are masked and don’t care. Only OA2[7:3] are …\nOA2[3:1] are masked and don’t care. Only OA2[7:4] are …\nOA2[4:1] are masked and don’t care. Only OA2[7:5] are …\nOA2[5:1] are masked and don’t care. Only OA2[7:6] are …\nOA2[6:1] are masked and don’t care. Only OA2[7] is …\nOA2[7:1] are masked and don’t care. No comparison is …\nDigital filter disabled\nNo mask\nThe transfer is not completed after the NBYTES data …\nThe master only sends the 1st 7 bits of the 10 bit …\nRead transfer, slave enters transmitter mode\nSoftware end mode: TC flag is set when NBYTES data are …\nWrite transfer, slave enters receiver mode\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nIndependent watchdog\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nKey register\nPrescaler register\nReload register\nStatus register\nWindow register\nKey register\nPrescaler register\nReload register\nStatus register\nWindow register\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nKey value (write only, read 0000h)\nPrescaler divider\nWatchdog prescaler value update\nWatchdog counter reload value\nWatchdog counter reload value update\nKey value (write only, read 0000h)\nPrescaler divider\nWatchdog prescaler value update\nWatchdog counter reload value\nWatchdog counter reload value update\nWatchdog counter window value\nWatchdog counter window value update\nWatchdog counter window value\nWatchdog counter window value update\nDivider /128\nDivider /16\nDivider /256\nDivider /256\nDivider /32\nDivider /4\nDivider /64\nDivider /8\nEnable access to PR, RLR and WINR registers (0x5555)\nReset the watchdog value (0xAAAA)\nStart the watchdog (0xCCCC)\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nManagement data input/output slave\nMDIOS clear flag register\nMDIOS configuration register\nMDIOS clear read flag register\nMDIOS clear write flag register\nMDIOS input data register %s\nMDIOS output data register %s\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nMDIOS read flag register\nMDIOS status register\nMDIOS write flag register\nMDIOS clear flag register\nMDIOS configuration register\nMDIOS clear read flag register\nMDIOS clear write flag register\nMDIOS input data register %s\nMDIOS output data register %s\nMDIOS read flag register\nMDIOS status register\nMDIOS write flag register\nClear the preamble error flag\nClear the read flag\nClear the start error flag\nClear the turnaround error flag\nClear the write flag\nInput data received from MDIO Master during write frames\nOutput data sent to MDIO Master during read frames\nDisable Preamble Check\nError interrupt enable\nPeripheral enable\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nPreamble error flag\nSlaves’s address\nRead flags for MDIO registers 0 to 31\nRegister Read Interrupt Enable\nStart error flag\nClear the preamble error flag\nClear the read flag\nClear the start error flag\nClear the turnaround error flag\nClear the write flag\nInput data received from MDIO Master during write frames\nOutput data sent to MDIO Master during read frames\nDisable Preamble Check\nError interrupt enable\nPeripheral enable\nPreamble error flag\nSlaves’s address\nRead flags for MDIO registers 0 to 31\nRegister Read Interrupt Enable\nStart error flag\nTurnaround error flag\nWrite flags for MDIO registers 0 to 31\nRegister write interrupt enable\nTurnaround error flag\nWrite flags for MDIO registers 0 to 31\nRegister write interrupt enable\nOctoSPI\nalternate bytes register\naddress register\ncommunication configuration register\ncontrol register\ndevice configuration register 1\ndevice configuration register 2\ndevice configuration register 3\ndevice configuration register 4\ndata length register\ndata register\nflag clear register\nReturns the argument unchanged.\nOCTOSPI HyperBus latency configuration register\nCalls <code>U::from(self)</code>.\ninstruction register\nlow-power timeout register\npolling interval register\npolling status match register\npolling status mask register\nstatus register\ntiming configuration register\nwrite alternate bytes register\nwrite communication configuration register\nwrite instruction register\nwrap alternate bytes register\nwrap communication configuration register\nwrap instruction register\nwrap timing configuration register\nwrite timing configuration register\nalternate bytes register\naddress register\ncommunication configuration register\ncontrol register\ndevice configuration register 1\ndevice configuration register 2\ndevice configuration register 3\ndevice configuration register 4\ndata length register\ndata register\nflag clear register\nOCTOSPI HyperBus latency configuration register\ninstruction register\nlow-power timeout register\npolling interval register\npolling status match register\npolling status mask register\nstatus register\ntiming configuration register\nwrite alternate bytes register\nOCTOSPI write communication configuration register\nwrite instruction register\nwrap alternate bytes register\nOCTOSPI wrap communication configuration register\nwrap instruction register\nwrap timing configuration register\nwrite timing configuration register\nAlternate bytes double transfer rate. This bit sets the …\nAlternate bytes double transfer rate. This bit sets the …\nAlternate bytes double transfer rate. This bit sets the …\nAlternate-byte mode. This field defines the alternate-byte …\nAlternate-byte mode. This field defines the alternate-byte …\nAlternate-byte mode. This field defines the alternate byte …\nAbort request. This bit aborts the ongoing command …\nAlternate bytes size. This bit defines alternate bytes …\nAlternate bytes size. This field defines alternate bytes …\nAlternate bytes size. This bit defines alternate bytes …\nAddress to be sent to the external device. In HyperBus …\nAddress double transfer rate. This bit sets the DTR mode …\nAddress double transfer rate. This bit sets the DTR mode …\nAddress double transfer rate. This bit sets the DTR mode …\nAddress mode. This field defines the address phase mode of …\nAddress mode. This field defines the address phase mode of …\nAddress mode. This field defines the address phase mode of …\nAddress size. This field defines address size.\nAddress size. This field defines address size.\nAddress size. This field defines address size.\nAlternate bytes\n31: 0]: Alternate bytes. Optional data to be sent to the …\n31: 0]: Alternate bytes Optional data to be sent to the …\nAutomatic status-polling mode stop. This bit determines if …\nBusy. This bit is set when an operation is ongoing. It is …\nMode 0/Mode 3 This bit indicates the level taken by the …\nNCS boundary. This field enables the transaction boundary …\nChip-select high time CSHT + 1 defines the minimum number …\nClear status match flag Writing 1 clears the SMF flag in …\nClear transfer complete flag Writing 1 clears the TCF flag …\nClear transfer error flag Writing 1 clears the TEF flag in …\nClear timeout flag Writing 1 clears the TOF flag in the SR …\n31: 0]: Data Data to be sent/received to/from the external …\nNumber of dummy cycles. This field defines the duration of …\nNumber of dummy cycles. This field defines the duration of …\nNumber of dummy cycles. This field defines the duration of …\nData double transfer rate. This bit sets the DTR mode for …\ndata double transfer rate. This bit sets the DTR mode for …\nData double transfer rate. This bit sets the DTR mode for …\nDevice size. This field defines the size of the external …\nDelay hold quarter cycle\nDelay hold quarter cycle. Add a quarter cycle delay on the …\n31: 0]: Data length Number of data to be retrieved …\nDelay block bypass\nDMA enable In Indirect mode, the DMA can be used to input …\nDual-memory configuration. This bit activates the …\nData mode. This field defines the data phase mode of …\nData mode. This field defines the data phase mode of …\nData mode. This field defines the data phase mode of …\nDQS enable. This bit enables the data strobe management.\nDQS enable. This bit enables the data strobe management.\nDQS enable. This bit enables the data strobe management.\nEnable This bit enables the OCTOSPI. Note: The DMA request …\nFIFO level. This field gives the number of valid bytes …\nFunctional mode. This field defines the OCTOSPI functional …\nFree running clock. This bit configures the free running …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nFlash select. This bit selects the Flash memory to be …\nFIFO threshold flag In Indirect mode, this bit is set when …\nFIFO threshold level. This field defines, in Indirect …\nFIFO threshold interrupt enable. This bit enables the FIFO …\nInstruction double transfer rate. This bit sets the DTR …\nInstruction double transfer rate. This bit sets the DTR …\nInstruction double transfer rate. This bit sets the DTR …\nInstruction mode. This field defines the instruction phase …\nInstruction mode. This field defines the instruction phase …\nInstruction mode. This field defines the instruction phase …\nInstruction to be sent to the external SPI device\nInstruction Instruction to be sent to the external SPI …\n31: 0]: Instruction Instruction to be sent to the external …\n15: 0]: Polling interval Number of CLK cycle between a …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nInstruction size. This bit defines instruction size.\nInstruction size. This bit defines instruction size:\nInstruction size. This field defines instruction size.\nLatency mode. This bit selects the Latency mode.\nStatus mask Mask to be applied to the status bytes …\n31: 0]: Status match Value to be compared with the masked …\nMaximum transfer\nMemory type. This bit indicates the type of memory to be …\nPolling match mode. This bit indicates which method must …\nClock prescaler. This field defines the scaler factor for …\nRefresh rate. This field enables the refresh rate feature. …\nAlternate bytes double transfer rate. This bit sets the …\nAlternate bytes double transfer rate. This bit sets the …\nAlternate bytes double transfer rate. This bit sets the …\nAlternate-byte mode. This field defines the alternate-byte …\nAlternate-byte mode. This field defines the alternate-byte …\nAlternate-byte mode. This field defines the alternate byte …\nAbort request. This bit aborts the ongoing command …\nAlternate bytes size. This bit defines alternate bytes …\nAlternate bytes size. This field defines alternate bytes …\nAlternate bytes size. This bit defines alternate bytes …\nAddress to be sent to the external device. In HyperBus …\nAddress double transfer rate. This bit sets the DTR mode …\nAddress double transfer rate. This bit sets the DTR mode …\nAddress double transfer rate. This bit sets the DTR mode …\nAddress mode. This field defines the address phase mode of …\nAddress mode. This field defines the address phase mode of …\nAddress mode. This field defines the address phase mode of …\nAddress size. This field defines address size.\nAddress size. This field defines address size.\nAddress size. This field defines address size.\nAlternate bytes\n31: 0]: Alternate bytes. Optional data to be sent to the …\n31: 0]: Alternate bytes Optional data to be sent to the …\nAutomatic status-polling mode stop. This bit determines if …\nBusy. This bit is set when an operation is ongoing. It is …\nMode 0/Mode 3 This bit indicates the level taken by the …\nNCS boundary. This field enables the transaction boundary …\nChip-select high time CSHT + 1 defines the minimum number …\nClear status match flag Writing 1 clears the SMF flag in …\nClear transfer complete flag Writing 1 clears the TCF flag …\nClear transfer error flag Writing 1 clears the TEF flag in …\nClear timeout flag Writing 1 clears the TOF flag in the SR …\n31: 0]: Data Data to be sent/received to/from the external …\nNumber of dummy cycles. This field defines the duration of …\nNumber of dummy cycles. This field defines the duration of …\nNumber of dummy cycles. This field defines the duration of …\nData double transfer rate. This bit sets the DTR mode for …\ndata double transfer rate. This bit sets the DTR mode for …\nData double transfer rate. This bit sets the DTR mode for …\nDevice size. This field defines the size of the external …\nDelay hold quarter cycle\nDelay hold quarter cycle. Add a quarter cycle delay on the …\n31: 0]: Data length Number of data to be retrieved …\nDelay block bypass\nDMA enable In Indirect mode, the DMA can be used to input …\nDual-memory configuration. This bit activates the …\nData mode. This field defines the data phase mode of …\nData mode. This field defines the data phase mode of …\nData mode. This field defines the data phase mode of …\nDQS enable. This bit enables the data strobe management.\nDQS enable. This bit enables the data strobe management.\nDQS enable. This bit enables the data strobe management.\nEnable This bit enables the OCTOSPI. Note: The DMA request …\nFIFO level. This field gives the number of valid bytes …\nFunctional mode. This field defines the OCTOSPI functional …\nFree running clock. This bit configures the free running …\nFlash select. This bit selects the Flash memory to be …\nFIFO threshold flag In Indirect mode, this bit is set when …\nFIFO threshold level. This field defines, in Indirect …\nFIFO threshold interrupt enable. This bit enables the FIFO …\nInstruction double transfer rate. This bit sets the DTR …\nInstruction double transfer rate. This bit sets the DTR …\nInstruction double transfer rate. This bit sets the DTR …\nInstruction mode. This field defines the instruction phase …\nInstruction mode. This field defines the instruction phase …\nInstruction mode. This field defines the instruction phase …\nInstruction to be sent to the external SPI device\nInstruction Instruction to be sent to the external SPI …\n31: 0]: Instruction Instruction to be sent to the external …\n15: 0]: Polling interval Number of CLK cycle between a …\nInstruction size. This bit defines instruction size.\nInstruction size. This bit defines instruction size:\nInstruction size. This field defines instruction size.\nLatency mode. This bit selects the Latency mode.\nStatus mask Mask to be applied to the status bytes …\n31: 0]: Status match Value to be compared with the masked …\nMaximum transfer\nMemory type. This bit indicates the type of memory to be …\nPolling match mode. This bit indicates which method must …\nClock prescaler. This field defines the scaler factor for …\nRefresh rate. This field enables the refresh rate feature. …\nSend instruction only once mode. This bit has no effect …\nStatus match flag. This bit is set in Automatic …\nStatus match interrupt enable. This bit enables the status …\nSample shift By default, the OCTOSPI samples data 1/2 of a …\nSample shift By default, the OCTOSPI samples data 1/2 of a …\n7: 0]: Access time. Device access time expressed in number …\nTimeout counter enable. This bit is valid only when the …\nTransfer complete flag. This bit is set in Indirect mode …\nTransfer complete interrupt enable. This bit enables the …\nTransfer error flag. This bit is set in Indirect mode when …\nTransfer error interrupt enable. This bit enables the …\n15: 0]: Timeout period After each access in Memory-mapped …\nTimeout flag. This bit is set when timeout occurs. It is …\nTimeout interrupt enable. This bit enables the timeout …\nRead write recovery time Device read write recovery time …\nWrap size. This field indicates the wrap size to which the …\nWrite zero latency. This bit enables zero latency on write …\nSend instruction only once mode. This bit has no effect …\nStatus match flag. This bit is set in Automatic …\nStatus match interrupt enable. This bit enables the status …\nSample shift By default, the OCTOSPI samples data 1/2 of a …\nSample shift By default, the OCTOSPI samples data 1/2 of a …\n7: 0]: Access time. Device access time expressed in number …\nTimeout counter enable. This bit is valid only when the …\nTransfer complete flag. This bit is set in Indirect mode …\nTransfer complete interrupt enable. This bit enables the …\nTransfer error flag. This bit is set in Indirect mode when …\nTransfer error interrupt enable. This bit enables the …\n15: 0]: Timeout period After each access in Memory-mapped …\nTimeout flag. This bit is set when timeout occurs. It is …\nTimeout interrupt enable. This bit enables the timeout …\nRead write recovery time Device read write recovery time …\nWrap size. This field indicates the wrap size to which the …\nWrite zero latency. This bit enables zero latency on write …\nAutomatic status-polling mode\nStandard mode\nAlternate bytes on eight lines\nFixed latency\nFLASH 1 selected (data exchanged over IO[3:0])\nFLASH 2 selected (data exchanged over IO[7:4])\nAlternate bytes on four lines\n1/2 cycle shift\nHyperBus memory mode, the protocol follows the HyperBus …\nHyperBus register mode, addressing register space. The …\nIndirect-read mode\nIndirect-write mode\nMacronix mode, D1/D0 ordering in DTR 8-data-bit mode. …\nMacronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. …\nAND-match mode, SMF is set if all the unmasked bits …\nOR-match mode, SMF is set if any of the unmasked bits …\nMemory-mapped mode\nMicron mode, D0/D1 ordering in DTR 8-data-bit mode. …\nFTF is set if there are one or more free bytes available …\nFTF is set if there are 32 free bytes available to be …\nFTF is set if there are two or more free bytes available …\nNo alternate bytes\nNo shift\nAlternate bytes on a single line\nAlternate bytes on two lines\nVariable initial latency\n16-bit alternate bytes\n24-bit alternate bytes\n32-bit alternate bytes\n8-bit alternate bytes\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nOctoSPI IO Manager\ncontrol register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nOctoSPI IO Manager Port 1 Configuration Register\nOctoSPI IO Manager Port 2 Configuration Register\ncontrol register\nOctoSPI IO Manager Port 1 Configuration Register\nOctoSPI IO Manager Port 2 Configuration Register\nCLK/CLK Enable for Port\nCLK/CLK Enable for Port\nCLK/CLK Source for Port\nCLK/CLK Source for Port\nDQS Enable for Port\nDQS Enable for Port\nDQS Source for Port\nDQS Source for Port\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nEnable for Port n\nEnable for Port n\nSource for Port\nSource for Port\nEnable for Port\nEnable for Port\nSource for Port\nSource for Port\nMultiplexed mode enable\nCS Enable for Port\nCS Enable for Port\nCS Source for Port\nCS Source for Port\nREQ to ACK time\nCLK/CLK Enable for Port\nCLK/CLK Enable for Port\nCLK/CLK Source for Port\nCLK/CLK Source for Port\nDQS Enable for Port\nDQS Enable for Port\nDQS Source for Port\nDQS Source for Port\nEnable for Port n\nEnable for Port n\nSource for Port\nSource for Port\nEnable for Port\nEnable for Port\nSource for Port\nSource for Port\nMultiplexed mode enable\nCS Enable for Port\nCS Enable for Port\nCS Source for Port\nCS Source for Port\nREQ to ACK time\nUSB on the go\nCore ID register\nDevice all endpoints interrupt register\nAll endpoints interrupt mask register\nDevice configuration register\nDevice control register\nDevice IN endpoint control register\nDevice IN endpoint FIFO empty interrupt mask register\nDevice IN endpoint interrupt register\nDevice IN endpoint common interrupt mask register\nDevice IN endpoint transfer size register\nDevice IN endpoint transmit FIFO size register\nEndpoint 0 transmit FIFO size register (device mode)\nDevice OUT endpoint control register\nDevice OUT endpoint interrupt register\nDevice OUT endpoint common interrupt mask register\nDevice OUT endpoint transfer size register\nDevice status register\nDevice IN endpoint transmit FIFO status register\nDevice VBUS discharge time register\nDevice VBUS pulsing time register\nDevice endpoint / host channel FIFO register\nReturns the argument unchanged.\nAHB configuration register\nGeneral core configuration register, for core_id …\nGeneral core configuration register, for core_id 0x0000_[23…\nOTG I2C access register\nInterrupt mask register\nCore interrupt register\nOTG core LPM configuration register\nControl and status register\nInterrupt register\nReset register\nReceive FIFO size register\nStatus read and pop register\nReceive status debug read register\nUSB configuration register\nHost all channels interrupt register\nHost all channels interrupt mask register\nHost channel characteristics register\nHost configuration register\nHost channel interrupt register\nHost channel mask register\nHost channel split control register\nHost channel transfer size register\nHost frame interval register\nHost frame number/frame time remaining register\nNon-periodic transmit FIFO size register (host mode)\nNon-periodic transmit FIFO/queue status register (host …\nHost port control and status register\nHost periodic transmit FIFO size register\nPeriodic transmit FIFO/queue status register\nCalls <code>U::from(self)</code>.\nPower and clock gating control register\nCore ID register\nDevice all endpoints interrupt register\nAll endpoints interrupt mask register\nDevice configuration register\nDevice control register\nDevice endpoint control register\nDevice IN endpoint FIFO empty interrupt mask register\nDevice endpoint interrupt register\nDevice IN endpoint common interrupt mask register\nDevice endpoint transfer size register\nDevice endpoint control register\nDevice endpoint interrupt register\nDevice OUT endpoint common interrupt mask register\nDevice OUT endpoint transfer size register\nDevice status register\nDevice IN endpoint transmit FIFO status register\nDevice VBUS discharge time register\nDevice VBUS pulsing time register\nFIFO register\nFIFO size register\nAHB configuration register\nGeneral core configuration register\nGeneral core configuration register\nI2C access register\nInterrupt mask register\nCore interrupt register\nCore LPM configuration register\nControl and status register\nInterrupt register\nReset register\nReceive FIFO size register\nStatus read and pop register\nUSB configuration register\nHost all channels interrupt register\nHost all channels interrupt mask register\nHost channel characteristics register\nHost configuration register\nHost channel interrupt register\nHost channel mask register\nHost channel transfer size register\nHost frame interval register\nHost frame number/frame time remaining register\nNon-periodic transmit FIFO/queue status register\nHost port control and status register\nPeriodic transmit FIFO/queue status register\nPower and clock gating control register\nI2C ACK\nACK response received/transmitted interrupt\nACK response received/transmitted interrupt mask\nI2C Address\nA-device timeout change\nAHB master idle\nA-session valid\nA-peripheral session valid override enable\nA-peripheral session valid override value\nB2BSTUP\nBabble error\nBabble error mask\nBattery charging detector (BCD) enable\nByte count\nBest effort service latency\nBESL threshold\nB-session valid\nI2C Busy/Done\nB-peripheral session valid override enable\nB-peripheral session valid override value\nClear global IN NAK\nClear global OUT NAK\nChannel disable\nChannel enable\nChannel halted\nChannel halted mask\nConnector ID status change\nConnector ID status change mask\nConnector ID status\nCurrent mode of operation\nCNAK\nCNAK\nCore soft reset\nCorrupt Tx packet\nDevice address\nDevice address\nData\nData fetch suspended\nDebounce done\nLong/short debounce time\nData contact detection (DCD) mode enable\nData contact detection (DCD) status\nDevice HNP enabled\nDisconnect detected interrupt mask\nDisconnect detected interrupt\nDMA enable\nDMA request signal enabled for USB OTG HS\nData PID\nData PID\nDevice speed\nData toggle error\nData toggle error mask\nDevice VBUS pulsing time\nErratic error\nEmbedded host enable\nEnable best effort service latency\nEnumeration done\nEnumeration done mask\nEnumerated speed\nEONUM/DPID\nEONUM/DPID\nEnd of periodic frame interrupt\nEnd of periodic frame interrupt mask\nEndpoint direction\nEPDIS\nEPDIS\nEPDISD\nEPDISD\nEndpoint disabled interrupt mask\nEndpoint disabled interrupt mask\nEPENA\nEPENA\nEndpoint mismatch interrupt mask\nEndpoint number (device mode) / Channel number (host mode)\nEndpoint number\nEPTYP\nEPTYP\nEndpoint type\nEarly suspend\nEarly suspend mask\nHost frame counter reset\nFIFO depth\nForce device mode\nForce host mode\nFrame number of the received SOF\nFrame interval\nFrame number (device mode)\nFrame overrun\nFrame overrun mask\nFrame number\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nFS/LS PHY clock select\nFS- and LS-only support\nData fetch suspended mask\nFrame time remaining\nGate HCLK\nGlobal IN non-periodic NAK effective\nGlobal non-periodic IN NAK effective mask\nGlobal IN NAK status\nGlobal interrupt mask\nGlobal OUT NAK effective mask\nGlobal OUT NAK status\nGlobal OUT NAK effective\nChannel interrupts\nChannel interrupt mask\nBurst length/type\nHost channels interrupt mask\nHost channels interrupt\nHost negotiation detected\nHost negotiation success\nHNP-capable\nHNP request\nHost negotiation success status change\nHost port interrupt\nHost set HNP enable\nHCLK soft reset\nI2C DatSe0 USB mode\nI2C Device Address\nI2C Enable\nID input pin changed\nIN endpoint interrupt bits\nIN endpoints interrupt mask\nIN endpoint interrupt\nIN EP interrupt mask bits\nIncomplete isochronous IN transfer\nIncomplete isochronous IN transfer mask\nINEPNE\nIN endpoint NAK effective mask\nIN token received with EP mismatch mask\nIN endpoint TxFIFO space available\nIN EP Tx FIFO empty interrupt mask bits\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nIncomplete periodic transfer (host mode) / Incomplete …\nIncomplete periodic transfer mask (host mode) / Incomplete …\nIsochronous OUT packet dropped interrupt\nIsochronous OUT packet dropped interrupt mask\nITTXFE\nIN token received when TxFIFO empty mask\nL1 deep sleep enable\nSleep State Resume OK\nL1 Shallow Sleep enable\nLPM token acknowledge enable\nLPM Channel Index\nLPM support enable\nLPM interrupt mask\nLPM retry count\nLPM retry count status\nLPM response\nLow-speed device\nMulti count\nMulticount\nMode mismatch interrupt\nMode mismatch interrupt mask\nMPSIZ\nMPSIZ\nMaximum packet size\nNAK response received interrupt\nNAK response received interrupt mask\nNAKSTS\nNAKSTS\nVBUS sensing disable\nNon-periodic transmit request queue space available\nNon-periodic TxFIFO empty\nNon-periodic TxFIFO empty mask\nNon-periodic TxFIFO space available\nTop of the non-periodic transmit request queue\nResponse received interrupt mask\nNon-zero-length status OUT handshake\nOdd frame\nOUT endpoint interrupt bits\nOUT endpoints interrupt mask\nOUT endpoint interrupt\nOUT EP interrupt mask bits\nOTEPDIS\nOUT token received when endpoint disabled mask\nOTG interrupt mask\nOTG interrupt\nIndicator complement\nPort connect detected\nPort connect status\nPrimary detection (PD) mode enable\nPrimary detection (PD) status\nPort enable\nPort enable/disable change\nPeriodic frame interval\nInternal high-speed PHY enable.\nPHY Low-power clock select\nFull-speed internal serial transceiver enable\nPHY Suspended\nPacket count\nPacket count\nPacket count\nPacket status (device mode)\nPacket status (host mode)\nPort line status\nPort overcurrent active\nPort overcurrent change\nPower-on programming done\nPort power\nPort resume\nProduct ID field\nPort reset\nHost port interrupt mask\nDM pull-up detection status\nPort speed\nPort suspend\nIndicator pass through\nPort test control\nPeriodic TxFIFO empty\nPeriodic TxFIFO empty level\nPeriodic TxFIFO empty mask\nPeriodic transmit data FIFO space available\nPeriodic transmit request queue space available\nTop of the periodic transmit request queue\nPower down\nPower down\nI2C Register Address\nbRemoteWake value\nReset detected interrupt mask\nRead/Write Indicator\nI2C Read/Write Data\nRemote wakeup signaling\nReceived data PID/SETUP packet count\nRxFIFO depth\nRxFIFO flush\nRxFIFO non-empty\nReceive FIFO non-empty mask\nRAM start address\nSD0PID/SEVNFRM\nSD0PID/SEVNFRM\nSecondary detection (SD) mode enable\nSecondary detection (SD) status\nSoft disconnect\nSession end detected\nI2C ACK\nACK response received/transmitted interrupt\nACK response received/transmitted interrupt mask\nI2C Address\nA-device timeout change\nAHB master idle\nA-session valid\nA-peripheral session valid override enable\nA-peripheral session valid override value\nB2BSTUP\nBabble error\nBabble error mask\nBattery charging detector (BCD) enable\nByte count\nBest effort service latency\nBESL threshold\nB-session valid\nI2C Busy/Done\nB-peripheral session valid override enable\nB-peripheral session valid override value\nClear global IN NAK\nClear global OUT NAK\nChannel disable\nChannel enable\nChannel halted\nChannel halted mask\nConnector ID status change\nConnector ID status change mask\nConnector ID status\nCurrent mode of operation\nCNAK\nCNAK\nCore soft reset\nCorrupt Tx packet\nDevice address\nDevice address\nData\nData fetch suspended\nDebounce done\nLong/short debounce time\nData contact detection (DCD) mode enable\nData contact detection (DCD) status\nDevice HNP enabled\nDisconnect detected interrupt mask\nDisconnect detected interrupt\nDMA enable\nDMA request signal enabled for USB OTG HS\nData PID\nData PID\nDevice speed\nData toggle error\nData toggle error mask\nDevice VBUS pulsing time\nErratic error\nEmbedded host enable\nEnable best effort service latency\nEnumeration done\nEnumeration done mask\nEnumerated speed\nEONUM/DPID\nEONUM/DPID\nEnd of periodic frame interrupt\nEnd of periodic frame interrupt mask\nEndpoint direction\nEPDIS\nEPDIS\nEPDISD\nEPDISD\nEndpoint disabled interrupt mask\nEndpoint disabled interrupt mask\nEPENA\nEPENA\nEndpoint mismatch interrupt mask\nEndpoint number (device mode) / Channel number (host mode)\nEndpoint number\nEPTYP\nEPTYP\nEndpoint type\nEarly suspend\nEarly suspend mask\nHost frame counter reset\nFIFO depth\nForce device mode\nForce host mode\nFrame number of the received SOF\nFrame interval\nFrame number (device mode)\nFrame overrun\nFrame overrun mask\nFrame number\nFS/LS PHY clock select\nFS- and LS-only support\nData fetch suspended mask\nFrame time remaining\nGate HCLK\nGlobal IN non-periodic NAK effective\nGlobal non-periodic IN NAK effective mask\nGlobal IN NAK status\nGlobal interrupt mask\nGlobal OUT NAK effective mask\nGlobal OUT NAK status\nGlobal OUT NAK effective\nChannel interrupts\nChannel interrupt mask\nBurst length/type\nHost channels interrupt mask\nHost channels interrupt\nHost negotiation detected\nHost negotiation success\nHNP-capable\nHNP request\nHost negotiation success status change\nHost port interrupt\nHost set HNP enable\nHCLK soft reset\nI2C DatSe0 USB mode\nI2C Device Address\nI2C Enable\nID input pin changed\nIN endpoint interrupt bits\nIN endpoints interrupt mask\nIN endpoint interrupt\nIN EP interrupt mask bits\nIncomplete isochronous IN transfer\nIncomplete isochronous IN transfer mask\nINEPNE\nIN endpoint NAK effective mask\nIN token received with EP mismatch mask\nIN endpoint TxFIFO space available\nIN EP Tx FIFO empty interrupt mask bits\nIncomplete periodic transfer (host mode) / Incomplete …\nIncomplete periodic transfer mask (host mode) / Incomplete …\nIsochronous OUT packet dropped interrupt\nIsochronous OUT packet dropped interrupt mask\nITTXFE\nIN token received when TxFIFO empty mask\nL1 deep sleep enable\nSleep State Resume OK\nL1 Shallow Sleep enable\nLPM token acknowledge enable\nLPM Channel Index\nLPM support enable\nLPM interrupt mask\nLPM retry count\nLPM retry count status\nLPM response\nLow-speed device\nMulti count\nMulticount\nMode mismatch interrupt\nMode mismatch interrupt mask\nMPSIZ\nMPSIZ\nMaximum packet size\nNAK response received interrupt\nNAK response received interrupt mask\nNAKSTS\nNAKSTS\nVBUS sensing disable\nNon-periodic transmit request queue space available\nNon-periodic TxFIFO empty\nNon-periodic TxFIFO empty mask\nNon-periodic TxFIFO space available\nTop of the non-periodic transmit request queue\nResponse received interrupt mask\nNon-zero-length status OUT handshake\nOdd frame\nOUT endpoint interrupt bits\nOUT endpoints interrupt mask\nOUT endpoint interrupt\nOUT EP interrupt mask bits\nOTEPDIS\nOUT token received when endpoint disabled mask\nOTG interrupt mask\nOTG interrupt\nIndicator complement\nPort connect detected\nPort connect status\nPrimary detection (PD) mode enable\nPrimary detection (PD) status\nPort enable\nPort enable/disable change\nPeriodic frame interval\nInternal high-speed PHY enable.\nPHY Low-power clock select\nFull-speed internal serial transceiver enable\nPHY Suspended\nPacket count\nPacket count\nPacket count\nPacket status (device mode)\nPacket status (host mode)\nPort line status\nPort overcurrent active\nPort overcurrent change\nPower-on programming done\nPort power\nPort resume\nProduct ID field\nPort reset\nHost port interrupt mask\nDM pull-up detection status\nPort speed\nPort suspend\nIndicator pass through\nPort test control\nPeriodic TxFIFO empty\nPeriodic TxFIFO empty level\nPeriodic TxFIFO empty mask\nPeriodic transmit data FIFO space available\nPeriodic transmit request queue space available\nTop of the periodic transmit request queue\nPower down\nPower down\nI2C Register Address\nbRemoteWake value\nReset detected interrupt mask\nRead/Write Indicator\nI2C Read/Write Data\nRemote wakeup signaling\nReceived data PID/SETUP packet count\nRxFIFO depth\nRxFIFO flush\nRxFIFO non-empty\nReceive FIFO non-empty mask\nRAM start address\nSD0PID/SEVNFRM\nSD0PID/SEVNFRM\nSecondary detection (SD) mode enable\nSecondary detection (SD) status\nSoft disconnect\nSession end detected\nSet global IN NAK\nSet global OUT NAK\nPort sleep status\nSNAK\nSNAK\nSend LPM transaction\nSNPM\nSNPM\nSODDFRM\nSODDFRM/SD1PID\nStart of frame\nStart of frame mask\nSOF output enable\nSRP-capable\nSession request\nSession request/new session detected interrupt mask\nSession request/new session detected interrupt\nSession request success\nSession request success status change\nSTALL\nSTALL\nSTALL response received interrupt\nSTALL response received interrupt mask\nStop PHY clock\nSTUP\nSETUP phase done mask\nSuspend status\nTest control\nTOC\nFS timeout calibration\nTimeout condition mask (Non-isochronous endpoints)\nUSB turnaround time\nTermSel DLine pulsing selection\nTransaction error\nTransaction error mask\nTXFE\nTxFIFO empty level\nTxFIFO flush\nTXFNUM\nTxFIFO number\nULPI Auto-resume\nULPI Clock SuspendM\nULPI External VBUS Drive\nULPI external VBUS indicator\nULPI FS/LS select\nULPI interface protect disable\nUSBAEP\nUSBAEP\nUSB reset mask\nUSB reset\nUSB suspend\nUSB suspend mask\nUSB VBUS detection enable\nEnable the VBUS “A” sensing device\nEnable the VBUS “B” sensing device\nDevice VBUS discharge time\nVBUS valid override enable\nVBUS valid override value\nResume/remote wakeup detected interrupt\nResume/remote wakeup detected interrupt mask\nTransceiver delay\nXFRC\nXFRC\nTransfer completed\nTransfer completed interrupt mask\nTransfer completed interrupt mask\nTransfer completed mask\nTransfer size\nTransfer size\nTransfer size\nSet global IN NAK\nSet global OUT NAK\nPort sleep status\nSNAK\nSNAK\nSend LPM transaction\nSNPM\nSNPM\nSODDFRM\nSODDFRM/SD1PID\nStart of frame\nStart of frame mask\nSOF output enable\nSRP-capable\nSession request\nSession request/new session detected interrupt mask\nSession request/new session detected interrupt\nSession request success\nSession request success status change\nSTALL\nSTALL\nSTALL response received interrupt\nSTALL response received interrupt mask\nStop PHY clock\nSTUP\nSETUP phase done mask\nSuspend status\nTest control\nTOC\nFS timeout calibration\nTimeout condition mask (Non-isochronous endpoints)\nUSB turnaround time\nTermSel DLine pulsing selection\nTransaction error\nTransaction error mask\nTXFE\nTxFIFO empty level\nTxFIFO flush\nTXFNUM\nTxFIFO number\nULPI Auto-resume\nULPI Clock SuspendM\nULPI External VBUS Drive\nULPI external VBUS indicator\nULPI FS/LS select\nULPI interface protect disable\nUSBAEP\nUSBAEP\nUSB reset mask\nUSB reset\nUSB suspend\nUSB suspend mask\nUSB VBUS detection enable\nEnable the VBUS “A” sensing device\nEnable the VBUS “B” sensing device\nDevice VBUS discharge time\nVBUS valid override enable\nVBUS valid override value\nResume/remote wakeup detected interrupt\nResume/remote wakeup detected interrupt mask\nTransceiver delay\nXFRC\nXFRC\nTransfer completed\nTransfer completed interrupt mask\nTransfer completed interrupt mask\nTransfer completed mask\nTransfer size\nTransfer size\nTransfer size\nChannel halted (triggers an interrupt)\nData toggle error (triggers an interrupt)\n80% of the frame interval\n85% of the frame interval\n90% of the frame interval\n95% of the frame interval\nFull speed using external ULPI PHY\nFull speed using internal embedded PHY\nHigh speed\nIN transfer completed (triggers an interrupt)\nIN data packet received\nOUT transfer completed (triggers an interrupt)\nOUT data packet received\nGlobal OUT NAK (triggers an interrupt)\nSETUP transaction completed (triggers an interrupt)\nSETUP data packet received\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nPWR\nThis register allows controlling CPU1 power.\nPWR control register 1\nThis register is not reset by wakeup from Standby mode, …\nReset only by POR only, not reset by wakeup from Standby …\nPWR control status register 1\nThis register allows controlling D3 domain power.Following …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nreset only by system reset, not reset by wakeup from …\nReset only by system reset, not reset by wakeup from …\nreset only by system reset, not reset by wakeup from …\nThis register allows controlling CPU1 power.\nPWR control register 1\nThis register is not reset by wakeup from Standby mode, …\nReset only by POR only, not reset by wakeup from Standby …\nPWR control status register 1\nThis register allows controlling D3 domain power.Following …\nreset only by system reset, not reset by wakeup from …\nReset only by system reset, not reset by wakeup from …\nreset only by system reset, not reset by wakeup from …\nVOS currently applied for VCORE voltage scaling selection. …\nVoltage levels ready bit for currently used VOS and …\nAnalog voltage detector level selection These bits select …\nPeripheral voltage monitor on VDDA enable\nAnalog voltage detector output on VDDA This bit is set and …\nBackup regulator enable When set, the Backup regulator …\nBackup regulator ready This bit is set by hardware to …\nPower management unit bypass\nClear D1 domain CPU1 Standby, Stop and HOLD flags (always …\nDisable backup domain write protection In reset state, the …\nFlash low-power mode in DStop mode This bit allows to …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nLow drop-out regulator enable\nLow-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use …\nVBAT and temperature monitoring enable When set, the VBAT …\nD1 domain Power Down Deepsleep selection. This bit allows …\nD2 domain Power Down Deepsleep. This bit allows CPU1 to …\nSystem D3 domain Power Down Deepsleep. This bit allows …\nProgrammable voltage detector level selection These bits …\nProgrammable voltage detector enable\nProgrammable voltage detect output This bit is set and …\nKeep system D3 domain in Run mode regardless of the CPU …\nSystem Standby flag This bit is set by hardware and …\nD1 domain DStandby flag This bit is set by hardware and …\nD2 domain DStandby flag This bit is set by hardware and …\nSD converter Enable\nStep-down converter forced ON and in High Power MR mode\nSMPS step-down converter external supply ready\nStep-down converter voltage output level selection\nVOS currently applied for VCORE voltage scaling selection. …\nVoltage levels ready bit for currently used VOS and …\nAnalog voltage detector level selection These bits select …\nPeripheral voltage monitor on VDDA enable\nAnalog voltage detector output on VDDA This bit is set and …\nBackup regulator enable When set, the Backup regulator …\nBackup regulator ready This bit is set by hardware to …\nPower management unit bypass\nClear D1 domain CPU1 Standby, Stop and HOLD flags (always …\nDisable backup domain write protection In reset state, the …\nFlash low-power mode in DStop mode This bit allows to …\nLow drop-out regulator enable\nLow-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use …\nVBAT and temperature monitoring enable When set, the VBAT …\nD1 domain Power Down Deepsleep selection. This bit allows …\nD2 domain Power Down Deepsleep. This bit allows CPU1 to …\nSystem D3 domain Power Down Deepsleep. This bit allows …\nProgrammable voltage detector level selection These bits …\nProgrammable voltage detector enable\nProgrammable voltage detect output This bit is set and …\nKeep system D3 domain in Run mode regardless of the CPU …\nSystem Standby flag This bit is set by hardware and …\nD1 domain DStandby flag This bit is set by hardware and …\nD2 domain DStandby flag This bit is set by hardware and …\nSD converter Enable\nStep-down converter forced ON and in High Power MR mode\nSMPS step-down converter external supply ready\nStep-down converter voltage output level selection\nSTOP flag This bit is set by hardware and cleared only by …\nSystem Stop mode voltage scaling selection These bits …\nTemperature level monitoring versus high threshold\nTemperature level monitoring versus low threshold\nVDD33USB voltage level detector enable.\nUSB supply ready.\nUSB regulator enable.\nVBAT level monitoring versus high threshold\nVBAT level monitoring versus low threshold\nVBAT charging enable\nVBAT charging resistor selection\nVoltage scaling selection according to performance These …\nVOS Ready bit for VCORE voltage scaling output selection. …\nClear Wakeup pin flag for WKUP. These bits are always read …\nEnable Wakeup Pin WKUPn+1 Each bit is set and cleared by …\nWakeup pin WKUPF flag. This bit is set by hardware and …\nWakeup pin polarity bit for WKUPn-7 These bits define the …\nWakeup pin pull configuration\nSTOP flag This bit is set by hardware and cleared only by …\nSystem Stop mode voltage scaling selection These bits …\nTemperature level monitoring versus high threshold\nTemperature level monitoring versus low threshold\nVDD33USB voltage level detector enable.\nUSB supply ready.\nUSB regulator enable.\nVBAT level monitoring versus high threshold\nVBAT level monitoring versus low threshold\nVBAT charging enable\nVBAT charging resistor selection\nVoltage scaling selection according to performance These …\nVOS Ready bit for VCORE voltage scaling output selection. …\nClear Wakeup pin flag for WKUP. These bits are always read …\nEnable Wakeup Pin WKUPn+1 Each bit is set and cleared by …\nWakeup pin WKUPF flag. This bit is set by hardware and …\nWakeup pin polarity bit for WKUPn-7 These bits define the …\nWakeup pin pull configuration\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nReset and clock control\nRCC AHB1 Clock Register\nRCC AHB1 Sleep Clock Register\nRCC AHB1 Peripheral Reset Register\nRCC AHB2 Clock Register\nRCC AHB2 Sleep Clock Register\nRCC AHB2 Peripheral Reset Register\nRCC AHB3 Clock Register\nRCC AHB3 Sleep Clock Register\nRCC AHB3 Reset Register\nRCC AHB4 Clock Register\nRCC AHB4 Sleep Clock Register\nRCC AHB4 Peripheral Reset Register\nRCC APB1 Clock Register\nRCC APB1 High Sleep Clock Register\nRCC APB1 Peripheral Reset Register\nRCC APB1 Clock Register\nRCC APB1 Low Sleep Clock Register\nRCC APB1 Peripheral Reset Register\nRCC APB2 Clock Register\nRCC APB2 Sleep Clock Register\nRCC APB2 Peripheral Reset Register\nRCC APB3 Clock Register\nRCC APB3 Sleep Clock Register\nRCC APB3 Peripheral Reset Register\nRCC APB4 Clock Register\nRCC APB4 Sleep Clock Register\nRCC APB4 Peripheral Reset Register\nRCC Backup Domain Control Register\nRCC AHB1 Clock Register\nRCC AHB1 Sleep Clock Register\nRCC AHB2 Clock Register\nRCC AHB2 Sleep Clock Register\nRCC AHB3 Clock Register\nRCC AHB3 Sleep Clock Register\nRCC AHB4 Clock Register\nRCC AHB4 Sleep Clock Register\nRCC APB1 Clock Register\nRCC APB1 High Sleep Clock Register\nRCC APB1 Clock Register\nRCC APB1 Low Sleep Clock Register\nRCC APB2 Clock Register\nRCC APB2 Sleep Clock Register\nRCC APB3 Clock Register\nRCC APB3 Sleep Clock Register\nRCC APB4 Clock Register\nRCC APB4 Sleep Clock Register\nRCC Reset Status Register\nRCC Clock Configuration Register\nRCC Clock Source Interrupt Clear Register\nRCC Clock Source Interrupt Enable Register\nRCC Clock Source Interrupt Flag Register\nclock control register\nRCC Clock Recovery RC Register\nRCC CSI configuration register\nRCC Clock Control and Status Register\nRCC Domain 1 Kernel Clock Configuration Register\nRCC Domain 1 Clock Configuration Register\nRCC Domain 2 Kernel Clock Configuration Register\nRCC Domain 2 Kernel Clock Configuration Register\nRCC Domain 2 Clock Configuration Register\nRCC D3 Autonomous mode Register\nRCC Domain 3 Kernel Clock Configuration Register\nRCC Domain 3 Clock Configuration Register\nReturns the argument unchanged.\nGlobal Control Register\nRCC HSI configuration register\nRCC Internal Clock Source Calibration Register\nCalls <code>U::from(self)</code>.\nRCC PLLs Configuration Register\nRCC PLLs Clock Source Selection Register\nRCC PLL1 Dividers Configuration Register\nRCC PLL1 Fractional Divider Register\nRCC Reset Status Register\nRCC AHB1 Clock Register\nRCC AHB1 Sleep Clock Register\nRCC AHB1 Peripheral Reset Register\nRCC AHB2 Clock Register\nRCC AHB2 Sleep Clock Register\nRCC AHB2 Peripheral Reset Register\nRCC AHB3 Clock Register\nRCC AHB3 Sleep Clock Register\nRCC AHB3 Reset Register\nRCC AHB4 Clock Register\nRCC AHB4 Sleep Clock Register\nRCC AHB4 Peripheral Reset Register\nRCC APB1 Clock Register\nRCC APB1 High Sleep Clock Register\nRCC APB1 Peripheral Reset Register\nRCC APB1 Clock Register\nRCC APB1 Low Sleep Clock Register\nRCC APB1 Peripheral Reset Register\nRCC APB2 Clock Register\nRCC APB2 Sleep Clock Register\nRCC APB2 Peripheral Reset Register\nRCC APB3 Clock Register\nRCC APB3 Sleep Clock Register\nRCC APB3 Peripheral Reset Register\nRCC APB4 Clock Register\nRCC APB4 Sleep Clock Register\nRCC APB4 Peripheral Reset Register\nRCC Backup Domain Control Register\nRCC AHB1 Clock Register\nRCC AHB1 Sleep Clock Register\nRCC AHB2 Clock Register\nRCC AHB2 Sleep Clock Register\nRCC AHB3 Clock Register\nRCC AHB3 Sleep Clock Register\nRCC AHB4 Clock Register\nRCC AHB4 Sleep Clock Register\nRCC APB1 Clock Register\nRCC APB1 High Sleep Clock Register\nRCC APB1 Clock Register\nRCC APB1 Low Sleep Clock Register\nRCC APB2 Clock Register\nRCC APB2 Sleep Clock Register\nRCC APB3 Clock Register\nRCC APB3 Sleep Clock Register\nRCC APB4 Clock Register\nRCC APB4 Sleep Clock Register\nRCC Reset Status Register\nRCC Clock Configuration Register\nRCC Clock Source Interrupt Clear Register\nRCC Clock Source Interrupt Enable Register\nRCC Clock Source Interrupt Flag Register\nclock control register\nRCC Clock Recovery RC Register\nRCC CSI configuration register\nRCC Clock Control and Status Register\nRCC Domain 1 Kernel Clock Configuration Register\nRCC Domain 1 Clock Configuration Register\nRCC Domain 2 Kernel Clock Configuration Register\nRCC Domain 2 Kernel Clock Configuration Register\nRCC Domain 2 Clock Configuration Register\nRCC D3 Autonomous mode Register\nRCC Domain 3 Kernel Clock Configuration Register\nRCC Domain 3 Clock Configuration Register\nGlobal Control Register\nRCC HSI configuration register\nRCC Internal Clock Source Calibration Register\nRCC PLLs Configuration Register\nRCC PLLs Clock Source Selection Register\nRCC PLL1 Dividers Configuration Register\nRCC PLL Fractional Divider Register\nRCC Reset Status Register\nADC1/2 Peripheral Clocks Enable\nADC1/2 Peripheral Clocks Enable\nADC1/2 Peripheral Clocks Enable During CSleep Mode\nADC1/2 Peripheral Clocks Enable During CSleep Mode\nADC1&amp;2 block reset\nADC3 Autonomous mode enable\nADC3 Peripheral Clocks Enable\nADC3 Peripheral Clocks Enable\nADC3 Peripheral Clocks Enable During CSleep Mode\nADC3 Peripheral Clocks Enable During CSleep Mode\nADC3 block reset\nSAR ADC kernel clock source selection\nART Clock Enable\nART Clock Enable\nART Clock Enable During CSleep Mode\nART Clock Enable During CSleep Mode\nART block reset\nAXISRAM block enable\nAXISRAM Block Clock Enable During CSleep mode\nAXISRAM Block Clock Enable During CSleep mode\nBDMA and DMAMUX Autonomous mode enable\nBDMA and DMAMUX2 Clock Enable\nBDMA and DMAMUX2 Clock Enable\nBDMA Clock Enable During CSleep Mode\nBDMA Clock Enable During CSleep Mode\nBDMA block reset\nVSwitch domain software reset\nBackup RAM Autonomous mode enable\nBackup RAM Clock Enable\nBackup RAM Clock Enable\nBackup RAM Clock Enable During CSleep Mode\nBackup RAM Clock Enable During CSleep Mode\nForce allow CPU1 to boot\nForce allow CPU2 to boot\nBOR reset flag\nBOR reset flag\nHDMI-CEC peripheral clock enable\nHDMI-CEC peripheral clock enable\nHDMI-CEC Peripheral Clocks Enable During CSleep Mode\nHDMI-CEC Peripheral Clocks Enable During CSleep Mode\nHDMI-CEC block reset\nHDMI-CEC kernel clock source selection\nper_ck clock source selection\nCOMP12 Autonomous mode enable\nCOMP1/2 peripheral clock enable\nCOMP1/2 peripheral clock enable\nCOMP1/2 peripheral clock enable during CSleep mode\nCOMP1/2 peripheral clock enable during CSleep mode\nCOMP12 Blocks Reset\nCORDIC enable\nCORDIC enable during CSleep Mode\nCORDIC enable during CSleep Mode\nCORDIC reset\nCPU reset\nCPU reset flag\nCPU reset flag\nCRC Autonomous mode enable\nCRC peripheral clock enable\nCRC peripheral clock enable\nCRC peripheral clock enable during CSleep mode\nCRC peripheral clock enable during CSleep mode\nCRC block reset\nClock Recovery System peripheral clock enable\nClock Recovery System peripheral clock enable\nClock Recovery System peripheral clock enable during …\nClock Recovery System peripheral clock enable during …\nClock Recovery System reset\nCRYPT peripheral clock enable\nCRYPT peripheral clock enable\nCRYPT peripheral clock enable during CSleep mode\nCRYPT peripheral clock enable during CSleep mode\nCryptography block reset\nCSI clock calibration\nCSI clock calibration\nCSI clock enable in Stop mode\nCSI clock enable\nCSI ready Interrupt Flag\nCSI clock ready flag\nCSI ready Interrupt Enable\nCSI clock trimming\nCSI clock trimming\nD1 domain clocks ready flag\nD1 domain Core prescaler\nD1DTCM1 Block Clock Enable During CSleep mode\nD1DTCM1 Block Clock Enable During CSleep mode\nD1 domain APB3 prescaler\nD1 domain power switch reset flag\nD1 domain power switch reset flag\nD2 domain clocks ready flag\nD2 domain APB1 prescaler\nD2 domain APB2 prescaler\nD2 domain power switch reset flag\nD2 domain power switch reset flag\nD3 domain APB4 prescaler\nDAC1&amp;2 peripheral clock enable\nDAC1&amp;2 peripheral clock enable\nDAC1/2 peripheral clock enable during CSleep mode\nDAC1/2 peripheral clock enable during CSleep mode\nDAC1 and 2 Blocks Reset\nDAC2 (containing one converter) Autonomous mode enable\nDAC2 (containing one converter) peripheral clock enable\nDAC2 (containing one converter) peripheral clock enable …\nDAC2 (containing one converter) reset\nDCMI peripheral clock\nDCMI peripheral clock\nDCMI peripheral clock enable during csleep mode\nDCMI peripheral clock enable during csleep mode\nDCMI block reset\nDFSDM1 Peripheral Clocks Enable\nDFSDM1 Peripheral Clocks Enable\nDFSDM1 Peripheral Clocks Enable During CSleep Mode\nDFSDM1 Peripheral Clocks Enable During CSleep Mode\nDFSDM1 block reset\nDFSDM1 kernel Clk clock source selection\nDFSDM2 kernel clock source selection\nPrescaler for PLL1\nPLL1 DIVP divider output enable\nPLL1 DIVQ divider output enable\nPLL1 DIVR divider output enable\nDMA1 Clock Enable\nDMA1 Clock Enable\nDMA1 Clock Enable During CSleep Mode\nDMA1 Clock Enable During CSleep Mode\nDMA1 block reset\nDMA2D Peripheral Clock Enable\nDMA2D Peripheral Clock Enable\nDMA2D Clock Enable During CSleep Mode\nDMA2D Clock Enable During CSleep Mode\nDMA2D block reset\nDMA2 Clock Enable\nDMA2 Clock Enable\nDMA2 Clock Enable During CSleep Mode\nDMA2 Clock Enable During CSleep Mode\nDMA2 block reset\nDSI Peripheral clocks enable\nDSI Peripheral clocks enable\nDSI Peripheral Clock Enable During CSleep Mode\nDSI Peripheral Clock Enable During CSleep Mode\nDSI block reset\nkernel clock source selection\nD1 DTCM1 block enable\nD1 DTCM2 block enable\nD1 DTCM2 Block Clock Enable During CSleep mode\nD1 DTCM2 Block Clock Enable During CSleep mode\nDigital temperature sensor Autonomous mode enable\nDigital temperature sensor block enable\nDigital temperature sensor block enable during CSleep Mode\nDigital temperature sensor block enable during CSleep Mode\nDigital temperature sensor block reset\nEthernet MAC bus interface Clock Enable\nEthernet MAC bus interface Clock Enable\nEthernet MAC bus interface Clock Enable During CSleep Mode\nEthernet MAC bus interface Clock Enable During CSleep Mode\nETH1MAC block reset\nEthernet Reception Clock Enable\nEthernet Reception Clock Enable\nEthernet Reception Clock Enable During CSleep Mode\nEthernet Reception Clock Enable During CSleep Mode\nEthernet Transmission Clock Enable\nEthernet Transmission Clock Enable\nEthernet Transmission Clock Enable During CSleep Mode\nEthernet Transmission Clock Enable During CSleep Mode\nFDCAN Peripheral Clocks Enable\nFDCAN Peripheral Clocks Enable\nFDCAN Peripheral Clocks Enable During CSleep Mode\nFDCAN Peripheral Clocks Enable During CSleep Mode\nFDCAN block reset\nFDCAN kernel clock source selection\nFLASH Clock Enable During CSleep Mode\nFlash interface clock enable during csleep mode\nFMAC enable\nFMAC enable during CSleep Mode\nFMAC enable during CSleep Mode\nFMAC reset\nFMC Peripheral Clocks Enable\nFMC Peripheral Clocks Enable\nFMC Peripheral Clocks Enable During CSleep Mode\nFMC Peripheral Clocks Enable During CSleep Mode\nFMC block reset\nFMC kernel clock source selection\nFractional part of the multiplication factor for PLL VCO\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\nHASH peripheral clock enable\nHASH peripheral clock enable\nHASH peripheral clock enable during CSleep mode\nHASH peripheral clock enable during CSleep mode\nHash block reset\nD1 domain AHB prescaler\nHRTIM peripheral clock enable\nHRTIM peripheral clock enable\nHRTIM peripheral clock enable during CSleep mode\nHRTIM peripheral clock enable during CSleep mode\nHRTIM block reset\nHigh Resolution Timer clock prescaler selection\nCSI ready Interrupt Clear\nHSE clock bypass\nHSE clock security system Interrupt Clear\nHSE clock security system Interrupt Flag\nHSE Clock Security System enable\nHSEM peripheral clock enable\nHSEM peripheral clock enable\nHSEM block reset\nHSE clock enable\nHSE clock ready flag\nHSE ready Interrupt Clear\nHSE ready Interrupt Flag\nHSE ready Interrupt Enable\nInternal RC 48 MHz clock calibration\nRC48 clock enable\nRC48 clock ready flag\nRC48 ready Interrupt Clear\nRC48 ready Interrupt Flag\nRC48 ready Interrupt Enable\nHSI clock calibration\nHSI clock calibration\nHSI clock divider\nHSI divider flag\nHigh Speed Internal clock enable in Stop mode\nInternal high-speed clock enable\nHSI clock ready flag\nHSI ready Interrupt Clear\nHSI ready Interrupt Flag\nHSI ready Interrupt Enable\nHSI clock trimming\nHSI clock trimming\nI2C1,2,3 kernel clock source selection\nI2C1 Peripheral Clocks Enable\nI2C1 Peripheral Clocks Enable\nI2C1 Peripheral Clocks Enable During CSleep Mode\nI2C1 Peripheral Clocks Enable During CSleep Mode\nI2C1 block reset\nI2C2 Peripheral Clocks Enable\nI2C2 Peripheral Clocks Enable\nI2C2 Peripheral Clocks Enable During CSleep Mode\nI2C2 Peripheral Clocks Enable During CSleep Mode\nI2C2 block reset\nI2C3 Peripheral Clocks Enable\nI2C3 Peripheral Clocks Enable\nI2C3 Peripheral Clocks Enable During CSleep Mode\nI2C3 Peripheral Clocks Enable During CSleep Mode\nI2C3 block reset\nI2C4 Autonomous mode enable\nI2C4 Peripheral Clocks Enable\nI2C4 Peripheral Clocks Enable\nI2C4 Peripheral Clocks Enable During CSleep Mode\nI2C4 Peripheral Clocks Enable During CSleep Mode\nI2C4 block reset\nI2C4 kernel clock source selection\nI2C5 Peripheral Clocks Enable\nI2C5 Peripheral Clocks Enable\nI2C5 block enable during CSleep Mode\nI2C5 block enable during CSleep Mode\nI2C5 block reset\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nOCTOSPI IO manager enable\nOCTOSPI IO manager enable during CSleep Mode\nOCTOSPI IO manager enable during CSleep Mode\nOCTOSPI IO manager reset\nD1 ITCM block enable\nD1ITCM Block Clock Enable During CSleep mode\nD1ITCM Block Clock Enable During CSleep mode\nIndependent Watchdog reset flag\nIndependent Watchdog reset flag\nJPGDEC Peripheral Clock Enable\nJPGDEC Peripheral Clock Enable\nJPGDEC Clock Enable During CSleep Mode\nJPGDEC Clock Enable During CSleep Mode\nJPGDEC block reset\nLPTIM1 Peripheral Clocks Enable\nLPTIM1 Peripheral Clocks Enable\nLPTIM1 Peripheral Clocks Enable During CSleep Mode\nLPTIM1 Peripheral Clocks Enable During CSleep Mode\nTIM block reset\nLPTIM1 kernel clock source selection\nLPTIM2 Autonomous mode enable\nLPTIM2 Peripheral Clocks Enable\nLPTIM2 Peripheral Clocks Enable\nLPTIM2 Peripheral Clocks Enable During CSleep Mode\nLPTIM2 Peripheral Clocks Enable During CSleep Mode\nLPTIM2 block reset\nLPTIM2 kernel clock source selection\nLPTIM3,4,5 kernel clock source selection\nLPTIM3 Autonomous mode enable\nLPTIM3 Peripheral Clocks Enable\nLPTIM3 Peripheral Clocks Enable\nLPTIM3 Peripheral Clocks Enable During CSleep Mode\nLPTIM3 Peripheral Clocks Enable During CSleep Mode\nLPTIM3 block reset\nLPTIM4 Autonomous mode enable\nLPTIM4 Peripheral Clocks Enable\nLPTIM4 Peripheral Clocks Enable\nLPTIM4 Peripheral Clocks Enable During CSleep Mode\nLPTIM4 Peripheral Clocks Enable During CSleep Mode\nLPTIM4 block reset\nLPTIM5 Autonomous mode enable\nLPTIM5 Peripheral Clocks Enable\nLPTIM5 Peripheral Clocks Enable\nLPTIM5 Peripheral Clocks Enable During CSleep Mode\nLPTIM5 Peripheral Clocks Enable During CSleep Mode\nLPTIM5 block reset\nLPUART1 Autonomous mode enable\nLPUART1 Peripheral Clocks Enable\nLPUART1 Peripheral Clocks Enable\nLPUART1 Peripheral Clocks Enable During CSleep Mode\nLPUART1 Peripheral Clocks Enable During CSleep Mode\nLPUART1 block reset\nLPUART1 kernel clock source selection\nReset due to illegal D1 DStandby or CPU CStop flag\nReset due to illegal D1 DStandby or CPU CStop flag\nLSE oscillator bypass\nLSE clock security system Interrupt Clear\nLSE clock security system failure detection\nLSE clock security system Interrupt Flag\nLSE clock security system Interrupt Enable\nLSE clock security system enable\nLSE oscillator driving capability\nLSE oscillator enabled\nLSE oscillator ready\nLSE ready Interrupt Clear\nLSE ready Interrupt Flag\nLSE ready Interrupt Enable\nLSI oscillator enable\nLSI oscillator ready\nLSI ready Interrupt Clear\nLSI ready Interrupt Flag\nLSI ready Interrupt Enable\nLTDC peripheral clock enable\nLTDC peripheral clock enable\nLTDC peripheral clock enable during CSleep mode\nLTDC peripheral clock enable during CSleep mode\nLTDC block reset\nMCO1 prescaler\nMicro-controller clock output 1\nMCO2 prescaler\nMicro-controller clock output 2\nMDIOS peripheral clock enable\nMDIOS peripheral clock enable\nMDIOS peripheral clock enable during CSleep mode\nMDIOS peripheral clock enable during CSleep mode\nMDIOS block reset\nMDMA Peripheral Clock Enable\nMDMA Peripheral Clock Enable\nMDMA Clock Enable During CSleep Mode\nMDMA Clock Enable During CSleep Mode\nMDMA block reset\nOCTOSPI2 and OCTOSPI2 delay block enable\nOCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode\nOCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode\nOCTOSPI2 and OCTOSPI2 delay block reset\nOPAMP peripheral clock enable\nOPAMP peripheral clock enable\nOPAMP peripheral clock enable during CSleep mode\nOPAMP peripheral clock enable during CSleep mode\nOPAMP block reset\nOTFDEC1 enable\nOTFDEC1 enable during CSleep Mode\nOTFDEC1 enable during CSleep Mode\nOTFDEC1 reset\nOTFDEC2 enable\nOTFDEC2 enable during CSleep Mode\nOTFDEC2 enable during CSleep Mode\nOTFDEC2 reset\nPin reset flag (NRST)\nPin reset flag (NRST)\nPLL1 fractional latch enable\nMultiplication factor for PLL1 VCO\nPLL1 enable\nPLL DIVP division factor\nPLL DIVQ division factor\nPLL DIVR division factor\nPLL1 clock ready flag\nPLL1 ready Interrupt Clear\nPLL1 ready Interrupt Flag\nPLL1 ready Interrupt Enable\nPLL1 input frequency range\nDIVMx and PLLs clock source selection\nPLL1 VCO selection\nPOR/PDR reset flag\nPOR/PDR reset flag\nQUADSPI and QUADSPI Delay Clock Enable\nQUADSPI and QUADSPI Delay Clock Enable\nQUADSPI and QUADSPI Delay Clock Enable During CSleep Mode\nQUADSPI and QUADSPI Delay Clock Enable During CSleep Mode\nQUADSPI and QUADSPI delay block reset\nQUADSPI kernel clock source selection\nRemove reset flag\nRemove reset flag\nRNG peripheral clocks enable\nRNG peripheral clocks enable\nRNG peripheral clock enable during CSleep mode\nRNG peripheral clock enable during CSleep mode\nRandom Number Generator block reset\nRNG kernel clock source selection\nRTC Autonomous mode enable\nRTC APB Clock Enable\nRTC APB Clock Enable\nRTC APB Clock Enable During CSleep Mode\nRTC APB Clock Enable During CSleep Mode\nRTC clock enable\nHSE division factor for RTC clock\nRTC clock source selection\nSAI1 Peripheral Clocks Enable\nSAI1 Peripheral Clocks Enable\nSAI1 Peripheral Clocks Enable During CSleep Mode\nSAI1 Peripheral Clocks Enable During CSleep Mode\nSAI1 block reset\nSAI1 and DFSDM1 kernel Aclk clock source selection\nSAI2 and SAI3 kernel clock source selection\nSAI2 Peripheral Clocks Enable\nSAI2 Peripheral Clocks Enable\nSAI2 Peripheral Clocks Enable During CSleep Mode\nSAI2 Peripheral Clocks Enable During CSleep Mode\nSAI2 block reset\nSAI3 Peripheral Clocks Enable\nSAI3 Peripheral Clocks Enable\nSAI3 Peripheral Clocks Enable During CSleep Mode\nSAI3 Peripheral Clocks Enable During CSleep Mode\nSAI3 block reset\nSAI4 Autonomous mode enable\nSub-Block A of SAI4 kernel clock source selection\nSub-Block B of SAI4 kernel clock source selection\nSAI4 Peripheral Clocks Enable\nSAI4 Peripheral Clocks Enable\nSAI4 Peripheral Clocks Enable During CSleep Mode\nSAI4 Peripheral Clocks Enable During CSleep Mode\nSAI4 block reset\nSDMMC1 and SDMMC1 Delay Clock Enable\nSDMMC1 and SDMMC1 Delay Clock Enable\nSDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode\nSDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode\nSDMMC1 and SDMMC1 delay block reset\nSDMMC2 and SDMMC2 delay clock enable\nSDMMC2 and SDMMC2 delay clock enable\nSDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode\nSDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode\nSDMMC2 and SDMMC2 Delay block reset\nSDMMC kernel clock source selection\nADC1/2 Peripheral Clocks Enable\nADC1/2 Peripheral Clocks Enable\nADC1/2 Peripheral Clocks Enable During CSleep Mode\nADC1/2 Peripheral Clocks Enable During CSleep Mode\nADC1&amp;2 block reset\nADC3 Autonomous mode enable\nADC3 Peripheral Clocks Enable\nADC3 Peripheral Clocks Enable\nADC3 Peripheral Clocks Enable During CSleep Mode\nADC3 Peripheral Clocks Enable During CSleep Mode\nADC3 block reset\nSAR ADC kernel clock source selection\nART Clock Enable\nART Clock Enable\nART Clock Enable During CSleep Mode\nART Clock Enable During CSleep Mode\nART block reset\nAXISRAM block enable\nAXISRAM Block Clock Enable During CSleep mode\nAXISRAM Block Clock Enable During CSleep mode\nBDMA and DMAMUX Autonomous mode enable\nBDMA and DMAMUX2 Clock Enable\nBDMA and DMAMUX2 Clock Enable\nBDMA Clock Enable During CSleep Mode\nBDMA Clock Enable During CSleep Mode\nBDMA block reset\nVSwitch domain software reset\nBackup RAM Autonomous mode enable\nBackup RAM Clock Enable\nBackup RAM Clock Enable\nBackup RAM Clock Enable During CSleep Mode\nBackup RAM Clock Enable During CSleep Mode\nForce allow CPU1 to boot\nForce allow CPU2 to boot\nBOR reset flag\nBOR reset flag\nHDMI-CEC peripheral clock enable\nHDMI-CEC peripheral clock enable\nHDMI-CEC Peripheral Clocks Enable During CSleep Mode\nHDMI-CEC Peripheral Clocks Enable During CSleep Mode\nHDMI-CEC block reset\nHDMI-CEC kernel clock source selection\nper_ck clock source selection\nCOMP12 Autonomous mode enable\nCOMP1/2 peripheral clock enable\nCOMP1/2 peripheral clock enable\nCOMP1/2 peripheral clock enable during CSleep mode\nCOMP1/2 peripheral clock enable during CSleep mode\nCOMP12 Blocks Reset\nCORDIC enable\nCORDIC enable during CSleep Mode\nCORDIC enable during CSleep Mode\nCORDIC reset\nCPU reset\nCPU reset flag\nCPU reset flag\nCRC Autonomous mode enable\nCRC peripheral clock enable\nCRC peripheral clock enable\nCRC peripheral clock enable during CSleep mode\nCRC peripheral clock enable during CSleep mode\nCRC block reset\nClock Recovery System peripheral clock enable\nClock Recovery System peripheral clock enable\nClock Recovery System peripheral clock enable during …\nClock Recovery System peripheral clock enable during …\nClock Recovery System reset\nCRYPT peripheral clock enable\nCRYPT peripheral clock enable\nCRYPT peripheral clock enable during CSleep mode\nCRYPT peripheral clock enable during CSleep mode\nCryptography block reset\nCSI clock calibration\nCSI clock calibration\nCSI clock enable in Stop mode\nCSI clock enable\nCSI ready Interrupt Flag\nCSI clock ready flag\nCSI ready Interrupt Enable\nCSI clock trimming\nCSI clock trimming\nD1 domain clocks ready flag\nD1 domain Core prescaler\nD1DTCM1 Block Clock Enable During CSleep mode\nD1DTCM1 Block Clock Enable During CSleep mode\nD1 domain APB3 prescaler\nD1 domain power switch reset flag\nD1 domain power switch reset flag\nD2 domain clocks ready flag\nD2 domain APB1 prescaler\nD2 domain APB2 prescaler\nD2 domain power switch reset flag\nD2 domain power switch reset flag\nD3 domain APB4 prescaler\nDAC1&amp;2 peripheral clock enable\nDAC1&amp;2 peripheral clock enable\nDAC1/2 peripheral clock enable during CSleep mode\nDAC1/2 peripheral clock enable during CSleep mode\nDAC1 and 2 Blocks Reset\nDAC2 (containing one converter) Autonomous mode enable\nDAC2 (containing one converter) peripheral clock enable\nDAC2 (containing one converter) peripheral clock enable …\nDAC2 (containing one converter) reset\nDCMI peripheral clock\nDCMI peripheral clock\nDCMI peripheral clock enable during csleep mode\nDCMI peripheral clock enable during csleep mode\nDCMI block reset\nDFSDM1 Peripheral Clocks Enable\nDFSDM1 Peripheral Clocks Enable\nDFSDM1 Peripheral Clocks Enable During CSleep Mode\nDFSDM1 Peripheral Clocks Enable During CSleep Mode\nDFSDM1 block reset\nDFSDM1 kernel Clk clock source selection\nDFSDM2 kernel clock source selection\nPrescaler for PLL1\nPLL1 DIVP divider output enable\nPLL1 DIVQ divider output enable\nPLL1 DIVR divider output enable\nDMA1 Clock Enable\nDMA1 Clock Enable\nDMA1 Clock Enable During CSleep Mode\nDMA1 Clock Enable During CSleep Mode\nDMA1 block reset\nDMA2D Peripheral Clock Enable\nDMA2D Peripheral Clock Enable\nDMA2D Clock Enable During CSleep Mode\nDMA2D Clock Enable During CSleep Mode\nDMA2D block reset\nDMA2 Clock Enable\nDMA2 Clock Enable\nDMA2 Clock Enable During CSleep Mode\nDMA2 Clock Enable During CSleep Mode\nDMA2 block reset\nDSI Peripheral clocks enable\nDSI Peripheral clocks enable\nDSI Peripheral Clock Enable During CSleep Mode\nDSI Peripheral Clock Enable During CSleep Mode\nDSI block reset\nkernel clock source selection\nD1 DTCM1 block enable\nD1 DTCM2 block enable\nD1 DTCM2 Block Clock Enable During CSleep mode\nD1 DTCM2 Block Clock Enable During CSleep mode\nDigital temperature sensor Autonomous mode enable\nDigital temperature sensor block enable\nDigital temperature sensor block enable during CSleep Mode\nDigital temperature sensor block enable during CSleep Mode\nDigital temperature sensor block reset\nEthernet MAC bus interface Clock Enable\nEthernet MAC bus interface Clock Enable\nEthernet MAC bus interface Clock Enable During CSleep Mode\nEthernet MAC bus interface Clock Enable During CSleep Mode\nETH1MAC block reset\nEthernet Reception Clock Enable\nEthernet Reception Clock Enable\nEthernet Reception Clock Enable During CSleep Mode\nEthernet Reception Clock Enable During CSleep Mode\nEthernet Transmission Clock Enable\nEthernet Transmission Clock Enable\nEthernet Transmission Clock Enable During CSleep Mode\nEthernet Transmission Clock Enable During CSleep Mode\nFDCAN Peripheral Clocks Enable\nFDCAN Peripheral Clocks Enable\nFDCAN Peripheral Clocks Enable During CSleep Mode\nFDCAN Peripheral Clocks Enable During CSleep Mode\nFDCAN block reset\nFDCAN kernel clock source selection\nFLASH Clock Enable During CSleep Mode\nFlash interface clock enable during csleep mode\nFMAC enable\nFMAC enable during CSleep Mode\nFMAC enable during CSleep Mode\nFMAC reset\nFMC Peripheral Clocks Enable\nFMC Peripheral Clocks Enable\nFMC Peripheral Clocks Enable During CSleep Mode\nFMC Peripheral Clocks Enable During CSleep Mode\nFMC block reset\nFMC kernel clock source selection\nFractional part of the multiplication factor for PLL VCO\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\n0GPIO peripheral clock enable\n0GPIO peripheral clock enable\nGPIO peripheral clock enable during CSleep mode\nGPIO peripheral clock enable during CSleep mode\nGPIO block reset\nHASH peripheral clock enable\nHASH peripheral clock enable\nHASH peripheral clock enable during CSleep mode\nHASH peripheral clock enable during CSleep mode\nHash block reset\nD1 domain AHB prescaler\nHRTIM peripheral clock enable\nHRTIM peripheral clock enable\nHRTIM peripheral clock enable during CSleep mode\nHRTIM peripheral clock enable during CSleep mode\nHRTIM block reset\nHigh Resolution Timer clock prescaler selection\nCSI ready Interrupt Clear\nHSE clock bypass\nHSE clock security system Interrupt Clear\nHSE clock security system Interrupt Flag\nHSE Clock Security System enable\nHSEM peripheral clock enable\nHSEM peripheral clock enable\nHSEM block reset\nHSE clock enable\nHSE clock ready flag\nHSE ready Interrupt Clear\nHSE ready Interrupt Flag\nHSE ready Interrupt Enable\nInternal RC 48 MHz clock calibration\nRC48 clock enable\nRC48 clock ready flag\nRC48 ready Interrupt Clear\nRC48 ready Interrupt Flag\nRC48 ready Interrupt Enable\nHSI clock calibration\nHSI clock calibration\nHSI clock divider\nHSI divider flag\nHigh Speed Internal clock enable in Stop mode\nInternal high-speed clock enable\nHSI clock ready flag\nHSI ready Interrupt Clear\nHSI ready Interrupt Flag\nHSI ready Interrupt Enable\nHSI clock trimming\nHSI clock trimming\nI2C1,2,3 kernel clock source selection\nI2C1 Peripheral Clocks Enable\nI2C1 Peripheral Clocks Enable\nI2C1 Peripheral Clocks Enable During CSleep Mode\nI2C1 Peripheral Clocks Enable During CSleep Mode\nI2C1 block reset\nI2C2 Peripheral Clocks Enable\nI2C2 Peripheral Clocks Enable\nI2C2 Peripheral Clocks Enable During CSleep Mode\nI2C2 Peripheral Clocks Enable During CSleep Mode\nI2C2 block reset\nI2C3 Peripheral Clocks Enable\nI2C3 Peripheral Clocks Enable\nI2C3 Peripheral Clocks Enable During CSleep Mode\nI2C3 Peripheral Clocks Enable During CSleep Mode\nI2C3 block reset\nI2C4 Autonomous mode enable\nI2C4 Peripheral Clocks Enable\nI2C4 Peripheral Clocks Enable\nI2C4 Peripheral Clocks Enable During CSleep Mode\nI2C4 Peripheral Clocks Enable During CSleep Mode\nI2C4 block reset\nI2C4 kernel clock source selection\nI2C5 Peripheral Clocks Enable\nI2C5 Peripheral Clocks Enable\nI2C5 block enable during CSleep Mode\nI2C5 block enable during CSleep Mode\nI2C5 block reset\nOCTOSPI IO manager enable\nOCTOSPI IO manager enable during CSleep Mode\nOCTOSPI IO manager enable during CSleep Mode\nOCTOSPI IO manager reset\nD1 ITCM block enable\nD1ITCM Block Clock Enable During CSleep mode\nD1ITCM Block Clock Enable During CSleep mode\nIndependent Watchdog reset flag\nIndependent Watchdog reset flag\nJPGDEC Peripheral Clock Enable\nJPGDEC Peripheral Clock Enable\nJPGDEC Clock Enable During CSleep Mode\nJPGDEC Clock Enable During CSleep Mode\nJPGDEC block reset\nLPTIM1 Peripheral Clocks Enable\nLPTIM1 Peripheral Clocks Enable\nLPTIM1 Peripheral Clocks Enable During CSleep Mode\nLPTIM1 Peripheral Clocks Enable During CSleep Mode\nTIM block reset\nLPTIM1 kernel clock source selection\nLPTIM2 Autonomous mode enable\nLPTIM2 Peripheral Clocks Enable\nLPTIM2 Peripheral Clocks Enable\nLPTIM2 Peripheral Clocks Enable During CSleep Mode\nLPTIM2 Peripheral Clocks Enable During CSleep Mode\nLPTIM2 block reset\nLPTIM2 kernel clock source selection\nLPTIM3,4,5 kernel clock source selection\nLPTIM3 Autonomous mode enable\nLPTIM3 Peripheral Clocks Enable\nLPTIM3 Peripheral Clocks Enable\nLPTIM3 Peripheral Clocks Enable During CSleep Mode\nLPTIM3 Peripheral Clocks Enable During CSleep Mode\nLPTIM3 block reset\nLPTIM4 Autonomous mode enable\nLPTIM4 Peripheral Clocks Enable\nLPTIM4 Peripheral Clocks Enable\nLPTIM4 Peripheral Clocks Enable During CSleep Mode\nLPTIM4 Peripheral Clocks Enable During CSleep Mode\nLPTIM4 block reset\nLPTIM5 Autonomous mode enable\nLPTIM5 Peripheral Clocks Enable\nLPTIM5 Peripheral Clocks Enable\nLPTIM5 Peripheral Clocks Enable During CSleep Mode\nLPTIM5 Peripheral Clocks Enable During CSleep Mode\nLPTIM5 block reset\nLPUART1 Autonomous mode enable\nLPUART1 Peripheral Clocks Enable\nLPUART1 Peripheral Clocks Enable\nLPUART1 Peripheral Clocks Enable During CSleep Mode\nLPUART1 Peripheral Clocks Enable During CSleep Mode\nLPUART1 block reset\nLPUART1 kernel clock source selection\nReset due to illegal D1 DStandby or CPU CStop flag\nReset due to illegal D1 DStandby or CPU CStop flag\nLSE oscillator bypass\nLSE clock security system Interrupt Clear\nLSE clock security system failure detection\nLSE clock security system Interrupt Flag\nLSE clock security system Interrupt Enable\nLSE clock security system enable\nLSE oscillator driving capability\nLSE oscillator enabled\nLSE oscillator ready\nLSE ready Interrupt Clear\nLSE ready Interrupt Flag\nLSE ready Interrupt Enable\nLSI oscillator enable\nLSI oscillator ready\nLSI ready Interrupt Clear\nLSI ready Interrupt Flag\nLSI ready Interrupt Enable\nLTDC peripheral clock enable\nLTDC peripheral clock enable\nLTDC peripheral clock enable during CSleep mode\nLTDC peripheral clock enable during CSleep mode\nLTDC block reset\nMCO1 prescaler\nMicro-controller clock output 1\nMCO2 prescaler\nMicro-controller clock output 2\nMDIOS peripheral clock enable\nMDIOS peripheral clock enable\nMDIOS peripheral clock enable during CSleep mode\nMDIOS peripheral clock enable during CSleep mode\nMDIOS block reset\nMDMA Peripheral Clock Enable\nMDMA Peripheral Clock Enable\nMDMA Clock Enable During CSleep Mode\nMDMA Clock Enable During CSleep Mode\nMDMA block reset\nOCTOSPI2 and OCTOSPI2 delay block enable\nOCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode\nOCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode\nOCTOSPI2 and OCTOSPI2 delay block reset\nOPAMP peripheral clock enable\nOPAMP peripheral clock enable\nOPAMP peripheral clock enable during CSleep mode\nOPAMP peripheral clock enable during CSleep mode\nOPAMP block reset\nOTFDEC1 enable\nOTFDEC1 enable during CSleep Mode\nOTFDEC1 enable during CSleep Mode\nOTFDEC1 reset\nOTFDEC2 enable\nOTFDEC2 enable during CSleep Mode\nOTFDEC2 enable during CSleep Mode\nOTFDEC2 reset\nPin reset flag (NRST)\nPin reset flag (NRST)\nPLL1 fractional latch enable\nMultiplication factor for PLL1 VCO\nPLL1 enable\nPLL DIVP division factor\nPLL DIVQ division factor\nPLL DIVR division factor\nPLL1 clock ready flag\nPLL1 ready Interrupt Clear\nPLL1 ready Interrupt Flag\nPLL1 ready Interrupt Enable\nPLL1 input frequency range\nDIVMx and PLLs clock source selection\nPLL1 VCO selection\nPOR/PDR reset flag\nPOR/PDR reset flag\nQUADSPI and QUADSPI Delay Clock Enable\nQUADSPI and QUADSPI Delay Clock Enable\nQUADSPI and QUADSPI Delay Clock Enable During CSleep Mode\nQUADSPI and QUADSPI Delay Clock Enable During CSleep Mode\nQUADSPI and QUADSPI delay block reset\nQUADSPI kernel clock source selection\nRemove reset flag\nRemove reset flag\nRNG peripheral clocks enable\nRNG peripheral clocks enable\nRNG peripheral clock enable during CSleep mode\nRNG peripheral clock enable during CSleep mode\nRandom Number Generator block reset\nRNG kernel clock source selection\nRTC Autonomous mode enable\nRTC APB Clock Enable\nRTC APB Clock Enable\nRTC APB Clock Enable During CSleep Mode\nRTC APB Clock Enable During CSleep Mode\nRTC clock enable\nHSE division factor for RTC clock\nRTC clock source selection\nSAI1 Peripheral Clocks Enable\nSAI1 Peripheral Clocks Enable\nSAI1 Peripheral Clocks Enable During CSleep Mode\nSAI1 Peripheral Clocks Enable During CSleep Mode\nSAI1 block reset\nSAI1 and DFSDM1 kernel Aclk clock source selection\nSAI2 and SAI3 kernel clock source selection\nSAI2 Peripheral Clocks Enable\nSAI2 Peripheral Clocks Enable\nSAI2 Peripheral Clocks Enable During CSleep Mode\nSAI2 Peripheral Clocks Enable During CSleep Mode\nSAI2 block reset\nSAI3 Peripheral Clocks Enable\nSAI3 Peripheral Clocks Enable\nSAI3 Peripheral Clocks Enable During CSleep Mode\nSAI3 Peripheral Clocks Enable During CSleep Mode\nSAI3 block reset\nSAI4 Autonomous mode enable\nSub-Block A of SAI4 kernel clock source selection\nSub-Block B of SAI4 kernel clock source selection\nSAI4 Peripheral Clocks Enable\nSAI4 Peripheral Clocks Enable\nSAI4 Peripheral Clocks Enable During CSleep Mode\nSAI4 Peripheral Clocks Enable During CSleep Mode\nSAI4 block reset\nSDMMC1 and SDMMC1 Delay Clock Enable\nSDMMC1 and SDMMC1 Delay Clock Enable\nSDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode\nSDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode\nSDMMC1 and SDMMC1 delay block reset\nSDMMC2 and SDMMC2 delay clock enable\nSDMMC2 and SDMMC2 delay clock enable\nSDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode\nSDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode\nSDMMC2 and SDMMC2 Delay block reset\nSDMMC kernel clock source selection\nSystem reset from CPU reset flag\nSystem reset from CPU reset flag\nSPDIFRX Peripheral Clocks Enable\nSPDIFRX Peripheral Clocks Enable\nSPDIFRX Peripheral Clocks Enable During CSleep Mode\nSPDIFRX Peripheral Clocks Enable During CSleep Mode\nSPDIFRX block reset\nSPDIFRX kernel clock source selection\nSPI/I2S1,2 and 3 kernel clock source selection\nSPI1 Peripheral Clocks Enable\nSPI1 Peripheral Clocks Enable\nSPI1 Peripheral Clocks Enable During CSleep Mode\nSPI1 Peripheral Clocks Enable During CSleep Mode\nSPI1 block reset\nSPI2 Peripheral Clocks Enable\nSPI2 Peripheral Clocks Enable\nSPI2 Peripheral Clocks Enable During CSleep Mode\nSPI2 Peripheral Clocks Enable During CSleep Mode\nSPI2 block reset\nSPI3 Peripheral Clocks Enable\nSPI3 Peripheral Clocks Enable\nSPI3 Peripheral Clocks Enable During CSleep Mode\nSPI3 Peripheral Clocks Enable During CSleep Mode\nSPI3 block reset\nSPI4 and 5 kernel clock source selection\nSPI4 Peripheral Clocks Enable\nSPI4 Peripheral Clocks Enable\nSPI4 Peripheral Clocks Enable During CSleep Mode\nSPI4 Peripheral Clocks Enable During CSleep Mode\nSPI4 block reset\nSPI5 Peripheral Clocks Enable\nSPI5 Peripheral Clocks Enable\nSPI5 Peripheral Clocks Enable During CSleep Mode\nSPI5 Peripheral Clocks Enable During CSleep Mode\nSPI5 block reset\nSPI6 Autonomous mode enable\nSPI6 Peripheral Clocks Enable\nSPI6 Peripheral Clocks Enable\nSPI6 Peripheral Clocks Enable During CSleep Mode\nSPI6 Peripheral Clocks Enable During CSleep Mode\nSPI6 block reset\nSPI6 kernel clock source selection\nSRAM1 block enable\nSRAM1 block enable\nSRAM1 Clock Enable During CSleep Mode\nSRAM1 Clock Enable During CSleep Mode\nSRAM2 block enable\nSRAM2 block enable\nSRAM2 Clock Enable During CSleep Mode\nSRAM2 Clock Enable During CSleep Mode\nSRAM3 block enable\nSRAM3 block enable\nSRAM3 Clock Enable During CSleep Mode\nSRAM3 Clock Enable During CSleep Mode\nSRAM4 Autonomous mode enable\nSRAM4 Clock Enable During CSleep Mode\nSRAM4 Clock Enable During CSleep Mode\nKernel clock selection after a wake up from system Stop\nSystem clock selection after a wake up from system Stop\nSystem clock switch\nSWPMI Peripheral Clocks Enable\nSWPMI Peripheral Clocks Enable\nSWPMI Peripheral Clocks Enable During CSleep Mode\nSWPMI Peripheral Clocks Enable During CSleep Mode\nSWPMI block reset\nSWPMI kernel clock source selection\nSystem clock switch status\nSYSCFG peripheral clock enable\nSYSCFG peripheral clock enable\nSYSCFG peripheral clock enable during CSleep mode\nSYSCFG peripheral clock enable during CSleep mode\nSYSCFG block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM12 peripheral clock enable during CSleep mode\nTIM12 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM13 peripheral clock enable during CSleep mode\nTIM13 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM14 peripheral clock enable during CSleep mode\nTIM14 peripheral clock enable during CSleep mode\nTIM block reset\nTIM15 peripheral clock enable\nTIM15 peripheral clock enable\nTIM15 peripheral clock enable during CSleep mode\nTIM15 peripheral clock enable during CSleep mode\nTIM15 block reset\nTIM16 peripheral clock enable\nTIM16 peripheral clock enable\nTIM16 peripheral clock enable during CSleep mode\nTIM16 peripheral clock enable during CSleep mode\nTIM16 block reset\nTIM17 peripheral clock enable\nTIM17 peripheral clock enable\nTIM17 peripheral clock enable during CSleep mode\nTIM17 peripheral clock enable during CSleep mode\nTIM17 block reset\nTIM1 peripheral clock enable\nTIM1 peripheral clock enable\nTIM1 peripheral clock enable during CSleep mode\nTIM1 peripheral clock enable during CSleep mode\nTIM1 block reset\nTIM23 block enable\nTIM23 block enable during CSleep Mode\nTIM23 block enable during CSleep Mode\nTIM23 block reset\nTIM24 block enable\nTIM24 block enable during CSleep Mode\nTIM24 block enable during CSleep Mode\nTIM24 block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM2 peripheral clock enable during CSleep mode\nTIM2 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM3 peripheral clock enable during CSleep mode\nTIM3 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM4 peripheral clock enable during CSleep mode\nTIM4 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM5 peripheral clock enable during CSleep mode\nTIM5 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM6 peripheral clock enable during CSleep mode\nTIM6 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM7 peripheral clock enable during CSleep mode\nTIM7 peripheral clock enable during CSleep mode\nTIM block reset\nTIM8 peripheral clock enable\nTIM8 peripheral clock enable\nTIM8 peripheral clock enable during CSleep mode\nTIM8 peripheral clock enable during CSleep mode\nTIM8 block reset\nTimers clocks prescaler selection\nUART4 Peripheral Clocks Enable\nUART4 Peripheral Clocks Enable\nUART4 Peripheral Clocks Enable During CSleep Mode\nUART4 Peripheral Clocks Enable During CSleep Mode\nUART4 block reset\nUART5 Peripheral Clocks Enable\nUART5 Peripheral Clocks Enable\nUART5 Peripheral Clocks Enable During CSleep Mode\nUART5 Peripheral Clocks Enable During CSleep Mode\nUART5 block reset\nUART7 Peripheral Clocks Enable\nUART7 Peripheral Clocks Enable\nUART7 Peripheral Clocks Enable During CSleep Mode\nUART7 Peripheral Clocks Enable During CSleep Mode\nUART7 block reset\nUART8 Peripheral Clocks Enable\nUART8 Peripheral Clocks Enable\nUART8 Peripheral Clocks Enable During CSleep Mode\nUART8 Peripheral Clocks Enable During CSleep Mode\nUART8 block reset\nUART9 Peripheral Clocks Enable\nUART9 Peripheral Clocks Enable\nUART9 block reset\nUSART10 Peripheral Clocks Enable\nUSART10 Peripheral Clocks Enable\nUSART10 block reset\nUSART1, 6, 9 and 10 kernel clock source selection\nUSART1 Peripheral Clocks Enable\nUSART1 Peripheral Clocks Enable\nUSART1 Peripheral Clocks Enable During CSleep Mode\nUSART1 Peripheral Clocks Enable During CSleep Mode\nUSART1 block reset\nUSART2/3, UART4,5, 7/8 (APB1) kernel clock source selection\nUSART2 Peripheral Clocks Enable\nUSART2 Peripheral Clocks Enable\nUSART2 Peripheral Clocks Enable During CSleep Mode\nUSART2 Peripheral Clocks Enable During CSleep Mode\nUSART2 block reset\nUSART3 Peripheral Clocks Enable\nUSART3 Peripheral Clocks Enable\nUSART3 Peripheral Clocks Enable During CSleep Mode\nUSART3 Peripheral Clocks Enable During CSleep Mode\nUSART3 block reset\nUSART6 Peripheral Clocks Enable\nUSART6 Peripheral Clocks Enable\nUSART6 Peripheral Clocks Enable During CSleep Mode\nUSART6 Peripheral Clocks Enable During CSleep Mode\nUSART6 block reset\nUSB_OTG_FS ULPI clock enable\nUSB_PHY2 Clocks Enable\nUSB_PHY2 clocks enable during CSleep mode\nUSB_PHY2 clocks enable during CSleep mode\nUSB_OTG_FS Peripheral Clocks Enable\nUSB_OTG_FS Peripheral Clocks Enable\nUSB_OTG_FS peripheral clock enable during CSleep mode\nUSB_OTG_FS peripheral clock enable during CSleep mode\nUSB_OTG_FS block reset\nUSB_OTG_HS ULPI clock enable\nUSB_PHY1 Clocks Enable\nUSB_PHY1 clock enable during CSleep mode\nUSB_PHY1 clock enable during CSleep mode\nUSB_OTG_HS Peripheral Clocks Enable\nUSB_OTG_HS Peripheral Clocks Enable\nUSB_OTG_HS peripheral clock enable during CSleep mode\nUSB_OTG_HS peripheral clock enable during CSleep mode\nUSB_OTG_HS block reset\nUSBOTG 1 and 2 kernel clock source selection\nVREF Autonomous mode enable\nVREF peripheral clock enable\nVREF peripheral clock enable\nVREF peripheral clock enable during CSleep mode\nVREF peripheral clock enable during CSleep mode\nVREF block reset\nWWDG1 reset scope control\nWWDG2 reset scope control\nWWDG1 Clock Enable\nWWDG1 Clock Enable\nWWDG1 Clock Enable During CSleep Mode\nWWDG1 Clock Enable During CSleep Mode\nWindow Watchdog reset flag\nWindow Watchdog reset flag\nWWDG2 peripheral clock enable\nWWDG2 peripheral clock enable\nWWDG2 peripheral Clocks Enable During CSleep Mode\nWWDG2 peripheral Clocks Enable During CSleep Mode\nSystem reset from CPU reset flag\nSystem reset from CPU reset flag\nSPDIFRX Peripheral Clocks Enable\nSPDIFRX Peripheral Clocks Enable\nSPDIFRX Peripheral Clocks Enable During CSleep Mode\nSPDIFRX Peripheral Clocks Enable During CSleep Mode\nSPDIFRX block reset\nSPDIFRX kernel clock source selection\nSPI/I2S1,2 and 3 kernel clock source selection\nSPI1 Peripheral Clocks Enable\nSPI1 Peripheral Clocks Enable\nSPI1 Peripheral Clocks Enable During CSleep Mode\nSPI1 Peripheral Clocks Enable During CSleep Mode\nSPI1 block reset\nSPI2 Peripheral Clocks Enable\nSPI2 Peripheral Clocks Enable\nSPI2 Peripheral Clocks Enable During CSleep Mode\nSPI2 Peripheral Clocks Enable During CSleep Mode\nSPI2 block reset\nSPI3 Peripheral Clocks Enable\nSPI3 Peripheral Clocks Enable\nSPI3 Peripheral Clocks Enable During CSleep Mode\nSPI3 Peripheral Clocks Enable During CSleep Mode\nSPI3 block reset\nSPI4 and 5 kernel clock source selection\nSPI4 Peripheral Clocks Enable\nSPI4 Peripheral Clocks Enable\nSPI4 Peripheral Clocks Enable During CSleep Mode\nSPI4 Peripheral Clocks Enable During CSleep Mode\nSPI4 block reset\nSPI5 Peripheral Clocks Enable\nSPI5 Peripheral Clocks Enable\nSPI5 Peripheral Clocks Enable During CSleep Mode\nSPI5 Peripheral Clocks Enable During CSleep Mode\nSPI5 block reset\nSPI6 Autonomous mode enable\nSPI6 Peripheral Clocks Enable\nSPI6 Peripheral Clocks Enable\nSPI6 Peripheral Clocks Enable During CSleep Mode\nSPI6 Peripheral Clocks Enable During CSleep Mode\nSPI6 block reset\nSPI6 kernel clock source selection\nSRAM1 block enable\nSRAM1 block enable\nSRAM1 Clock Enable During CSleep Mode\nSRAM1 Clock Enable During CSleep Mode\nSRAM2 block enable\nSRAM2 block enable\nSRAM2 Clock Enable During CSleep Mode\nSRAM2 Clock Enable During CSleep Mode\nSRAM3 block enable\nSRAM3 block enable\nSRAM3 Clock Enable During CSleep Mode\nSRAM3 Clock Enable During CSleep Mode\nSRAM4 Autonomous mode enable\nSRAM4 Clock Enable During CSleep Mode\nSRAM4 Clock Enable During CSleep Mode\nKernel clock selection after a wake up from system Stop\nSystem clock selection after a wake up from system Stop\nSystem clock switch\nSWPMI Peripheral Clocks Enable\nSWPMI Peripheral Clocks Enable\nSWPMI Peripheral Clocks Enable During CSleep Mode\nSWPMI Peripheral Clocks Enable During CSleep Mode\nSWPMI block reset\nSWPMI kernel clock source selection\nSystem clock switch status\nSYSCFG peripheral clock enable\nSYSCFG peripheral clock enable\nSYSCFG peripheral clock enable during CSleep mode\nSYSCFG peripheral clock enable during CSleep mode\nSYSCFG block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM12 peripheral clock enable during CSleep mode\nTIM12 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM13 peripheral clock enable during CSleep mode\nTIM13 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM14 peripheral clock enable during CSleep mode\nTIM14 peripheral clock enable during CSleep mode\nTIM block reset\nTIM15 peripheral clock enable\nTIM15 peripheral clock enable\nTIM15 peripheral clock enable during CSleep mode\nTIM15 peripheral clock enable during CSleep mode\nTIM15 block reset\nTIM16 peripheral clock enable\nTIM16 peripheral clock enable\nTIM16 peripheral clock enable during CSleep mode\nTIM16 peripheral clock enable during CSleep mode\nTIM16 block reset\nTIM17 peripheral clock enable\nTIM17 peripheral clock enable\nTIM17 peripheral clock enable during CSleep mode\nTIM17 peripheral clock enable during CSleep mode\nTIM17 block reset\nTIM1 peripheral clock enable\nTIM1 peripheral clock enable\nTIM1 peripheral clock enable during CSleep mode\nTIM1 peripheral clock enable during CSleep mode\nTIM1 block reset\nTIM23 block enable\nTIM23 block enable during CSleep Mode\nTIM23 block enable during CSleep Mode\nTIM23 block reset\nTIM24 block enable\nTIM24 block enable during CSleep Mode\nTIM24 block enable during CSleep Mode\nTIM24 block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM2 peripheral clock enable during CSleep mode\nTIM2 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM3 peripheral clock enable during CSleep mode\nTIM3 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM4 peripheral clock enable during CSleep mode\nTIM4 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM5 peripheral clock enable during CSleep mode\nTIM5 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM6 peripheral clock enable during CSleep mode\nTIM6 peripheral clock enable during CSleep mode\nTIM block reset\nTIM peripheral clock enable\nTIM peripheral clock enable\nTIM7 peripheral clock enable during CSleep mode\nTIM7 peripheral clock enable during CSleep mode\nTIM block reset\nTIM8 peripheral clock enable\nTIM8 peripheral clock enable\nTIM8 peripheral clock enable during CSleep mode\nTIM8 peripheral clock enable during CSleep mode\nTIM8 block reset\nTimers clocks prescaler selection\nUART4 Peripheral Clocks Enable\nUART4 Peripheral Clocks Enable\nUART4 Peripheral Clocks Enable During CSleep Mode\nUART4 Peripheral Clocks Enable During CSleep Mode\nUART4 block reset\nUART5 Peripheral Clocks Enable\nUART5 Peripheral Clocks Enable\nUART5 Peripheral Clocks Enable During CSleep Mode\nUART5 Peripheral Clocks Enable During CSleep Mode\nUART5 block reset\nUART7 Peripheral Clocks Enable\nUART7 Peripheral Clocks Enable\nUART7 Peripheral Clocks Enable During CSleep Mode\nUART7 Peripheral Clocks Enable During CSleep Mode\nUART7 block reset\nUART8 Peripheral Clocks Enable\nUART8 Peripheral Clocks Enable\nUART8 Peripheral Clocks Enable During CSleep Mode\nUART8 Peripheral Clocks Enable During CSleep Mode\nUART8 block reset\nUART9 Peripheral Clocks Enable\nUART9 Peripheral Clocks Enable\nUART9 block reset\nUSART10 Peripheral Clocks Enable\nUSART10 Peripheral Clocks Enable\nUSART10 block reset\nUSART1, 6, 9 and 10 kernel clock source selection\nUSART1 Peripheral Clocks Enable\nUSART1 Peripheral Clocks Enable\nUSART1 Peripheral Clocks Enable During CSleep Mode\nUSART1 Peripheral Clocks Enable During CSleep Mode\nUSART1 block reset\nUSART2/3, UART4,5, 7/8 (APB1) kernel clock source selection\nUSART2 Peripheral Clocks Enable\nUSART2 Peripheral Clocks Enable\nUSART2 Peripheral Clocks Enable During CSleep Mode\nUSART2 Peripheral Clocks Enable During CSleep Mode\nUSART2 block reset\nUSART3 Peripheral Clocks Enable\nUSART3 Peripheral Clocks Enable\nUSART3 Peripheral Clocks Enable During CSleep Mode\nUSART3 Peripheral Clocks Enable During CSleep Mode\nUSART3 block reset\nUSART6 Peripheral Clocks Enable\nUSART6 Peripheral Clocks Enable\nUSART6 Peripheral Clocks Enable During CSleep Mode\nUSART6 Peripheral Clocks Enable During CSleep Mode\nUSART6 block reset\nUSB_OTG_FS ULPI clock enable\nUSB_PHY2 Clocks Enable\nUSB_PHY2 clocks enable during CSleep mode\nUSB_PHY2 clocks enable during CSleep mode\nUSB_OTG_FS Peripheral Clocks Enable\nUSB_OTG_FS Peripheral Clocks Enable\nUSB_OTG_FS peripheral clock enable during CSleep mode\nUSB_OTG_FS peripheral clock enable during CSleep mode\nUSB_OTG_FS block reset\nUSB_OTG_HS ULPI clock enable\nUSB_PHY1 Clocks Enable\nUSB_PHY1 clock enable during CSleep mode\nUSB_PHY1 clock enable during CSleep mode\nUSB_OTG_HS Peripheral Clocks Enable\nUSB_OTG_HS Peripheral Clocks Enable")