rtic/2/api/search.desc/rp2040_pac/rp2040_pac-desc-4-.js

searchState.loadedDescShard("rp2040_pac", 4, "Field <code>EP12_OUT</code> writer -\nField <code>EP13_IN</code> reader -\nField <code>EP13_IN</code> writer -\nField <code>EP13_OUT</code> reader -\nField <code>EP13_OUT</code> writer -\nField <code>EP14_IN</code> reader -\nField <code>EP14_IN</code> writer -\nField <code>EP14_OUT</code> reader -\nField <code>EP14_OUT</code> writer -\nField <code>EP15_IN</code> reader -\nField <code>EP15_IN</code> writer -\nField <code>EP15_OUT</code> reader -\nField <code>EP15_OUT</code> writer -\nField <code>EP1_IN</code> reader -\nField <code>EP1_IN</code> writer -\nField <code>EP1_OUT</code> reader -\nField <code>EP1_OUT</code> writer -\nField <code>EP2_IN</code> reader -\nField <code>EP2_IN</code> writer -\nField <code>EP2_OUT</code> reader -\nField <code>EP2_OUT</code> writer -\nField <code>EP3_IN</code> reader -\nField <code>EP3_IN</code> writer -\nField <code>EP3_OUT</code> reader -\nField <code>EP3_OUT</code> writer -\nField <code>EP4_IN</code> reader -\nField <code>EP4_IN</code> writer -\nField <code>EP4_OUT</code> reader -\nField <code>EP4_OUT</code> writer -\nField <code>EP5_IN</code> reader -\nField <code>EP5_IN</code> writer -\nField <code>EP5_OUT</code> reader -\nField <code>EP5_OUT</code> writer -\nField <code>EP6_IN</code> reader -\nField <code>EP6_IN</code> writer -\nField <code>EP6_OUT</code> reader -\nField <code>EP6_OUT</code> writer -\nField <code>EP7_IN</code> reader -\nField <code>EP7_IN</code> writer -\nField <code>EP7_OUT</code> reader -\nField <code>EP7_OUT</code> writer -\nField <code>EP8_IN</code> reader -\nField <code>EP8_IN</code> writer -\nField <code>EP8_OUT</code> reader -\nField <code>EP8_OUT</code> writer -\nField <code>EP9_IN</code> reader -\nField <code>EP9_IN</code> writer -\nField <code>EP9_OUT</code> reader -\nField <code>EP9_OUT</code> writer -\nDevice only: Can be set to ignore the buffer control …\nRegister <code>EP_ABORT</code> reader\nRegister <code>EP_ABORT</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nBit 20\nBit 20\nBit 21\nBit 21\nBit 22\nBit 22\nBit 23\nBit 23\nBit 24\nBit 24\nBit 25\nBit 25\nBit 26\nBit 26\nBit 27\nBit 27\nBit 28\nBit 28\nBit 29\nBit 29\nBit 30\nBit 30\nBit 31\nBit 31\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 12\nBit 12\nBit 13\nBit 13\nBit 14\nBit 14\nBit 15\nBit 15\nBit 16\nBit 16\nBit 17\nBit 17\nBit 18\nBit 18\nBit 19\nBit 19\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>EP0_IN</code> reader -\nField <code>EP0_IN</code> writer -\nField <code>EP0_OUT</code> reader -\nField <code>EP0_OUT</code> writer -\nField <code>EP10_IN</code> reader -\nField <code>EP10_IN</code> writer -\nField <code>EP10_OUT</code> reader -\nField <code>EP10_OUT</code> writer -\nField <code>EP11_IN</code> reader -\nField <code>EP11_IN</code> writer -\nField <code>EP11_OUT</code> reader -\nField <code>EP11_OUT</code> writer -\nField <code>EP12_IN</code> reader -\nField <code>EP12_IN</code> writer -\nField <code>EP12_OUT</code> reader -\nField <code>EP12_OUT</code> writer -\nField <code>EP13_IN</code> reader -\nField <code>EP13_IN</code> writer -\nField <code>EP13_OUT</code> reader -\nField <code>EP13_OUT</code> writer -\nField <code>EP14_IN</code> reader -\nField <code>EP14_IN</code> writer -\nField <code>EP14_OUT</code> reader -\nField <code>EP14_OUT</code> writer -\nField <code>EP15_IN</code> reader -\nField <code>EP15_IN</code> writer -\nField <code>EP15_OUT</code> reader -\nField <code>EP15_OUT</code> writer -\nField <code>EP1_IN</code> reader -\nField <code>EP1_IN</code> writer -\nField <code>EP1_OUT</code> reader -\nField <code>EP1_OUT</code> writer -\nField <code>EP2_IN</code> reader -\nField <code>EP2_IN</code> writer -\nField <code>EP2_OUT</code> reader -\nField <code>EP2_OUT</code> writer -\nField <code>EP3_IN</code> reader -\nField <code>EP3_IN</code> writer -\nField <code>EP3_OUT</code> reader -\nField <code>EP3_OUT</code> writer -\nField <code>EP4_IN</code> reader -\nField <code>EP4_IN</code> writer -\nField <code>EP4_OUT</code> reader -\nField <code>EP4_OUT</code> writer -\nField <code>EP5_IN</code> reader -\nField <code>EP5_IN</code> writer -\nField <code>EP5_OUT</code> reader -\nField <code>EP5_OUT</code> writer -\nField <code>EP6_IN</code> reader -\nField <code>EP6_IN</code> writer -\nField <code>EP6_OUT</code> reader -\nField <code>EP6_OUT</code> writer -\nField <code>EP7_IN</code> reader -\nField <code>EP7_IN</code> writer -\nField <code>EP7_OUT</code> reader -\nField <code>EP7_OUT</code> writer -\nField <code>EP8_IN</code> reader -\nField <code>EP8_IN</code> writer -\nField <code>EP8_OUT</code> reader -\nField <code>EP8_OUT</code> writer -\nField <code>EP9_IN</code> reader -\nField <code>EP9_IN</code> writer -\nField <code>EP9_OUT</code> reader -\nField <code>EP9_OUT</code> writer -\nDevice only: Used in conjunction with <code>EP_ABORT</code>. Set once …\nRegister <code>EP_ABORT_DONE</code> reader\nRegister <code>EP_ABORT_DONE</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nBit 20\nBit 20\nBit 21\nBit 21\nBit 22\nBit 22\nBit 23\nBit 23\nBit 24\nBit 24\nBit 25\nBit 25\nBit 26\nBit 26\nBit 27\nBit 27\nBit 28\nBit 28\nBit 29\nBit 29\nBit 30\nBit 30\nBit 31\nBit 31\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 12\nBit 12\nBit 13\nBit 13\nBit 14\nBit 14\nBit 15\nBit 15\nBit 16\nBit 16\nBit 17\nBit 17\nBit 18\nBit 18\nBit 19\nBit 19\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>EP0_IN</code> reader -\nField <code>EP0_IN</code> writer -\nField <code>EP0_OUT</code> reader -\nField <code>EP0_OUT</code> writer -\nDevice: this bit must be set in conjunction with the <code>STALL</code> …\nRegister <code>EP_STALL_ARM</code> reader\nRegister <code>EP_STALL_ARM</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>EP0_IN</code> reader -\nField <code>EP0_IN</code> writer -\nField <code>EP0_OUT</code> reader -\nField <code>EP0_OUT</code> writer -\nField <code>EP10_IN</code> reader -\nField <code>EP10_IN</code> writer -\nField <code>EP10_OUT</code> reader -\nField <code>EP10_OUT</code> writer -\nField <code>EP11_IN</code> reader -\nField <code>EP11_IN</code> writer -\nField <code>EP11_OUT</code> reader -\nField <code>EP11_OUT</code> writer -\nField <code>EP12_IN</code> reader -\nField <code>EP12_IN</code> writer -\nField <code>EP12_OUT</code> reader -\nField <code>EP12_OUT</code> writer -\nField <code>EP13_IN</code> reader -\nField <code>EP13_IN</code> writer -\nField <code>EP13_OUT</code> reader -\nField <code>EP13_OUT</code> writer -\nField <code>EP14_IN</code> reader -\nField <code>EP14_IN</code> writer -\nField <code>EP14_OUT</code> reader -\nField <code>EP14_OUT</code> writer -\nField <code>EP15_IN</code> reader -\nField <code>EP15_IN</code> writer -\nField <code>EP15_OUT</code> reader -\nField <code>EP15_OUT</code> writer -\nField <code>EP1_IN</code> reader -\nField <code>EP1_IN</code> writer -\nField <code>EP1_OUT</code> reader -\nField <code>EP1_OUT</code> writer -\nField <code>EP2_IN</code> reader -\nField <code>EP2_IN</code> writer -\nField <code>EP2_OUT</code> reader -\nField <code>EP2_OUT</code> writer -\nField <code>EP3_IN</code> reader -\nField <code>EP3_IN</code> writer -\nField <code>EP3_OUT</code> reader -\nField <code>EP3_OUT</code> writer -\nField <code>EP4_IN</code> reader -\nField <code>EP4_IN</code> writer -\nField <code>EP4_OUT</code> reader -\nField <code>EP4_OUT</code> writer -\nField <code>EP5_IN</code> reader -\nField <code>EP5_IN</code> writer -\nField <code>EP5_OUT</code> reader -\nField <code>EP5_OUT</code> writer -\nField <code>EP6_IN</code> reader -\nField <code>EP6_IN</code> writer -\nField <code>EP6_OUT</code> reader -\nField <code>EP6_OUT</code> writer -\nField <code>EP7_IN</code> reader -\nField <code>EP7_IN</code> writer -\nField <code>EP7_OUT</code> reader -\nField <code>EP7_OUT</code> writer -\nField <code>EP8_IN</code> reader -\nField <code>EP8_IN</code> writer -\nField <code>EP8_OUT</code> reader -\nField <code>EP8_OUT</code> writer -\nField <code>EP9_IN</code> reader -\nField <code>EP9_IN</code> writer -\nField <code>EP9_OUT</code> reader -\nField <code>EP9_OUT</code> writer -\nDevice: bits are set when the <code>IRQ_ON_NAK</code> or <code>IRQ_ON_STALL</code> …\nRegister <code>EP_STATUS_STALL_NAK</code> reader\nRegister <code>EP_STATUS_STALL_NAK</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nBit 20\nBit 20\nBit 21\nBit 21\nBit 22\nBit 22\nBit 23\nBit 23\nBit 24\nBit 24\nBit 25\nBit 25\nBit 26\nBit 26\nBit 27\nBit 27\nBit 28\nBit 28\nBit 29\nBit 29\nBit 30\nBit 30\nBit 31\nBit 31\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 12\nBit 12\nBit 13\nBit 13\nBit 14\nBit 14\nBit 15\nBit 15\nBit 16\nBit 16\nBit 17\nBit 17\nBit 18\nBit 18\nBit 19\nBit 19\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ADDRESS</code> reader - Device address\nField <code>ADDRESS</code> writer - Device address\nField <code>ENDPOINT</code> reader - Endpoint number of the interrupt …\nField <code>ENDPOINT</code> writer - Endpoint number of the interrupt …\nInterrupt endpoints. Only valid in HOST mode.\nField <code>INTEP_DIR</code> reader - Direction of the interrupt …\nField <code>INTEP_DIR</code> writer - Direction of the interrupt …\nField <code>INTEP_PREAMBLE</code> reader - Interrupt EP requires …\nField <code>INTEP_PREAMBLE</code> writer - Interrupt EP requires …\nRegister <code>HOST_ADDR_ENDP%s</code> reader\nRegister <code>HOST_ADDR_ENDP%s</code> writer\nBits 0:6 - Device address\nBits 0:6 - Device address\nWrites raw bits to the register.\nBits 16:19 - Endpoint number of the interrupt endpoint\nBits 16:19 - Endpoint number of the interrupt endpoint\nReturns the argument unchanged.\nBit 25 - Direction of the interrupt endpoint. In=0, Out=1\nBit 25 - Direction of the interrupt endpoint. In=0, Out=1\nBit 26 - Interrupt EP requires preamble (is a low speed …\nBit 26 - Interrupt EP requires preamble (is a low speed …\nCalls <code>U::from(self)</code>.\nField <code>INT_EP_ACTIVE</code> reader - Host: Enable interrupt …\nField <code>INT_EP_ACTIVE</code> writer - Host: Enable interrupt …\ninterrupt endpoint control register\nRegister <code>INT_EP_CTRL</code> reader\nRegister <code>INT_EP_CTRL</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 1:15 - Host: Enable interrupt endpoint 1 -&gt; 15\nBits 1:15 - Host: Enable interrupt endpoint 1 -&gt; 15\nCalls <code>U::from(self)</code>.\nField <code>ABORT_DONE</code> reader - Raised when any bit in …\nField <code>ABORT_DONE</code> writer - Raised when any bit in …\nField <code>BUFF_STATUS</code> reader - Raised when any bit in …\nField <code>BUFF_STATUS</code> writer - Raised when any bit in …\nField <code>BUS_RESET</code> reader - Source: SIE_STATUS.BUS_RESET\nField <code>BUS_RESET</code> writer - Source: SIE_STATUS.BUS_RESET\nField <code>DEV_CONN_DIS</code> reader - Set when the device connection …\nField <code>DEV_CONN_DIS</code> writer - Set when the device connection …\nField <code>DEV_RESUME_FROM_HOST</code> reader - Set when the device …\nField <code>DEV_RESUME_FROM_HOST</code> writer - Set when the device …\nField <code>DEV_SOF</code> reader - Set every time the device receives …\nField <code>DEV_SOF</code> writer - Set every time the device receives …\nField <code>DEV_SUSPEND</code> reader - Set when the device suspend …\nField <code>DEV_SUSPEND</code> writer - Set when the device suspend …\nField <code>EP_STALL_NAK</code> reader - Raised when any bit in …\nField <code>EP_STALL_NAK</code> writer - Raised when any bit in …\nField <code>ERROR_BIT_STUFF</code> reader - Source: …\nField <code>ERROR_BIT_STUFF</code> writer - Source: …\nField <code>ERROR_CRC</code> reader - Source: SIE_STATUS.CRC_ERROR\nField <code>ERROR_CRC</code> writer - Source: SIE_STATUS.CRC_ERROR\nField <code>ERROR_DATA_SEQ</code> reader - Source: …\nField <code>ERROR_DATA_SEQ</code> writer - Source: …\nField <code>ERROR_RX_OVERFLOW</code> reader - Source: …\nField <code>ERROR_RX_OVERFLOW</code> writer - Source: …\nField <code>ERROR_RX_TIMEOUT</code> reader - Source: …\nField <code>ERROR_RX_TIMEOUT</code> writer - Source: …\nField <code>HOST_CONN_DIS</code> reader - Host: raised when a device is …\nField <code>HOST_CONN_DIS</code> writer - Host: raised when a device is …\nField <code>HOST_RESUME</code> reader - Host: raised when a device …\nField <code>HOST_RESUME</code> writer - Host: raised when a device …\nField <code>HOST_SOF</code> reader - Host: raised every time the host …\nField <code>HOST_SOF</code> writer - Host: raised every time the host …\nInterrupt Enable\nRegister <code>INTE</code> reader\nField <code>SETUP_REQ</code> reader - Device. Source: …\nField <code>SETUP_REQ</code> writer - Device. Source: …\nField <code>STALL</code> reader - Source: SIE_STATUS.STALL_REC\nField <code>STALL</code> writer - Source: SIE_STATUS.STALL_REC\nField <code>TRANS_COMPLETE</code> reader - Raised every time …\nField <code>TRANS_COMPLETE</code> writer - Raised every time …\nField <code>VBUS_DETECT</code> reader - Source: SIE_STATUS.VBUS_DETECTED\nField <code>VBUS_DETECT</code> writer - Source: SIE_STATUS.VBUS_DETECTED\nRegister <code>INTE</code> writer\nBit 18 - Raised when any bit in ABORT_DONE is set. Clear …\nBit 18 - Raised when any bit in ABORT_DONE is set. Clear …\nWrites raw bits to the register.\nBit 4 - Raised when any bit in BUFF_STATUS is set. Clear …\nBit 4 - Raised when any bit in BUFF_STATUS is set. Clear …\nBit 12 - Source: SIE_STATUS.BUS_RESET\nBit 12 - Source: SIE_STATUS.BUS_RESET\nBit 13 - Set when the device connection state changes. …\nBit 13 - Set when the device connection state changes. …\nBit 15 - Set when the device receives a resume from the …\nBit 15 - Set when the device receives a resume from the …\nBit 17 - Set every time the device receives a SOF (Start …\nBit 17 - Set every time the device receives a SOF (Start …\nBit 14 - Set when the device suspend state changes. …\nBit 14 - Set when the device suspend state changes. …\nBit 19 - Raised when any bit in EP_STATUS_STALL_NAK is …\nBit 19 - Raised when any bit in EP_STATUS_STALL_NAK is …\nBit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR\nBit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR\nBit 9 - Source: SIE_STATUS.CRC_ERROR\nBit 9 - Source: SIE_STATUS.CRC_ERROR\nBit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR\nBit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR\nBit 7 - Source: SIE_STATUS.RX_OVERFLOW\nBit 7 - Source: SIE_STATUS.RX_OVERFLOW\nBit 6 - Source: SIE_STATUS.RX_TIMEOUT\nBit 6 - Source: SIE_STATUS.RX_TIMEOUT\nReturns the argument unchanged.\nBit 0 - Host: raised when a device is connected or …\nBit 0 - Host: raised when a device is connected or …\nBit 1 - Host: raised when a device wakes up the host. …\nBit 1 - Host: raised when a device wakes up the host. …\nBit 2 - Host: raised every time the host sends a SOF …\nBit 2 - Host: raised every time the host sends a SOF …\nCalls <code>U::from(self)</code>.\nBit 16 - Device. Source: SIE_STATUS.SETUP_REC\nBit 16 - Device. Source: SIE_STATUS.SETUP_REC\nBit 10 - Source: SIE_STATUS.STALL_REC\nBit 10 - Source: SIE_STATUS.STALL_REC\nBit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is …\nBit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is …\nBit 11 - Source: SIE_STATUS.VBUS_DETECTED\nBit 11 - Source: SIE_STATUS.VBUS_DETECTED\nField <code>ABORT_DONE</code> reader - Raised when any bit in …\nField <code>ABORT_DONE</code> writer - Raised when any bit in …\nField <code>BUFF_STATUS</code> reader - Raised when any bit in …\nField <code>BUFF_STATUS</code> writer - Raised when any bit in …\nField <code>BUS_RESET</code> reader - Source: SIE_STATUS.BUS_RESET\nField <code>BUS_RESET</code> writer - Source: SIE_STATUS.BUS_RESET\nField <code>DEV_CONN_DIS</code> reader - Set when the device connection …\nField <code>DEV_CONN_DIS</code> writer - Set when the device connection …\nField <code>DEV_RESUME_FROM_HOST</code> reader - Set when the device …\nField <code>DEV_RESUME_FROM_HOST</code> writer - Set when the device …\nField <code>DEV_SOF</code> reader - Set every time the device receives …\nField <code>DEV_SOF</code> writer - Set every time the device receives …\nField <code>DEV_SUSPEND</code> reader - Set when the device suspend …\nField <code>DEV_SUSPEND</code> writer - Set when the device suspend …\nField <code>EP_STALL_NAK</code> reader - Raised when any bit in …\nField <code>EP_STALL_NAK</code> writer - Raised when any bit in …\nField <code>ERROR_BIT_STUFF</code> reader - Source: …\nField <code>ERROR_BIT_STUFF</code> writer - Source: …\nField <code>ERROR_CRC</code> reader - Source: SIE_STATUS.CRC_ERROR\nField <code>ERROR_CRC</code> writer - Source: SIE_STATUS.CRC_ERROR\nField <code>ERROR_DATA_SEQ</code> reader - Source: …\nField <code>ERROR_DATA_SEQ</code> writer - Source: …\nField <code>ERROR_RX_OVERFLOW</code> reader - Source: …\nField <code>ERROR_RX_OVERFLOW</code> writer - Source: …\nField <code>ERROR_RX_TIMEOUT</code> reader - Source: …\nField <code>ERROR_RX_TIMEOUT</code> writer - Source: …\nField <code>HOST_CONN_DIS</code> reader - Host: raised when a device is …\nField <code>HOST_CONN_DIS</code> writer - Host: raised when a device is …\nField <code>HOST_RESUME</code> reader - Host: raised when a device …\nField <code>HOST_RESUME</code> writer - Host: raised when a device …\nField <code>HOST_SOF</code> reader - Host: raised every time the host …\nField <code>HOST_SOF</code> writer - Host: raised every time the host …\nInterrupt Force\nRegister <code>INTF</code> reader\nField <code>SETUP_REQ</code> reader - Device. Source: …\nField <code>SETUP_REQ</code> writer - Device. Source: …\nField <code>STALL</code> reader - Source: SIE_STATUS.STALL_REC\nField <code>STALL</code> writer - Source: SIE_STATUS.STALL_REC\nField <code>TRANS_COMPLETE</code> reader - Raised every time …\nField <code>TRANS_COMPLETE</code> writer - Raised every time …\nField <code>VBUS_DETECT</code> reader - Source: SIE_STATUS.VBUS_DETECTED\nField <code>VBUS_DETECT</code> writer - Source: SIE_STATUS.VBUS_DETECTED\nRegister <code>INTF</code> writer\nBit 18 - Raised when any bit in ABORT_DONE is set. Clear …\nBit 18 - Raised when any bit in ABORT_DONE is set. Clear …\nWrites raw bits to the register.\nBit 4 - Raised when any bit in BUFF_STATUS is set. Clear …\nBit 4 - Raised when any bit in BUFF_STATUS is set. Clear …\nBit 12 - Source: SIE_STATUS.BUS_RESET\nBit 12 - Source: SIE_STATUS.BUS_RESET\nBit 13 - Set when the device connection state changes. …\nBit 13 - Set when the device connection state changes. …\nBit 15 - Set when the device receives a resume from the …\nBit 15 - Set when the device receives a resume from the …\nBit 17 - Set every time the device receives a SOF (Start …\nBit 17 - Set every time the device receives a SOF (Start …\nBit 14 - Set when the device suspend state changes. …\nBit 14 - Set when the device suspend state changes. …\nBit 19 - Raised when any bit in EP_STATUS_STALL_NAK is …\nBit 19 - Raised when any bit in EP_STATUS_STALL_NAK is …\nBit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR\nBit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR\nBit 9 - Source: SIE_STATUS.CRC_ERROR\nBit 9 - Source: SIE_STATUS.CRC_ERROR\nBit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR\nBit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR\nBit 7 - Source: SIE_STATUS.RX_OVERFLOW\nBit 7 - Source: SIE_STATUS.RX_OVERFLOW\nBit 6 - Source: SIE_STATUS.RX_TIMEOUT\nBit 6 - Source: SIE_STATUS.RX_TIMEOUT\nReturns the argument unchanged.\nBit 0 - Host: raised when a device is connected or …\nBit 0 - Host: raised when a device is connected or …\nBit 1 - Host: raised when a device wakes up the host. …\nBit 1 - Host: raised when a device wakes up the host. …\nBit 2 - Host: raised every time the host sends a SOF …\nBit 2 - Host: raised every time the host sends a SOF …\nCalls <code>U::from(self)</code>.\nBit 16 - Device. Source: SIE_STATUS.SETUP_REC\nBit 16 - Device. Source: SIE_STATUS.SETUP_REC\nBit 10 - Source: SIE_STATUS.STALL_REC\nBit 10 - Source: SIE_STATUS.STALL_REC\nBit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is …\nBit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is …\nBit 11 - Source: SIE_STATUS.VBUS_DETECTED\nBit 11 - Source: SIE_STATUS.VBUS_DETECTED\nField <code>ABORT_DONE</code> reader - Raised when any bit in …\nField <code>BUFF_STATUS</code> reader - Raised when any bit in …\nField <code>BUS_RESET</code> reader - Source: SIE_STATUS.BUS_RESET\nField <code>DEV_CONN_DIS</code> reader - Set when the device connection …\nField <code>DEV_RESUME_FROM_HOST</code> reader - Set when the device …\nField <code>DEV_SOF</code> reader - Set every time the device receives …\nField <code>DEV_SUSPEND</code> reader - Set when the device suspend …\nField <code>EP_STALL_NAK</code> reader - Raised when any bit in …\nField <code>ERROR_BIT_STUFF</code> reader - Source: …\nField <code>ERROR_CRC</code> reader - Source: SIE_STATUS.CRC_ERROR\nField <code>ERROR_DATA_SEQ</code> reader - Source: …\nField <code>ERROR_RX_OVERFLOW</code> reader - Source: …\nField <code>ERROR_RX_TIMEOUT</code> reader - Source: …\nField <code>HOST_CONN_DIS</code> reader - Host: raised when a device is …\nField <code>HOST_RESUME</code> reader - Host: raised when a device …\nField <code>HOST_SOF</code> reader - Host: raised every time the host …\nRaw Interrupts\nRegister <code>INTR</code> reader\nField <code>SETUP_REQ</code> reader - Device. Source: …\nField <code>STALL</code> reader - Source: SIE_STATUS.STALL_REC\nField <code>TRANS_COMPLETE</code> reader - Raised every time …\nField <code>VBUS_DETECT</code> reader - Source: SIE_STATUS.VBUS_DETECTED\nBit 18 - Raised when any bit in ABORT_DONE is set. Clear …\nBit 4 - Raised when any bit in BUFF_STATUS is set. Clear …\nBit 12 - Source: SIE_STATUS.BUS_RESET\nBit 13 - Set when the device connection state changes. …\nBit 15 - Set when the device receives a resume from the …\nBit 17 - Set every time the device receives a SOF (Start …\nBit 14 - Set when the device suspend state changes. …\nBit 19 - Raised when any bit in EP_STATUS_STALL_NAK is …\nBit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR\nBit 9 - Source: SIE_STATUS.CRC_ERROR\nBit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR\nBit 7 - Source: SIE_STATUS.RX_OVERFLOW\nBit 6 - Source: SIE_STATUS.RX_TIMEOUT\nReturns the argument unchanged.\nBit 0 - Host: raised when a device is connected or …\nBit 1 - Host: raised when a device wakes up the host. …\nBit 2 - Host: raised every time the host sends a SOF …\nCalls <code>U::from(self)</code>.\nBit 16 - Device. Source: SIE_STATUS.SETUP_REC\nBit 10 - Source: SIE_STATUS.STALL_REC\nBit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is …\nBit 11 - Source: SIE_STATUS.VBUS_DETECTED\nField <code>ABORT_DONE</code> reader - Raised when any bit in …\nField <code>BUFF_STATUS</code> reader - Raised when any bit in …\nField <code>BUS_RESET</code> reader - Source: SIE_STATUS.BUS_RESET\nField <code>DEV_CONN_DIS</code> reader - Set when the device connection …\nField <code>DEV_RESUME_FROM_HOST</code> reader - Set when the device …\nField <code>DEV_SOF</code> reader - Set every time the device receives …\nField <code>DEV_SUSPEND</code> reader - Set when the device suspend …\nField <code>EP_STALL_NAK</code> reader - Raised when any bit in …\nField <code>ERROR_BIT_STUFF</code> reader - Source: …\nField <code>ERROR_CRC</code> reader - Source: SIE_STATUS.CRC_ERROR\nField <code>ERROR_DATA_SEQ</code> reader - Source: …\nField <code>ERROR_RX_OVERFLOW</code> reader - Source: …\nField <code>ERROR_RX_TIMEOUT</code> reader - Source: …\nField <code>HOST_CONN_DIS</code> reader - Host: raised when a device is …\nField <code>HOST_RESUME</code> reader - Host: raised when a device …\nField <code>HOST_SOF</code> reader - Host: raised every time the host …\nInterrupt status after masking &amp; forcing\nRegister <code>INTS</code> reader\nField <code>SETUP_REQ</code> reader - Device. Source: …\nField <code>STALL</code> reader - Source: SIE_STATUS.STALL_REC\nField <code>TRANS_COMPLETE</code> reader - Raised every time …\nField <code>VBUS_DETECT</code> reader - Source: SIE_STATUS.VBUS_DETECTED\nBit 18 - Raised when any bit in ABORT_DONE is set. Clear …\nBit 4 - Raised when any bit in BUFF_STATUS is set. Clear …\nBit 12 - Source: SIE_STATUS.BUS_RESET\nBit 13 - Set when the device connection state changes. …\nBit 15 - Set when the device receives a resume from the …\nBit 17 - Set every time the device receives a SOF (Start …\nBit 14 - Set when the device suspend state changes. …\nBit 19 - Raised when any bit in EP_STATUS_STALL_NAK is …\nBit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR\nBit 9 - Source: SIE_STATUS.CRC_ERROR\nBit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR\nBit 7 - Source: SIE_STATUS.RX_OVERFLOW\nBit 6 - Source: SIE_STATUS.RX_TIMEOUT\nReturns the argument unchanged.\nBit 0 - Host: raised when a device is connected or …\nBit 1 - Host: raised when a device wakes up the host. …\nBit 2 - Host: raised every time the host sends a SOF …\nCalls <code>U::from(self)</code>.\nBit 16 - Device. Source: SIE_STATUS.SETUP_REC\nBit 10 - Source: SIE_STATUS.STALL_REC\nBit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is …\nBit 11 - Source: SIE_STATUS.VBUS_DETECTED\nField <code>CONTROLLER_EN</code> reader - Enable controller\nField <code>CONTROLLER_EN</code> writer - Enable controller\nField <code>HOST_NDEVICE</code> reader - Device mode = 0, Host mode = 1\nField <code>HOST_NDEVICE</code> writer - Device mode = 0, Host mode = 1\nMain control register\nRegister <code>MAIN_CTRL</code> reader\nField <code>SIM_TIMING</code> reader - Reduced timings for simulation\nField <code>SIM_TIMING</code> writer - Reduced timings for simulation\nRegister <code>MAIN_CTRL</code> writer\nWrites raw bits to the register.\nBit 0 - Enable controller\nBit 0 - Enable controller\nReturns the argument unchanged.\nBit 1 - Device mode = 0, Host mode = 1\nBit 1 - Device mode = 0, Host mode = 1\nCalls <code>U::from(self)</code>.\nBit 31 - Reduced timings for simulation\nBit 31 - Reduced timings for simulation\nField <code>DELAY_FS</code> reader - NAK polling interval for a full …\nField <code>DELAY_FS</code> writer - NAK polling interval for a full …\nField <code>DELAY_LS</code> reader - NAK polling interval for a low …\nField <code>DELAY_LS</code> writer - NAK polling interval for a low …\nUsed by the host controller. Sets the wait time in …\nRegister <code>NAK_POLL</code> reader\nRegister <code>NAK_POLL</code> writer\nWrites raw bits to the register.\nBits 16:25 - NAK polling interval for a full speed device\nBits 16:25 - NAK polling interval for a full speed device\nBits 0:9 - NAK polling interval for a low speed device\nBits 0:9 - NAK polling interval for a low speed device\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>DIRECT_DM</code> reader - Direct control of DM\nField <code>DIRECT_DM</code> writer - Direct control of DM\nField <code>DIRECT_DP</code> reader - Direct control of DP\nField <code>DIRECT_DP</code> writer - Direct control of DP\nField <code>DIRECT_EN</code> reader - Direct bus drive enable\nField <code>DIRECT_EN</code> writer - Direct bus drive enable\nField <code>EP0_DOUBLE_BUF</code> reader - Device: EP0 single buffered …\nField <code>EP0_DOUBLE_BUF</code> writer - Device: EP0 single buffered …\nField <code>EP0_INT_1BUF</code> reader - Device: Set bit in BUFF_STATUS …\nField <code>EP0_INT_1BUF</code> writer - Device: Set bit in BUFF_STATUS …\nField <code>EP0_INT_2BUF</code> reader - Device: Set bit in BUFF_STATUS …\nField <code>EP0_INT_2BUF</code> writer - Device: Set bit in BUFF_STATUS …\nField <code>EP0_INT_NAK</code> reader - Device: Set bit in …\nField <code>EP0_INT_NAK</code> writer - Device: Set bit in …\nField <code>EP0_INT_STALL</code> reader - Device: Set bit in …\nField <code>EP0_INT_STALL</code> writer - Device: Set bit in …\nField <code>KEEP_ALIVE_EN</code> reader - Host: Enable keep alive …\nField <code>KEEP_ALIVE_EN</code> writer - Host: Enable keep alive …\nField <code>PREAMBLE_EN</code> reader - Host: Preable enable for LS …\nField <code>PREAMBLE_EN</code> writer - Host: Preable enable for LS …\nField <code>PULLDOWN_EN</code> reader - Host: Enable pull down resistors\nField <code>PULLDOWN_EN</code> writer - Host: Enable pull down resistors\nField <code>PULLUP_EN</code> reader - Device: Enable pull up resistor\nField <code>PULLUP_EN</code> writer - Device: Enable pull up resistor\nRegister <code>SIE_CTRL</code> reader\nField <code>RECEIVE_DATA</code> reader - Host: Receive transaction (IN …\nField <code>RECEIVE_DATA</code> writer - Host: Receive transaction (IN …\nField <code>RESET_BUS</code> reader - Host: Reset bus\nField <code>RESET_BUS</code> writer - Host: Reset bus\nField <code>RESUME</code> reader - Device: Remote wakeup. Device can …\nField <code>RESUME</code> writer - Device: Remote wakeup. Device can …\nField <code>RPU_OPT</code> reader - Device: Pull-up strength (0=1K2, …\nField <code>RPU_OPT</code> writer - Device: Pull-up strength (0=1K2, …\nField <code>SEND_DATA</code> reader - Host: Send transaction (OUT from …\nField <code>SEND_DATA</code> writer - Host: Send transaction (OUT from …\nField <code>SEND_SETUP</code> reader - Host: Send Setup packet\nField <code>SEND_SETUP</code> writer - Host: Send Setup packet\nSIE control register\nField <code>SOF_EN</code> reader - Host: Enable SOF generation (for …\nField <code>SOF_EN</code> writer - Host: Enable SOF generation (for …\nField <code>SOF_SYNC</code> reader - Host: Delay packet(s) until after …\nField <code>SOF_SYNC</code> writer - Host: Delay packet(s) until after …\nField <code>START_TRANS</code> reader - Host: Start transaction\nField <code>START_TRANS</code> writer - Host: Start transaction\nField <code>STOP_TRANS</code> reader - Host: Stop transaction\nField <code>STOP_TRANS</code> writer - Host: Stop transaction\nField <code>TRANSCEIVER_PD</code> reader - Power down bus transceiver\nField <code>TRANSCEIVER_PD</code> writer - Power down bus transceiver\nField <code>VBUS_EN</code> reader - Host: Enable VBUS\nField <code>VBUS_EN</code> writer - Host: Enable VBUS\nRegister <code>SIE_CTRL</code> writer\nWrites raw bits to the register.\nBit 24 - Direct control of DM\nBit 24 - Direct control of DM\nBit 25 - Direct control of DP\nBit 25 - Direct control of DP\nBit 26 - Direct bus drive enable\nBit 26 - Direct bus drive enable\nBit 30 - Device: EP0 single buffered = 0, double buffered …\nBit 30 - Device: EP0 single buffered = 0, double buffered …\nBit 29 - Device: Set bit in BUFF_STATUS for every buffer …\nBit 29 - Device: Set bit in BUFF_STATUS for every buffer …\nBit 28 - Device: Set bit in BUFF_STATUS for every 2 …\nBit 28 - Device: Set bit in BUFF_STATUS for every 2 …\nBit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 …\nBit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 …\nBit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 …\nBit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 10 - Host: Enable keep alive packet (for low speed bus)\nBit 10 - Host: Enable keep alive packet (for low speed bus)\nBit 6 - Host: Preable enable for LS device on FS hub\nBit 6 - Host: Preable enable for LS device on FS hub\nBit 15 - Host: Enable pull down resistors\nBit 15 - Host: Enable pull down resistors\nBit 16 - Device: Enable pull up resistor\nBit 16 - Device: Enable pull up resistor\nBit 3 - Host: Receive transaction (IN to host)\nBit 3 - Host: Receive transaction (IN to host)\nBit 13 - Host: Reset bus\nBit 13 - Host: Reset bus\nBit 12 - Device: Remote wakeup. Device can initiate its …\nBit 12 - Device: Remote wakeup. Device can initiate its …\nBit 17 - Device: Pull-up strength (0=1K2, 1=2k3)\nBit 17 - Device: Pull-up strength (0=1K2, 1=2k3)\nBit 2 - Host: Send transaction (OUT from host)\nBit 2 - Host: Send transaction (OUT from host)\nBit 1 - Host: Send Setup packet\nBit 1 - Host: Send Setup packet\nBit 9 - Host: Enable SOF generation (for full speed bus)\nBit 9 - Host: Enable SOF generation (for full speed bus)\nBit 8 - Host: Delay packet(s) until after SOF\nBit 8 - Host: Delay packet(s) until after SOF\nBit 0 - Host: Start transaction\nBit 0 - Host: Start transaction\nBit 4 - Host: Stop transaction\nBit 4 - Host: Stop transaction\nBit 18 - Power down bus transceiver\nBit 18 - Power down bus transceiver\nBit 11 - Host: Enable VBUS\nBit 11 - Host: Enable VBUS\nField <code>ACK_REC</code> reader - ACK received. Raised by both host …\nField <code>ACK_REC</code> writer - ACK received. Raised by both host …\nField <code>BIT_STUFF_ERROR</code> reader - Bit Stuff Error. Raised by …\nField <code>BIT_STUFF_ERROR</code> writer - Bit Stuff Error. Raised by …\nField <code>BUS_RESET</code> reader - Device: bus reset received\nField <code>BUS_RESET</code> writer - Device: bus reset received\nField <code>CONNECTED</code> reader - Device: connected\nField <code>CONNECTED</code> writer - Device: connected\nField <code>CRC_ERROR</code> reader - CRC Error. Raised by the Serial …\nField <code>CRC_ERROR</code> writer - CRC Error. Raised by the Serial …\nField <code>DATA_SEQ_ERROR</code> reader - Data Sequence Error.\nField <code>DATA_SEQ_ERROR</code> writer - Data Sequence Error.\n1: J\n2: K\nUSB bus line state\nField <code>LINE_STATE</code> reader - USB bus line state\nField <code>NAK_REC</code> reader - Host: NAK received\nField <code>NAK_REC</code> writer - Host: NAK received\nRegister <code>SIE_STATUS</code> reader\nField <code>RESUME</code> reader - Host: Device has initiated a remote …\nField <code>RESUME</code> writer - Host: Device has initiated a remote …\nField <code>RX_OVERFLOW</code> reader - RX overflow is raised by the …\nField <code>RX_OVERFLOW</code> writer - RX overflow is raised by the …\nField <code>RX_TIMEOUT</code> reader - RX timeout is raised by both the …\nField <code>RX_TIMEOUT</code> writer - RX timeout is raised by both the …\n0: SE0\n3: SE1\nField <code>SETUP_REC</code> reader - Device: Setup packet received\nField <code>SETUP_REC</code> writer - Device: Setup packet received\nSIE status register\nField <code>SPEED</code> reader - Host: device speed. Disconnected = …\nField <code>SPEED</code> writer - Host: device speed. Disconnected = …\nField <code>STALL_REC</code> reader - Host: STALL received\nField <code>STALL_REC</code> writer - Host: STALL received\nField <code>SUSPENDED</code> reader - Bus in suspended state. Valid for …\nField <code>SUSPENDED</code> writer - Bus in suspended state. Valid for …\nField <code>TRANS_COMPLETE</code> reader - Transaction complete.\nField <code>TRANS_COMPLETE</code> writer - Transaction complete.\nField <code>VBUS_DETECTED</code> reader - Device: VBUS Detected\nField <code>VBUS_OVER_CURR</code> reader - VBUS over current detected\nRegister <code>SIE_STATUS</code> writer\nBit 30 - ACK received. Raised by both host and device.\nBit 30 - ACK received. Raised by both host and device.\nBit 25 - Bit Stuff Error. Raised by the Serial RX engine.\nBit 25 - Bit Stuff Error. Raised by the Serial RX engine.\nWrites raw bits to the register.\nBit 19 - Device: bus reset received\nBit 19 - Device: bus reset received\nBit 16 - Device: connected\nBit 16 - Device: connected\nBit 24 - CRC Error. Raised by the Serial RX engine.\nBit 24 - CRC Error. Raised by the Serial RX engine.\nBit 31 - Data Sequence Error.\nBit 31 - Data Sequence Error.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nJ\nK\nSE0\nSE1\nBits 2:3 - USB bus line state\nBit 28 - Host: NAK received\nBit 28 - Host: NAK received\nBit 11 - Host: Device has initiated a remote resume. …\nBit 11 - Host: Device has initiated a remote resume. …\nBit 26 - RX overflow is raised by the Serial RX engine if …\nBit 26 - RX overflow is raised by the Serial RX engine if …\nBit 27 - RX timeout is raised by both the host and device …\nBit 27 - RX timeout is raised by both the host and device …\nBit 17 - Device: Setup packet received\nBit 17 - Device: Setup packet received\nBits 8:9 - Host: device speed. Disconnected = 00, LS = 01, …\nBits 8:9 - Host: device speed. Disconnected = 00, LS = 01, …\nBit 29 - Host: STALL received\nBit 29 - Host: STALL received\nBit 4 - Bus in suspended state. Valid for device and host. …\nBit 4 - Bus in suspended state. Valid for device and host. …\nBit 18 - Transaction complete.\nBit 18 - Transaction complete.\nGet enumerated values variant\nBit 0 - Device: VBUS Detected\nBit 10 - VBUS over current detected\nField <code>COUNT</code> reader -\nRegister <code>SOF_RD</code> reader\nRead the last SOF (Start of Frame) frame number seen. In …\nBits 0:10\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>COUNT</code> writer -\nSet the SOF (Start of Frame) frame number in the host …\nRegister <code>SOF_WR</code> writer\nWrites raw bits to the register.\nBits 0:10\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>USB_MUXING</code> reader\nField <code>SOFTCON</code> reader -\nField <code>SOFTCON</code> writer -\nField <code>TO_DIGITAL_PAD</code> reader -\nField <code>TO_DIGITAL_PAD</code> writer -\nField <code>TO_EXTPHY</code> reader -\nField <code>TO_EXTPHY</code> writer -\nField <code>TO_PHY</code> reader -\nField <code>TO_PHY</code> writer -\nWhere to connect the USB controller. Should be to_phy by …\nRegister <code>USB_MUXING</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nField <code>OVERCURR_DETECT_EN</code> reader -\nField <code>OVERCURR_DETECT_EN</code> writer -\nField <code>OVERCURR_DETECT</code> reader -\nField <code>OVERCURR_DETECT</code> writer -\nRegister <code>USB_PWR</code> reader\nOverrides for the power signals in the event that the VBUS …\nField <code>VBUS_DETECT_OVERRIDE_EN</code> reader -\nField <code>VBUS_DETECT_OVERRIDE_EN</code> writer -\nField <code>VBUS_DETECT</code> reader -\nField <code>VBUS_DETECT</code> writer -\nField <code>VBUS_EN_OVERRIDE_EN</code> reader -\nField <code>VBUS_EN_OVERRIDE_EN</code> writer -\nField <code>VBUS_EN</code> reader -\nField <code>VBUS_EN</code> writer -\nRegister <code>USB_PWR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 4\nBit 4\nBit 5\nBit 5\nBit 2\nBit 2\nBit 3\nBit 3\nBit 0\nBit 0\nBit 1\nBit 1\nField <code>DM_OVCN</code> reader - DM overcurrent\nField <code>DM_OVV</code> reader - DM over voltage\nField <code>DM_PULLDN_EN</code> reader - DM pull down enable\nField <code>DM_PULLDN_EN</code> writer - DM pull down enable\nField <code>DM_PULLUP_EN</code> reader - DM pull up enable\nField <code>DM_PULLUP_EN</code> writer - DM pull up enable\nField <code>DM_PULLUP_HISEL</code> reader - Enable the second DM pull …\nField <code>DM_PULLUP_HISEL</code> writer - Enable the second DM pull …\nField <code>DP_OVCN</code> reader - DP overcurrent\nField <code>DP_OVV</code> reader - DP over voltage\nField <code>DP_PULLDN_EN</code> reader - DP pull down enable\nField <code>DP_PULLDN_EN</code> writer - DP pull down enable\nField <code>DP_PULLUP_EN</code> reader - DP pull up enable\nField <code>DP_PULLUP_EN</code> writer - DP pull up enable\nField <code>DP_PULLUP_HISEL</code> reader - Enable the second DP pull …\nField <code>DP_PULLUP_HISEL</code> writer - Enable the second DP pull …\nRegister <code>USBPHY_DIRECT</code> reader\nField <code>RX_DD</code> reader - Differential RX\nField <code>RX_DM</code> reader - DPM pin state\nField <code>RX_DP</code> reader - DPP pin state\nField <code>RX_PD</code> reader - RX power down override (if override …\nField <code>RX_PD</code> writer - RX power down override (if override …\nField <code>TX_DIFFMODE</code> reader - TX_DIFFMODE=0: Single ended mode\nField <code>TX_DIFFMODE</code> writer - TX_DIFFMODE=0: Single ended mode\nField <code>TX_DM_OE</code> reader - Output enable. If TX_DIFFMODE=1, …\nField <code>TX_DM_OE</code> writer - Output enable. If TX_DIFFMODE=1, …\nField <code>TX_DM</code> reader - Output data. TX_DIFFMODE=1, Ignored …\nField <code>TX_DM</code> writer - Output data. TX_DIFFMODE=1, Ignored …\nField <code>TX_DP_OE</code> reader - Output enable. If TX_DIFFMODE=1, …\nField <code>TX_DP_OE</code> writer - Output enable. If TX_DIFFMODE=1, …\nField <code>TX_DP</code> reader - Output data. If TX_DIFFMODE=1, Drives …\nField <code>TX_DP</code> writer - Output data. If TX_DIFFMODE=1, Drives …\nField <code>TX_FSSLEW</code> reader - TX_FSSLEW=0: Low speed slew rate …\nField <code>TX_FSSLEW</code> writer - TX_FSSLEW=0: Low speed slew rate …\nField <code>TX_PD</code> reader - TX power down override (if override …\nField <code>TX_PD</code> writer - TX power down override (if override …\nThis register allows for direct control of the USB phy. …\nRegister <code>USBPHY_DIRECT</code> writer\nWrites raw bits to the register.\nBit 20 - DM overcurrent\nBit 22 - DM over voltage\nBit 6 - DM pull down enable\nBit 6 - DM pull down enable\nBit 5 - DM pull up enable\nBit 5 - DM pull up enable\nBit 4 - Enable the second DM pull up resistor. 0 - Pull = …\nBit 4 - Enable the second DM pull up resistor. 0 - Pull = …\nBit 19 - DP overcurrent\nBit 21 - DP over voltage\nBit 2 - DP pull down enable\nBit 2 - DP pull down enable\nBit 1 - DP pull up enable\nBit 1 - DP pull up enable\nBit 0 - Enable the second DP pull up resistor. 0 - Pull = …\nBit 0 - Enable the second DP pull up resistor. 0 - Pull = …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 16 - Differential RX\nBit 18 - DPM pin state\nBit 17 - DPP pin state\nBit 12 - RX power down override (if override enable is …\nBit 12 - RX power down override (if override enable is …\nBit 15 - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: …\nBit 15 - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: …\nBit 11 - Output data. TX_DIFFMODE=1, Ignored …\nBit 11 - Output data. TX_DIFFMODE=1, Ignored …\nBit 9 - Output enable. If TX_DIFFMODE=1, Ignored. If …\nBit 9 - Output enable. If TX_DIFFMODE=1, Ignored. If …\nBit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM …\nBit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM …\nBit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM …\nBit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM …\nBit 14 - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: …\nBit 14 - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: …\nBit 13 - TX power down override (if override enable is …\nBit 13 - TX power down override (if override enable is …\nField <code>DM_PULLDN_EN_OVERRIDE_EN</code> reader -\nField <code>DM_PULLDN_EN_OVERRIDE_EN</code> writer -\nField <code>DM_PULLUP_HISEL_OVERRIDE_EN</code> reader -\nField <code>DM_PULLUP_HISEL_OVERRIDE_EN</code> writer -\nField <code>DM_PULLUP_OVERRIDE_EN</code> reader -\nField <code>DM_PULLUP_OVERRIDE_EN</code> writer -\nField <code>DP_PULLDN_EN_OVERRIDE_EN</code> reader -\nField <code>DP_PULLDN_EN_OVERRIDE_EN</code> writer -\nField <code>DP_PULLUP_EN_OVERRIDE_EN</code> reader -\nField <code>DP_PULLUP_EN_OVERRIDE_EN</code> writer -\nField <code>DP_PULLUP_HISEL_OVERRIDE_EN</code> reader -\nField <code>DP_PULLUP_HISEL_OVERRIDE_EN</code> writer -\nRegister <code>USBPHY_DIRECT_OVERRIDE</code> reader\nField <code>RX_PD_OVERRIDE_EN</code> reader -\nField <code>RX_PD_OVERRIDE_EN</code> writer -\nField <code>TX_DIFFMODE_OVERRIDE_EN</code> reader -\nField <code>TX_DIFFMODE_OVERRIDE_EN</code> writer -\nField <code>TX_DM_OE_OVERRIDE_EN</code> reader -\nField <code>TX_DM_OE_OVERRIDE_EN</code> writer -\nField <code>TX_DM_OVERRIDE_EN</code> reader -\nField <code>TX_DM_OVERRIDE_EN</code> writer -\nField <code>TX_DP_OE_OVERRIDE_EN</code> reader -\nField <code>TX_DP_OE_OVERRIDE_EN</code> writer -\nField <code>TX_DP_OVERRIDE_EN</code> reader -\nField <code>TX_DP_OVERRIDE_EN</code> writer -\nField <code>TX_FSSLEW_OVERRIDE_EN</code> reader -\nField <code>TX_FSSLEW_OVERRIDE_EN</code> writer -\nField <code>TX_PD_OVERRIDE_EN</code> reader -\nField <code>TX_PD_OVERRIDE_EN</code> writer -\nOverride enable for each control in usbphy_direct\nRegister <code>USBPHY_DIRECT_OVERRIDE</code> writer\nWrites raw bits to the register.\nBit 4\nBit 4\nBit 1\nBit 1\nBit 12\nBit 12\nBit 3\nBit 3\nBit 2\nBit 2\nBit 0\nBit 0\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 9\nBit 9\nBit 15\nBit 15\nBit 6\nBit 6\nBit 8\nBit 8\nBit 5\nBit 5\nBit 7\nBit 7\nBit 11\nBit 11\nBit 10\nBit 10\nField <code>DM_PULLDN_TRIM</code> reader - Value to drive to USB PHY DM …\nField <code>DM_PULLDN_TRIM</code> writer - Value to drive to USB PHY DM …\nField <code>DP_PULLDN_TRIM</code> reader - Value to drive to USB PHY DP …\nField <code>DP_PULLDN_TRIM</code> writer - Value to drive to USB PHY DP …\nRegister <code>USBPHY_TRIM</code> reader\nUsed to adjust trim values of USB phy pull down resistors.\nRegister <code>USBPHY_TRIM</code> writer\nWrites raw bits to the register.\nBits 8:12 - Value to drive to USB PHY DM pulldown resistor …\nBits 8:12 - Value to drive to USB PHY DM pulldown resistor …\nBits 0:4 - Value to drive to USB PHY DP pulldown resistor …\nBits 0:4 - Value to drive to USB PHY DP pulldown resistor …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBOD (rw) register accessor: brown-out detection control\nCHIP_RESET (rw) register accessor: Chip reset control and …\nRegister block\nVREG (rw) register accessor: Voltage regulator control and …\nbrown-out detection control\n0x04 - brown-out detection control\nChip reset control and status\n0x08 - Chip reset control and status\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nVoltage regulator control and status\n0x00 - Voltage regulator control and status\nbrown-out detection control\nField <code>EN</code> reader - enable 0=not enabled, 1=enabled\nField <code>EN</code> writer - enable 0=not enabled, 1=enabled\nRegister <code>BOD</code> reader\nField <code>VSEL</code> reader - threshold select 0000 - 0.473V 0001 - …\nField <code>VSEL</code> writer - threshold select 0000 - 0.473V 0001 - …\nRegister <code>BOD</code> writer\nWrites raw bits to the register.\nBit 0 - enable 0=not enabled, 1=enabled\nBit 0 - enable 0=not enabled, 1=enabled\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 4:7 - threshold select 0000 - 0.473V 0001 - 0.516V …\nBits 4:7 - threshold select 0000 - 0.473V 0001 - 0.516V …\nChip reset control and status\nField <code>HAD_POR</code> reader - Last reset was from the power-on …\nField <code>HAD_PSM_RESTART</code> reader - Last reset was from the …\nField <code>HAD_RUN</code> reader - Last reset was from the RUN pin\nField <code>PSM_RESTART_FLAG</code> reader - This is set by psm_restart …\nField <code>PSM_RESTART_FLAG</code> writer - This is set by psm_restart …\nRegister <code>CHIP_RESET</code> reader\nRegister <code>CHIP_RESET</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 8 - Last reset was from the power-on reset or …\nBit 20 - Last reset was from the debug port\nBit 16 - Last reset was from the RUN pin\nCalls <code>U::from(self)</code>.\nBit 24 - This is set by psm_restart from the debugger. Its …\nBit 24 - This is set by psm_restart from the debugger. Its …\nField <code>EN</code> reader - enable 0=not enabled, 1=enabled\nField <code>EN</code> writer - enable 0=not enabled, 1=enabled\nField <code>HIZ</code> reader - high impedance mode select 0=not in …\nField <code>HIZ</code> writer - high impedance mode select 0=not in …\nRegister <code>VREG</code> reader\nField <code>ROK</code> reader - regulation status 0=not in regulation, …\n5: 0.80V\n6: 0.85V\n7: 0.90V\n8: 0.95V\n9: 1.00V\n10: 1.05V\n11: 1.10V (default)\n12: 1.15V\n13: 1.20V\n14: 1.25V\n15: 1.30V\nVoltage regulator control and status\nOutput voltage select for on-chip voltage regulator.\nField <code>VSEL</code> reader - Output voltage select for on-chip …\nField <code>VSEL</code> writer - Output voltage select for on-chip …\nRegister <code>VREG</code> writer\nWrites raw bits to the register.\nBit 0 - enable 0=not enabled, 1=enabled\nBit 0 - enable 0=not enabled, 1=enabled\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 1 - high impedance mode select 0=not in high impedance …\nBit 1 - high impedance mode select 0=not in high impedance …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n0.80V\n0.85V\n0.90V\n0.95V\n1.00V\n1.05V\n1.10V (default)\n1.15V\n1.20V\n1.25V\n1.30V\nBit 12 - regulation status 0=not in regulation, 1=in …\nGet enumerated values variant\n0.80V\n0.85V\n0.90V\n0.95V\n1.00V\n1.05V\n1.10V (default)\n1.15V\n1.20V\n1.25V\n1.30V\nBits 4:7 - Output voltage select for on-chip voltage …\nBits 4:7 - Output voltage select for on-chip voltage …\nCTRL (rw) register accessor: Watchdog control The …\nLOAD (w) register accessor: Load the watchdog timer. The …\nREASON (r) register accessor: Logs the reason for the last …\nRegister block\nSCRATCH0 (rw) register accessor: Scratch register. …\nSCRATCH1 (rw) register accessor: Scratch register. …\nSCRATCH2 (rw) register accessor: Scratch register. …\nSCRATCH3 (rw) register accessor: Scratch register. …\nSCRATCH4 (rw) register accessor: Scratch register. …\nSCRATCH5 (rw) register accessor: Scratch register. …\nSCRATCH6 (rw) register accessor: Scratch register. …\nSCRATCH7 (rw) register accessor: Scratch register. …\nTICK (rw) register accessor: Controls the tick generator\nWatchdog control The rst_wdsel register determines which …\n0x00 - Watchdog control The rst_wdsel register determines …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nLoad the watchdog timer. The maximum setting is 0xffffff …\n0x04 - Load the watchdog timer. The maximum setting is …\nLogs the reason for the last reset. Both bits are zero for …\n0x08 - Logs the reason for the last reset. Both bits are …\nScratch register. Information persists through soft reset …\n0x0c - Scratch register. Information persists through soft …\nScratch register. Information persists through soft reset …\n0x10 - Scratch register. Information persists through soft …\nScratch register. Information persists through soft reset …\n0x14 - Scratch register. Information persists through soft …\nScratch register. Information persists through soft reset …\n0x18 - Scratch register. Information persists through soft …\nScratch register. Information persists through soft reset …\n0x1c - Scratch register. Information persists through soft …\nScratch register. Information persists through soft reset …\n0x20 - Scratch register. Information persists through soft …\nScratch register. Information persists through soft reset …\n0x24 - Scratch register. Information persists through soft …\nScratch register. Information persists through soft reset …\n0x28 - Scratch register. Information persists through soft …\nControls the tick generator\n0x2c - Controls the tick generator\nWatchdog control The rst_wdsel register determines which …\nField <code>ENABLE</code> reader - When not enabled the watchdog timer …\nField <code>ENABLE</code> writer - When not enabled the watchdog timer …\nField <code>PAUSE_DBG0</code> reader - Pause the watchdog timer when …\nField <code>PAUSE_DBG0</code> writer - Pause the watchdog timer when …\nField <code>PAUSE_DBG1</code> reader - Pause the watchdog timer when …\nField <code>PAUSE_DBG1</code> writer - Pause the watchdog timer when …\nField <code>PAUSE_JTAG</code> reader - Pause the watchdog timer when …\nField <code>PAUSE_JTAG</code> writer - Pause the watchdog timer when …\nRegister <code>CTRL</code> reader\nField <code>TIME</code> reader - Indicates the number of ticks / 2 (see …\nField <code>TRIGGER</code> reader - Trigger a watchdog reset\nField <code>TRIGGER</code> writer - Trigger a watchdog reset\nRegister <code>CTRL</code> writer\nWrites raw bits to the register.\nBit 30 - When not enabled the watchdog timer is paused\nBit 30 - When not enabled the watchdog timer is paused\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 25 - Pause the watchdog timer when processor 0 is in …\nBit 25 - Pause the watchdog timer when processor 0 is in …\nBit 26 - Pause the watchdog timer when processor 1 is in …\nBit 26 - Pause the watchdog timer when processor 1 is in …\nBit 24 - Pause the watchdog timer when JTAG is accessing …\nBit 24 - Pause the watchdog timer when JTAG is accessing …\nBits 0:23 - Indicates the number of ticks / 2 (see errata …\nBit 31 - Trigger a watchdog reset\nBit 31 - Trigger a watchdog reset\nLoad the watchdog timer. The maximum setting is 0xffffff …\nField <code>LOAD</code> writer -\nRegister <code>LOAD</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:23\nField <code>FORCE</code> reader -\nRegister <code>REASON</code> reader\nLogs the reason for the last reset. Both bits are zero for …\nField <code>TIMER</code> reader -\nBit 1\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0\nRegister <code>SCRATCH0</code> reader\nScratch register. Information persists through soft reset …\nRegister <code>SCRATCH0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SCRATCH1</code> reader\nScratch register. Information persists through soft reset …\nRegister <code>SCRATCH1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SCRATCH2</code> reader\nScratch register. Information persists through soft reset …\nRegister <code>SCRATCH2</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SCRATCH3</code> reader\nScratch register. Information persists through soft reset …\nRegister <code>SCRATCH3</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SCRATCH4</code> reader\nScratch register. Information persists through soft reset …\nRegister <code>SCRATCH4</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SCRATCH5</code> reader\nScratch register. Information persists through soft reset …\nRegister <code>SCRATCH5</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SCRATCH6</code> reader\nScratch register. Information persists through soft reset …\nRegister <code>SCRATCH6</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SCRATCH7</code> reader\nScratch register. Information persists through soft reset …\nRegister <code>SCRATCH7</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>COUNT</code> reader - Count down timer: the remaining …\nField <code>CYCLES</code> reader - Total number of clk_tick cycles …\nField <code>CYCLES</code> writer - Total number of clk_tick cycles …\nField <code>ENABLE</code> reader - start / stop tick generation\nField <code>ENABLE</code> writer - start / stop tick generation\nRegister <code>TICK</code> reader\nField <code>RUNNING</code> reader - Is the tick generator running?\nControls the tick generator\nRegister <code>TICK</code> writer\nWrites raw bits to the register.\nBits 11:19 - Count down timer: the remaining number …\nBits 0:8 - Total number of clk_tick cycles before the next …\nBits 0:8 - Total number of clk_tick cycles before the next …\nBit 9 - start / stop tick generation\nBit 9 - start / stop tick generation\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 10 - Is the tick generator running?\nCTRL (rw) register accessor: Cache control\nCTR_ACC (rw) register accessor: Cache Access counter A 32 …\nCTR_HIT (rw) register accessor: Cache Hit counter A 32 bit …\nFLUSH (rw) register accessor: Cache Flush control\nRegister block\nSTAT (r) register accessor: Cache Status\nSTREAM_ADDR (rw) register accessor: FIFO stream address\nSTREAM_CTR (rw) register accessor: FIFO stream control\nSTREAM_FIFO (r) register accessor: FIFO stream data …\nCache Access counter A 32 bit saturating counter that …\n0x10 - Cache Access counter A 32 bit saturating counter …\nCache Hit counter A 32 bit saturating counter that …\n0x0c - Cache Hit counter A 32 bit saturating counter that …\nCache control\n0x00 - Cache control\nCache Flush control\n0x04 - Cache Flush control\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCache Status\n0x08 - Cache Status\nFIFO stream address\n0x14 - FIFO stream address\nFIFO stream control\n0x18 - FIFO stream control\nFIFO stream data Streamed data is buffered here, for …\n0x1c - FIFO stream data Streamed data is buffered here, …\nCache Access counter A 32 bit saturating counter that …\nRegister <code>CTR_ACC</code> reader\nRegister <code>CTR_ACC</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCache Hit counter A 32 bit saturating counter that …\nRegister <code>CTR_HIT</code> reader\nRegister <code>CTR_HIT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCache control\nField <code>EN</code> reader - When 1, enable the cache. When the cache …\nField <code>EN</code> writer - When 1, enable the cache. When the cache …\nField <code>ERR_BADWRITE</code> reader - When 1, writes to any alias …\nField <code>ERR_BADWRITE</code> writer - When 1, writes to any alias …\nField <code>POWER_DOWN</code> reader - When 1, the cache memories are …\nField <code>POWER_DOWN</code> writer - When 1, the cache memories are …\nRegister <code>CTRL</code> reader\nRegister <code>CTRL</code> writer\nWrites raw bits to the register.\nBit 0 - When 1, enable the cache. When the cache is …\nBit 0 - When 1, enable the cache. When the cache is …\nBit 1 - When 1, writes to any alias other than 0x0 …\nBit 1 - When 1, writes to any alias other than 0x0 …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 3 - When 1, the cache memories are powered down. They …\nBit 3 - When 1, the cache memories are powered down. They …\nField <code>FLUSH</code> reader - Write 1 to flush the cache. This …\nCache Flush control\nField <code>FLUSH</code> writer - Write 1 to flush the cache. This …\nRegister <code>FLUSH</code> reader\nRegister <code>FLUSH</code> writer\nWrites raw bits to the register.\nBit 0 - Write 1 to flush the cache. This clears the tag …\nBit 0 - Write 1 to flush the cache. This clears the tag …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>FIFO_EMPTY</code> reader - When 1, indicates the XIP …\nField <code>FIFO_FULL</code> reader - When 1, indicates the XIP …\nField <code>FLUSH_READY</code> reader - Reads as 0 while a cache flush …\nRegister <code>STAT</code> reader\nCache Status\nBit 1 - When 1, indicates the XIP streaming FIFO is …\nBit 2 - When 1, indicates the XIP streaming FIFO is …\nBit 0 - Reads as 0 while a cache flush is in progress, and …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>STREAM_ADDR</code> reader\nField <code>STREAM_ADDR</code> reader - The address of the next word to …\nFIFO stream address\nField <code>STREAM_ADDR</code> writer - The address of the next word to …\nRegister <code>STREAM_ADDR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 2:31 - The address of the next word to be streamed …\nBits 2:31 - The address of the next word to be streamed …\nRegister <code>STREAM_CTR</code> reader\nField <code>STREAM_CTR</code> reader - Write a nonzero value to start a …\nFIFO stream control\nField <code>STREAM_CTR</code> writer - Write a nonzero value to start a …\nRegister <code>STREAM_CTR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:21 - Write a nonzero value to start a streaming …\nBits 0:21 - Write a nonzero value to start a streaming …\nRegister <code>STREAM_FIFO</code> reader\nFIFO stream data Streamed data is buffered here, for …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBAUDR (rw) register accessor: Baud rate\nCTRLR0 (rw) register accessor: Control register 0\nCTRLR1 (rw) register accessor: Master Control register 1\nDMACR (rw) register accessor: DMA control\nDMARDLR (rw) register accessor: DMA RX data level\nDMATDLR (rw) register accessor: DMA TX data level\nDR0 (rw) register accessor: Data Register 0 (of 36)\nICR (r) register accessor: Interrupt clear\nIDR (r) register accessor: Identification register\nIMR (rw) register accessor: Interrupt mask\nISR (r) register accessor: Interrupt status\nMSTICR (r) register accessor: Multi-master interrupt clear\nMWCR (rw) register accessor: Microwire Control\nRISR (r) register accessor: Raw interrupt status\nRXFLR (r) register accessor: RX FIFO level\nRXFTLR (rw) register accessor: RX FIFO threshold level\nRXOICR (r) register accessor: RX FIFO overflow interrupt …\nRXUICR (r) register accessor: RX FIFO underflow interrupt …\nRX_SAMPLE_DLY (rw) register accessor: RX sample delay\nRegister block\nSER (rw) register accessor: Slave enable\nSPI_CTRLR0 (rw) register accessor: SPI control\nSR (r) register accessor: Status register\nSSIENR (rw) register accessor: SSI Enable\nSSI_VERSION_ID (r) register accessor: Version ID\nTXD_DRIVE_EDGE (rw) register accessor: TX drive edge\nTXFLR (r) register accessor: TX FIFO level\nTXFTLR (rw) register accessor: TX FIFO threshold level\nTXOICR (r) register accessor: TX FIFO overflow interrupt …\nBaud rate\n0x14 - Baud rate\nControl register 0\n0x00 - Control register 0\nMaster Control register 1\n0x04 - Master Control register 1\nDMA control\n0x4c - DMA control\nDMA RX data level\n0x54 - DMA RX data level\nDMA TX data level\n0x50 - DMA TX data level\nData Register 0 (of 36)\n0x60 - Data Register 0 (of 36)\nReturns the argument unchanged.\nInterrupt clear\n0x48 - Interrupt clear\nIdentification register\n0x58 - Identification register\nInterrupt mask\n0x2c - Interrupt mask\nCalls <code>U::from(self)</code>.\nInterrupt status\n0x30 - Interrupt status\nMulti-master interrupt clear\n0x44 - Multi-master interrupt clear\nMicrowire Control\n0x0c - Microwire Control\nRaw interrupt status\n0x34 - Raw interrupt status\nRX sample delay\n0xf0 - RX sample delay\nRX FIFO level\n0x24 - RX FIFO level\nRX FIFO threshold level\n0x1c - RX FIFO threshold level\nRX FIFO overflow interrupt clear\n0x3c - RX FIFO overflow interrupt clear\nRX FIFO underflow interrupt clear\n0x40 - RX FIFO underflow interrupt clear\nSlave enable\n0x10 - Slave enable\nSPI control\n0xf4 - SPI control\nStatus register\n0x28 - Status register\nVersion ID\n0x5c - Version ID\nSSI Enable\n0x08 - SSI Enable\nTX drive edge\n0xf8 - TX drive edge\nTX FIFO level\n0x20 - TX FIFO level\nTX FIFO threshold level\n0x18 - TX FIFO threshold level\nTX FIFO overflow interrupt clear\n0x38 - TX FIFO overflow interrupt clear\nBaud rate\nRegister <code>BAUDR</code> reader\nField <code>SCKDV</code> reader - SSI clock divider\nField <code>SCKDV</code> writer - SSI clock divider\nRegister <code>BAUDR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15 - SSI clock divider\nBits 0:15 - SSI clock divider\nField <code>CFS</code> reader - Control frame size Value of n -&gt; n+1 …\nField <code>CFS</code> writer - Control frame size Value of n -&gt; n+1 …\nControl register 0\nField <code>DFS_32</code> reader - Data frame size in 32b transfer mode …\nField <code>DFS_32</code> writer - Data frame size in 32b transfer mode …\nField <code>DFS</code> reader - Data frame size\nField <code>DFS</code> writer - Data frame size\n1: Dual-SPI frame format; two bits per SCK, half-duplex\n3: EEPROM read mode (TX then RX; RX starts after control …\nField <code>FRF</code> reader - Frame format\nField <code>FRF</code> writer - Frame format\n2: Quad-SPI frame format; four bits per SCK, half-duplex\nRegister <code>CTRLR0</code> reader\n2: Receive only (not for FRF == 0, standard SPI mode)\nField <code>SCPH</code> reader - Serial clock phase\nField <code>SCPH</code> writer - Serial clock phase\nField <code>SCPOL</code> reader - Serial clock polarity\nField <code>SCPOL</code> writer - Serial clock polarity\nField <code>SLV_OE</code> reader - Slave output enable\nField <code>SLV_OE</code> writer - Slave output enable\nSPI frame format\nField <code>SPI_FRF</code> reader - SPI frame format\nField <code>SPI_FRF</code> writer - SPI frame format\nField <code>SRL</code> reader - Shift register loop (test mode)\nField <code>SRL</code> writer - Shift register loop (test mode)\nField <code>SSTE</code> reader - Slave select toggle enable\nField <code>SSTE</code> writer - Slave select toggle enable\n0: Standard 1-bit SPI frame format; 1 bit per SCK, …\nTransfer mode\nField <code>TMOD</code> reader - Transfer mode\nField <code>TMOD</code> writer - Transfer mode\n0: Both transmit and receive\n1: Transmit only (not for FRF == 0, standard SPI mode)\nRegister <code>CTRLR0</code> writer\nWrites raw bits to the register.\nBits 12:15 - Control frame size Value of n -&gt; n+1 clocks …\nBits 12:15 - Control frame size Value of n -&gt; n+1 clocks …\nBits 0:3 - Data frame size\nBits 0:3 - Data frame size\nBits 16:20 - Data frame size in 32b transfer mode Value of …\nBits 16:20 - Data frame size in 32b transfer mode Value of …\nDual-SPI frame format; two bits per SCK, half-duplex\nEEPROM read mode (TX then RX; RX starts after control data …\nBits 4:5 - Frame format\nBits 4:5 - Frame format\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nDual-SPI frame format; two bits per SCK, half-duplex\nEEPROM read mode (TX then RX; RX starts after control data …\nQuad-SPI frame format; four bits per SCK, half-duplex\nReceive only (not for FRF == 0, standard SPI mode)\nStandard 1-bit SPI frame format; 1 bit per SCK, full-duplex\nBoth transmit and receive\nTransmit only (not for FRF == 0, standard SPI mode)\nQuad-SPI frame format; four bits per SCK, half-duplex\nReceive only (not for FRF == 0, standard SPI mode)\nBit 6 - Serial clock phase\nBit 6 - Serial clock phase\nBit 7 - Serial clock polarity\nBit 7 - Serial clock polarity\nBit 10 - Slave output enable\nBit 10 - Slave output enable\nBits 21:22 - SPI frame format\nBits 21:22 - SPI frame format\nBit 11 - Shift register loop (test mode)\nBit 11 - Shift register loop (test mode)\nBit 24 - Slave select toggle enable\nBit 24 - Slave select toggle enable\nStandard 1-bit SPI frame format; 1 bit per SCK, full-duplex\nBits 8:9 - Transfer mode\nBits 8:9 - Transfer mode\nBoth transmit and receive\nTransmit only (not for FRF == 0, standard SPI mode)\nGet enumerated values variant\nGet enumerated values variant\nMaster Control register 1\nField <code>NDF</code> reader - Number of data frames\nField <code>NDF</code> writer - Number of data frames\nRegister <code>CTRLR1</code> reader\nRegister <code>CTRLR1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15 - Number of data frames\nBits 0:15 - Number of data frames\nDMA control\nRegister <code>DMACR</code> reader\nField <code>RDMAE</code> reader - Receive DMA enable\nField <code>RDMAE</code> writer - Receive DMA enable\nField <code>TDMAE</code> reader - Transmit DMA enable\nField <code>TDMAE</code> writer - Transmit DMA enable\nRegister <code>DMACR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Receive DMA enable\nBit 0 - Receive DMA enable\nBit 1 - Transmit DMA enable\nBit 1 - Transmit DMA enable\nDMA RX data level\nField <code>DMARDL</code> reader - Receive data watermark level …\nField <code>DMARDL</code> writer - Receive data watermark level …\nRegister <code>DMARDLR</code> reader\nRegister <code>DMARDLR</code> writer\nWrites raw bits to the register.\nBits 0:7 - Receive data watermark level (DMARDLR+1)\nBits 0:7 - Receive data watermark level (DMARDLR+1)\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDMA TX data level\nField <code>DMATDL</code> reader - Transmit data watermark level\nField <code>DMATDL</code> writer - Transmit data watermark level\nRegister <code>DMATDLR</code> reader\nRegister <code>DMATDLR</code> writer\nWrites raw bits to the register.\nBits 0:7 - Transmit data watermark level\nBits 0:7 - Transmit data watermark level\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nData Register 0 (of 36)\nField <code>DR</code> reader - First data register of 36\nField <code>DR</code> writer - First data register of 36\nRegister <code>DR0</code> reader\nRegister <code>DR0</code> writer\nWrites raw bits to the register.\nBits 0:31 - First data register of 36\nBits 0:31 - First data register of 36\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ICR</code> reader - Clear-on-read all active interrupts\nInterrupt clear\nRegister <code>ICR</code> reader\nReturns the argument unchanged.\nBit 0 - Clear-on-read all active interrupts\nCalls <code>U::from(self)</code>.\nField <code>IDCODE</code> reader - Peripheral dentification code\nIdentification register\nRegister <code>IDR</code> reader\nReturns the argument unchanged.\nBits 0:31 - Peripheral dentification code\nCalls <code>U::from(self)</code>.\nInterrupt mask\nField <code>MSTIM</code> reader - Multi-master contention interrupt mask\nField <code>MSTIM</code> writer - Multi-master contention interrupt mask\nRegister <code>IMR</code> reader\nField <code>RXFIM</code> reader - Receive FIFO full interrupt mask\nField <code>RXFIM</code> writer - Receive FIFO full interrupt mask\nField <code>RXOIM</code> reader - Receive FIFO overflow interrupt mask\nField <code>RXOIM</code> writer - Receive FIFO overflow interrupt mask\nField <code>RXUIM</code> reader - Receive FIFO underflow interrupt mask\nField <code>RXUIM</code> writer - Receive FIFO underflow interrupt mask\nField <code>TXEIM</code> reader - Transmit FIFO empty interrupt mask\nField <code>TXEIM</code> writer - Transmit FIFO empty interrupt mask\nField <code>TXOIM</code> reader - Transmit FIFO overflow interrupt mask\nField <code>TXOIM</code> writer - Transmit FIFO overflow interrupt mask\nRegister <code>IMR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 5 - Multi-master contention interrupt mask\nBit 5 - Multi-master contention interrupt mask\nBit 4 - Receive FIFO full interrupt mask\nBit 4 - Receive FIFO full interrupt mask\nBit 3 - Receive FIFO overflow interrupt mask\nBit 3 - Receive FIFO overflow interrupt mask\nBit 2 - Receive FIFO underflow interrupt mask\nBit 2 - Receive FIFO underflow interrupt mask\nBit 0 - Transmit FIFO empty interrupt mask\nBit 0 - Transmit FIFO empty interrupt mask\nBit 1 - Transmit FIFO overflow interrupt mask\nBit 1 - Transmit FIFO overflow interrupt mask\nInterrupt status\nField <code>MSTIS</code> reader - Multi-master contention interrupt …\nRegister <code>ISR</code> reader\nField <code>RXFIS</code> reader - Receive FIFO full interrupt status\nField <code>RXOIS</code> reader - Receive FIFO overflow interrupt status\nField <code>RXUIS</code> reader - Receive FIFO underflow interrupt …\nField <code>TXEIS</code> reader - Transmit FIFO empty interrupt status\nField <code>TXOIS</code> reader - Transmit FIFO overflow interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 5 - Multi-master contention interrupt status\nBit 4 - Receive FIFO full interrupt status\nBit 3 - Receive FIFO overflow interrupt status\nBit 2 - Receive FIFO underflow interrupt status\nBit 0 - Transmit FIFO empty interrupt status\nBit 1 - Transmit FIFO overflow interrupt status\nField <code>MSTICR</code> reader - Clear-on-read multi-master …\nMulti-master interrupt clear\nRegister <code>MSTICR</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Clear-on-read multi-master contention interrupt\nField <code>MDD</code> reader - Microwire control\nField <code>MDD</code> writer - Microwire control\nField <code>MHS</code> reader - Microwire handshaking\nField <code>MHS</code> writer - Microwire handshaking\nMicrowire Control\nField <code>MWMOD</code> reader - Microwire transfer mode\nField <code>MWMOD</code> writer - Microwire transfer mode\nRegister <code>MWCR</code> reader\nRegister <code>MWCR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 1 - Microwire control\nBit 1 - Microwire control\nBit 2 - Microwire handshaking\nBit 2 - Microwire handshaking\nBit 0 - Microwire transfer mode\nBit 0 - Microwire transfer mode\nField <code>MSTIR</code> reader - Multi-master contention raw interrupt …\nRegister <code>RISR</code> reader\nRaw interrupt status\nField <code>RXFIR</code> reader - Receive FIFO full raw interrupt status\nField <code>RXOIR</code> reader - Receive FIFO overflow raw interrupt …\nField <code>RXUIR</code> reader - Receive FIFO underflow raw interrupt …\nField <code>TXEIR</code> reader - Transmit FIFO empty raw interrupt …\nField <code>TXOIR</code> reader - Transmit FIFO overflow raw interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 5 - Multi-master contention raw interrupt status\nBit 4 - Receive FIFO full raw interrupt status\nBit 3 - Receive FIFO overflow raw interrupt status\nBit 2 - Receive FIFO underflow raw interrupt status\nBit 0 - Transmit FIFO empty raw interrupt status\nBit 1 - Transmit FIFO overflow raw interrupt status\nRegister <code>RX_SAMPLE_DLY</code> reader\nField <code>RSD</code> reader - RXD sample delay (in SCLK cycles)\nField <code>RSD</code> writer - RXD sample delay (in SCLK cycles)\nRX sample delay\nRegister <code>RX_SAMPLE_DLY</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - RXD sample delay (in SCLK cycles)\nBits 0:7 - RXD sample delay (in SCLK cycles)\nRegister <code>RXFLR</code> reader\nRX FIFO level\nField <code>RXTFL</code> reader - Receive FIFO level\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - Receive FIFO level\nRegister <code>RXFTLR</code> reader\nField <code>RFT</code> reader - Receive FIFO threshold\nField <code>RFT</code> writer - Receive FIFO threshold\nRX FIFO threshold level\nRegister <code>RXFTLR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - Receive FIFO threshold\nBits 0:7 - Receive FIFO threshold\nRegister <code>RXOICR</code> reader\nField <code>RXOICR</code> reader - Clear-on-read receive FIFO overflow …\nRX FIFO overflow interrupt clear\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Clear-on-read receive FIFO overflow interrupt\nRegister <code>RXUICR</code> reader\nField <code>RXUICR</code> reader - Clear-on-read receive FIFO underflow …\nRX FIFO underflow interrupt clear\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Clear-on-read receive FIFO underflow interrupt\nRegister <code>SER</code> reader\nField <code>SER</code> reader - For each bit: 0 -&gt; slave not selected 1 …\nSlave enable\nField <code>SER</code> writer - For each bit: 0 -&gt; slave not selected 1 …\nRegister <code>SER</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - For each bit: 0 -&gt; slave not selected 1 -&gt; slave …\nBit 0 - For each bit: 0 -&gt; slave not selected 1 -&gt; slave …\nField <code>ADDR_L</code> reader - Address length (0b-60b in 4b …\nField <code>ADDR_L</code> writer - Address length (0b-60b in 4b …\nField <code>INST_DDR_EN</code> reader - Instruction DDR transfer enable\nField <code>INST_DDR_EN</code> writer - Instruction DDR transfer enable\nInstruction length (0/4/8/16b)\nField <code>INST_L</code> reader - Instruction length (0/4/8/16b)\nField <code>INST_L</code> writer - Instruction length (0/4/8/16b)\n0: No instruction\nRegister <code>SPI_CTRLR0</code> reader\nSPI control\nField <code>SPI_DDR_EN</code> reader - SPI DDR transfer enable\nField <code>SPI_DDR_EN</code> writer - SPI DDR transfer enable\nField <code>SPI_RXDS_EN</code> reader - Read data strobe enable\nField <code>SPI_RXDS_EN</code> writer - Read data strobe enable\nAddress and instruction transfer format\nField <code>TRANS_TYPE</code> reader - Address and instruction transfer …\nField <code>TRANS_TYPE</code> writer - Address and instruction transfer …\nRegister <code>SPI_CTRLR0</code> writer\nField <code>WAIT_CYCLES</code> reader - Wait cycles between control …\nField <code>WAIT_CYCLES</code> writer - Wait cycles between control …\nField <code>XIP_CMD</code> reader - SPI Command to send in XIP mode …\nField <code>XIP_CMD</code> writer - SPI Command to send in XIP mode …\n3: 16-bit instruction\n16-bit instruction\n0: Command and address both in standard SPI frame format\n1: Command in standard SPI format, address in format …\nCommand and address both in standard SPI frame format\nCommand in standard SPI format, address in format …\n2: Command and address both in format specified by FRF …\nCommand and address both in format specified by FRF (e.g. …\n1: 4-bit instruction\n4-bit instruction\n2: 8-bit instruction\n8-bit instruction\nBits 2:5 - Address length (0b-60b in 4b increments)\nBits 2:5 - Address length (0b-60b in 4b increments)\nWrites raw bits to the register.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 17 - Instruction DDR transfer enable\nBit 17 - Instruction DDR transfer enable\nBits 8:9 - Instruction length (0/4/8/16b)\nBits 8:9 - Instruction length (0/4/8/16b)\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n16-bit instruction\nCommand and address both in standard SPI frame format\nCommand in standard SPI format, address in format …\nCommand and address both in format specified by FRF (e.g. …\n4-bit instruction\n8-bit instruction\nNo instruction\nNo instruction\nBit 16 - SPI DDR transfer enable\nBit 16 - SPI DDR transfer enable\nBit 18 - Read data strobe enable\nBit 18 - Read data strobe enable\nBits 0:1 - Address and instruction transfer format\nBits 0:1 - Address and instruction transfer format\nGet enumerated values variant\nGet enumerated values variant\nBits 11:15 - Wait cycles between control frame transmit …\nBits 11:15 - Wait cycles between control frame transmit …\nBits 24:31 - SPI Command to send in XIP mode (INST_L = …\nBits 24:31 - SPI Command to send in XIP mode (INST_L = …\nField <code>BUSY</code> reader - SSI busy flag\nField <code>DCOL</code> reader - Data collision error\nRegister <code>SR</code> reader\nField <code>RFF</code> reader - Receive FIFO full\nField <code>RFNE</code> reader - Receive FIFO not empty\nStatus register\nField <code>TFE</code> reader - Transmit FIFO empty\nField <code>TFNF</code> reader - Transmit FIFO not full\nField <code>TXE</code> reader - Transmission error\nBit 0 - SSI busy flag\nBit 6 - Data collision error\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 4 - Receive FIFO full\nBit 3 - Receive FIFO not empty\nBit 2 - Transmit FIFO empty\nBit 1 - Transmit FIFO not full\nBit 5 - Transmission error\nRegister <code>SSI_VERSION_ID</code> reader\nField <code>SSI_COMP_VERSION</code> reader - SNPS component version …\nVersion ID\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:31 - SNPS component version (format X.YY)\nRegister <code>SSIENR</code> reader\nSSI Enable\nField <code>SSI_EN</code> reader - SSI enable\nField <code>SSI_EN</code> writer - SSI enable\nRegister <code>SSIENR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - SSI enable\nBit 0 - SSI enable\nRegister <code>TXD_DRIVE_EDGE</code> reader\nField <code>TDE</code> reader - TXD drive edge\nField <code>TDE</code> writer - TXD drive edge\nTX drive edge\nRegister <code>TXD_DRIVE_EDGE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - TXD drive edge\nBits 0:7 - TXD drive edge\nRegister <code>TXFLR</code> reader\nField <code>TFTFL</code> reader - Transmit FIFO level\nTX FIFO level\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - Transmit FIFO level\nRegister <code>TXFTLR</code> reader\nField <code>TFT</code> reader - Transmit FIFO threshold\nField <code>TFT</code> writer - Transmit FIFO threshold\nTX FIFO threshold level\nRegister <code>TXFTLR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - Transmit FIFO threshold\nBits 0:7 - Transmit FIFO threshold\nRegister <code>TXOICR</code> reader\nField <code>TXOICR</code> reader - Clear-on-read transmit FIFO overflow …\nTX FIFO overflow interrupt clear\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Clear-on-read transmit FIFO overflow interrupt\nCTRL (rw) register accessor: Crystal Oscillator Control\nDORMANT (rw) register accessor: Crystal Oscillator pause …\nRegister block\nSTARTUP (rw) register accessor: Controls the startup delay\nSTATUS (rw) register accessor: Crystal Oscillator Status\nCrystal Oscillator Control\n0x00 - Crystal Oscillator Control\nCrystal Oscillator pause control This is used to save …\n0x08 - Crystal Oscillator pause control This is used to …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nControls the startup delay\n0x0c - Controls the startup delay\nCrystal Oscillator Status\n0x04 - Crystal Oscillator Status\nCrystal Oscillator Control\n3358: <code>110100011110</code>\n4011: <code>111110101011</code>\nOn power-up this field is initialised to DISABLE and the …\nField <code>ENABLE</code> reader - On power-up this field is …\nField <code>ENABLE</code> writer - On power-up this field is …\nFrequency range. This resets to 0xAA0 and cannot be …\nField <code>FREQ_RANGE</code> reader - Frequency range. This resets to …\nField <code>FREQ_RANGE</code> writer - Frequency range. This resets to …\nRegister <code>CTRL</code> reader\n2721: <code>101010100001</code>\n2722: <code>101010100010</code>\n2723: <code>101010100011</code>\nRegister <code>CTRL</code> writer\n2720: <code>101010100000</code>\n<code>101010100000</code>\nWrites raw bits to the register.\n<code>110100011110</code>\nBits 12:23 - On power-up this field is initialised to …\nBits 12:23 - On power-up this field is initialised to …\n<code>111110101011</code>\nBits 0:11 - Frequency range. This resets to 0xAA0 and …\nBits 0:11 - Frequency range. This resets to 0xAA0 and …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>101010100000</code>\n<code>110100011110</code>\n<code>111110101011</code>\n<code>101010100001</code>\n<code>101010100010</code>\n<code>101010100011</code>\n<code>101010100001</code>\n<code>101010100010</code>\n<code>101010100011</code>\nGet enumerated values variant\nGet enumerated values variant\nCrystal Oscillator pause control This is used to save …\nRegister <code>DORMANT</code> reader\nRegister <code>DORMANT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>DELAY</code> reader - in multiples of 256*xtal_period. The …\nField <code>DELAY</code> writer - in multiples of 256*xtal_period. The …\nRegister <code>STARTUP</code> reader\nControls the startup delay\nRegister <code>STARTUP</code> writer\nField <code>X4</code> reader - Multiplies the startup_delay by 4. This …\nField <code>X4</code> writer - Multiplies the startup_delay by 4. This …\nWrites raw bits to the register.\nBits 0:13 - in multiples of 256*xtal_period. The reset …\nBits 0:13 - in multiples of 256*xtal_period. The reset …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 20 - Multiplies the startup_delay by 4. This is of …\nBit 20 - Multiplies the startup_delay by 4. This is of …\nField <code>BADWRITE</code> reader - An invalid value has been written …\nField <code>BADWRITE</code> writer - An invalid value has been written …\nField <code>ENABLED</code> reader - Oscillator is enabled but not …\nThe current frequency range setting, always reads 0\nField <code>FREQ_RANGE</code> reader - The current frequency range …\nRegister <code>STATUS</code> reader\n1: <code>1</code>\n2: <code>10</code>\n3: <code>11</code>\nField <code>STABLE</code> reader - Oscillator is running and stable\nCrystal Oscillator Status\nRegister <code>STATUS</code> writer\n0: <code>0</code>\nBit 24 - An invalid value has been written to CTRL_ENABLE …\nBit 24 - An invalid value has been written to CTRL_ENABLE …\nWrites raw bits to the register.\nBit 12 - Oscillator is enabled but not necessarily running …\nBits 0:1 - The current frequency range setting, always …\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>0</code>\n<code>1</code>\n<code>10</code>\n<code>11</code>\nBit 31 - Oscillator is running and stable\nGet enumerated values variant")