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rtic/2/api/search.desc/rp2040_pac/rp2040_pac-desc-2-.js
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2024-10-24 05:57:30 +00:00

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searchState.loadedDescShard("rp2040_pac", 2, "Field <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nInterrupt status after masking &amp; forcing for proc1\nRegister <code>PROC1_INTS%s</code> reader\nReturns the argument unchanged.\nBit 3\nBit 2\nBit 1\nBit 0\nBit 7\nBit 6\nBit 5\nBit 4\nBit 11\nBit 10\nBit 9\nBit 8\nBit 15\nBit 14\nBit 13\nBit 12\nBit 19\nBit 18\nBit 17\nBit 16\nBit 23\nBit 22\nBit 21\nBit 20\nBit 27\nBit 26\nBit 25\nBit 24\nBit 31\nBit 30\nBit 29\nBit 28\nCalls <code>U::from(self)</code>.\nDORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable …\nDORMANT_WAKE_INTF (rw) register accessor: Interrupt Force …\nDORMANT_WAKE_INTS (r) register accessor: Interrupt status …\nCluster GPIO_QSPI%s, containing GPIO_QSPI_<em><em>STATUS, GPIO_QSPI</em></em>…\nINTR (rw) register accessor: Raw Interrupts\nPROC0_INTE (rw) register accessor: Interrupt Enable for …\nPROC0_INTF (rw) register accessor: Interrupt Force for …\nPROC0_INTS (r) register accessor: Interrupt status after …\nPROC1_INTE (rw) register accessor: Interrupt Enable for …\nPROC1_INTF (rw) register accessor: Interrupt Force for …\nPROC1_INTS (r) register accessor: Interrupt status after …\nRegister block\nInterrupt Enable for dormant_wake\n0x4c - Interrupt Enable for dormant_wake\nInterrupt Force for dormant_wake\n0x50 - Interrupt Force for dormant_wake\nInterrupt status after masking &amp; forcing for dormant_wake\n0x54 - Interrupt status after masking &amp; forcing for …\nReturns the argument unchanged.\nCluster Cluster GPIO_QSPI%s, containing GPIO_QSPI_<em><em>STATUS, </em></em>…\n0x00..0x30 - Cluster GPIO_QSPI%s, containing GPIO_QSPI_…\nIterator for array of: 0x00..0x30 - Cluster GPIO_QSPI%s, …\n0x00..0x08 - Cluster GPIO_QSPISCLK, containing GPIO_QSPI_…\n0x10..0x18 - Cluster GPIO_QSPISD0, containing GPIO_QSPI_…\n0x18..0x20 - Cluster GPIO_QSPISD1, containing GPIO_QSPI_…\n0x20..0x28 - Cluster GPIO_QSPISD2, containing GPIO_QSPI_…\n0x28..0x30 - Cluster GPIO_QSPISD3, containing GPIO_QSPI_…\n0x08..0x10 - Cluster GPIO_QSPISS, containing GPIO_QSPI_…\nCalls <code>U::from(self)</code>.\nRaw Interrupts\n0x30 - Raw Interrupts\nInterrupt Enable for proc0\n0x34 - Interrupt Enable for proc0\nInterrupt Force for proc0\n0x38 - Interrupt Force for proc0\nInterrupt status after masking &amp; forcing for proc0\n0x3c - Interrupt status after masking &amp; forcing for proc0\nInterrupt Enable for proc1\n0x40 - Interrupt Enable for proc1\nInterrupt Force for proc1\n0x44 - Interrupt Force for proc1\nInterrupt status after masking &amp; forcing for proc1\n0x48 - Interrupt status after masking &amp; forcing for proc1\nInterrupt Enable for dormant_wake\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> writer -\nRegister <code>DORMANT_WAKE_INTE</code> reader\nRegister <code>DORMANT_WAKE_INTE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nCalls <code>U::from(self)</code>.\nInterrupt Force for dormant_wake\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> writer -\nRegister <code>DORMANT_WAKE_INTF</code> reader\nRegister <code>DORMANT_WAKE_INTF</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nCalls <code>U::from(self)</code>.\nInterrupt status after masking &amp; forcing for dormant_wake\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nRegister <code>DORMANT_WAKE_INTS</code> reader\nReturns the argument unchanged.\nBit 3\nBit 2\nBit 1\nBit 0\nBit 11\nBit 10\nBit 9\nBit 8\nBit 15\nBit 14\nBit 13\nBit 12\nBit 19\nBit 18\nBit 17\nBit 16\nBit 23\nBit 22\nBit 21\nBit 20\nBit 7\nBit 6\nBit 5\nBit 4\nCalls <code>U::from(self)</code>.\nGPIO_CTRL (rw) register accessor: GPIO control including …\nRegister block\nGPIO_STATUS (r) register accessor: GPIO status\nReturns the argument unchanged.\nGPIO control including function select and overrides.\n0x04 - GPIO control including function select and …\nGPIO status\n0x00 - GPIO status\nCalls <code>U::from(self)</code>.\n2: disable output\n3: enable output\n0-31 -&gt; selects pin function according to the gpio table …\nField <code>FUNCSEL</code> reader - 0-31 -&gt; selects pin function …\nField <code>FUNCSEL</code> writer - 0-31 -&gt; selects pin function …\nGPIO control including function select and overrides.\n3: drive output high\n3: drive peri input high\n3: drive interrupt high\nValue on reset: 0\nField <code>INOVER</code> reader -\nField <code>INOVER</code> writer -\n1: drive output from inverse of peripheral signal selected …\n1: drive output enable from inverse of peripheral signal …\n1: invert the peri input\n1: invert the interrupt\nValue on reset: 0\nField <code>IRQOVER</code> reader -\nField <code>IRQOVER</code> writer -\n2: drive output low\n2: drive peri input low\n2: drive interrupt low\n0: drive output from peripheral signal selected by funcsel\n0: drive output enable from peripheral signal selected by …\n0: don’t invert the peri input\n0: don’t invert the interrupt\n31: <code>11111</code>\nValue on reset: 0\nField <code>OEOVER</code> reader -\nField <code>OEOVER</code> writer -\nValue on reset: 0\nField <code>OUTOVER</code> reader -\nField <code>OUTOVER</code> writer -\nRegister <code>GPIO_CTRL</code> reader\n5: <code>101</code>\nRegister <code>GPIO_CTRL</code> writer\n0: <code>0</code>\nWrites raw bits to the register.\ndisable output\nenable output\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBits 0:4 - 0-31 -&gt; selects pin function according to the …\nBits 0:4 - 0-31 -&gt; selects pin function according to the …\ndrive output high\ndrive peri input high\ndrive interrupt high\nBits 16:17\nBits 16:17\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\ndrive output from inverse of peripheral signal selected by …\ndrive output enable from inverse of peripheral signal …\ninvert the peri input\ninvert the interrupt\nBits 28:29\nBits 28:29\ndisable output\nenable output\ndrive output high\ndrive peri input high\ndrive interrupt high\ndrive output from inverse of peripheral signal selected by …\ndrive output enable from inverse of peripheral signal …\ninvert the peri input\ninvert the interrupt\ndrive output low\ndrive peri input low\ndrive interrupt low\ndrive output from peripheral signal selected by funcsel\ndrive output enable from peripheral signal selected by …\ndon’t invert the peri input\ndon’t invert the interrupt\n<code>11111</code>\n<code>101</code>\n<code>0</code>\ndrive output low\ndrive peri input low\ndrive interrupt low\ndrive output from peripheral signal selected by funcsel\ndrive output enable from peripheral signal selected by …\ndon’t invert the peri input\ndon’t invert the interrupt\n<code>11111</code>\nBits 12:13\nBits 12:13\nBits 8:9\nBits 8:9\n<code>101</code>\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\n<code>0</code>\nGPIO status\nField <code>INFROMPAD</code> reader - input signal from pad, before …\nField <code>INTOPERI</code> reader - input signal to peripheral, after …\nField <code>IRQFROMPAD</code> reader - interrupt from pad before …\nField <code>IRQTOPROC</code> reader - interrupt to processors, after …\nField <code>OEFROMPERI</code> reader - output enable from selected …\nField <code>OETOPAD</code> reader - output enable to pad after register …\nField <code>OUTFROMPERI</code> reader - output signal from selected …\nField <code>OUTTOPAD</code> reader - output signal to pad after …\nRegister <code>GPIO_STATUS</code> reader\nReturns the argument unchanged.\nBit 17 - input signal from pad, before override is applied\nCalls <code>U::from(self)</code>.\nBit 19 - input signal to peripheral, after override is …\nBit 24 - interrupt from pad before override is applied\nBit 26 - interrupt to processors, after override is applied\nBit 12 - output enable from selected peripheral, before …\nBit 13 - output enable to pad after register override is …\nBit 8 - output signal from selected peripheral, before …\nBit 9 - output signal to pad after register override is …\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nRaw Interrupts\nRegister <code>INTR</code> reader\nRegister <code>INTR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 0\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 20\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 4\nCalls <code>U::from(self)</code>.\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> writer -\nInterrupt Enable for proc0\nRegister <code>PROC0_INTE</code> reader\nRegister <code>PROC0_INTE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nCalls <code>U::from(self)</code>.\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> writer -\nInterrupt Force for proc0\nRegister <code>PROC0_INTF</code> reader\nRegister <code>PROC0_INTF</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nCalls <code>U::from(self)</code>.\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nInterrupt status after masking &amp; forcing for proc0\nRegister <code>PROC0_INTS</code> reader\nReturns the argument unchanged.\nBit 3\nBit 2\nBit 1\nBit 0\nBit 11\nBit 10\nBit 9\nBit 8\nBit 15\nBit 14\nBit 13\nBit 12\nBit 19\nBit 18\nBit 17\nBit 16\nBit 23\nBit 22\nBit 21\nBit 20\nBit 7\nBit 6\nBit 5\nBit 4\nCalls <code>U::from(self)</code>.\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> writer -\nInterrupt Enable for proc1\nRegister <code>PROC1_INTE</code> reader\nRegister <code>PROC1_INTE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nCalls <code>U::from(self)</code>.\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> writer -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> writer -\nInterrupt Force for proc1\nRegister <code>PROC1_INTF</code> reader\nRegister <code>PROC1_INTF</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nCalls <code>U::from(self)</code>.\nField <code>GPIO_QSPI_SCLK_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SCLK_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD0_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD1_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD2_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SD3_LEVEL_LOW</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_EDGE_LOW</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_HIGH</code> reader -\nField <code>GPIO_QSPI_SS_LEVEL_LOW</code> reader -\nInterrupt status after masking &amp; forcing for proc1\nRegister <code>PROC1_INTS</code> reader\nReturns the argument unchanged.\nBit 3\nBit 2\nBit 1\nBit 0\nBit 11\nBit 10\nBit 9\nBit 8\nBit 15\nBit 14\nBit 13\nBit 12\nBit 19\nBit 18\nBit 17\nBit 16\nBit 23\nBit 22\nBit 21\nBit 20\nBit 7\nBit 6\nBit 5\nBit 4\nCalls <code>U::from(self)</code>.\nGPIO (rw) register accessor: Pad control register\nRegister block\nSWCLK (rw) register accessor: Pad control register\nSWD (rw) register accessor: Pad control register\nVOLTAGE_SELECT (rw) register accessor: Voltage select. Per …\nReturns the argument unchanged.\nPad control register\n0x04..0x7c - Pad control register\nIterator for array of: 0x04..0x7c - Pad control register\nCalls <code>U::from(self)</code>.\nPad control register\n0x7c - Pad control register\nPad control register\n0x80 - Pad control register\nVoltage select. Per bank control\n0x00 - Voltage select. Per bank control\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nPad control register\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>GPIO%s</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nRegister <code>GPIO%s</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>SWCLK</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nPad control register\nRegister <code>SWCLK</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>SWD</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nPad control register\nRegister <code>SWD</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nRegister <code>VOLTAGE_SELECT</code> reader\nValue on reset: 0\nField <code>VOLTAGE_SELECT</code> reader -\nVoltage select. Per bank control\nField <code>VOLTAGE_SELECT</code> writer -\nRegister <code>VOLTAGE_SELECT</code> writer\n1: Set voltage to 1.8V (DVDD &lt;= 1V8)\nSet voltage to 1.8V (DVDD &lt;= 1V8)\n0: Set voltage to 3.3V (DVDD &gt;= 2V5)\nSet voltage to 3.3V (DVDD &gt;= 2V5)\nWrites raw bits to the register.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nSet voltage to 1.8V (DVDD &lt;= 1V8)\nSet voltage to 3.3V (DVDD &gt;= 2V5)\nGet enumerated values variant\nBit 0\nBit 0\nGPIO_QSPI_SCLK (rw) register accessor: Pad control register\nGPIO_QSPI_SD0 (rw) register accessor: Pad control register\nGPIO_QSPI_SD1 (rw) register accessor: Pad control register\nGPIO_QSPI_SD2 (rw) register accessor: Pad control register\nGPIO_QSPI_SD3 (rw) register accessor: Pad control register\nGPIO_QSPI_SS (rw) register accessor: Pad control register\nRegister block\nVOLTAGE_SELECT (rw) register accessor: Voltage select. Per …\nReturns the argument unchanged.\nPad control register\n0x04 - Pad control register\nPad control register\n0x08 - Pad control register\nPad control register\n0x0c - Pad control register\nPad control register\n0x10 - Pad control register\nPad control register\n0x14 - Pad control register\nPad control register\n0x18 - Pad control register\nCalls <code>U::from(self)</code>.\nVoltage select. Per bank control\n0x00 - Voltage select. Per bank control\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nPad control register\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>GPIO_QSPI_SCLK</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nRegister <code>GPIO_QSPI_SCLK</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nPad control register\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>GPIO_QSPI_SD0</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nRegister <code>GPIO_QSPI_SD0</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nPad control register\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>GPIO_QSPI_SD1</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nRegister <code>GPIO_QSPI_SD1</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nPad control register\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>GPIO_QSPI_SD2</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nRegister <code>GPIO_QSPI_SD2</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nPad control register\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>GPIO_QSPI_SD3</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nRegister <code>GPIO_QSPI_SD3</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nDrive strength.\nField <code>DRIVE</code> reader - Drive strength.\nField <code>DRIVE</code> writer - Drive strength.\nPad control register\nField <code>IE</code> reader - Input enable\nField <code>IE</code> writer - Input enable\nField <code>OD</code> reader - Output disable. Has priority over output …\nField <code>OD</code> writer - Output disable. Has priority over output …\nField <code>PDE</code> reader - Pull down enable\nField <code>PDE</code> writer - Pull down enable\nField <code>PUE</code> reader - Pull up enable\nField <code>PUE</code> writer - Pull up enable\nRegister <code>GPIO_QSPI_SS</code> reader\nField <code>SCHMITT</code> reader - Enable schmitt trigger\nField <code>SCHMITT</code> writer - Enable schmitt trigger\nField <code>SLEWFAST</code> reader - Slew rate control. 1 = Fast, 0 = …\nField <code>SLEWFAST</code> writer - Slew rate control. 1 = Fast, 0 = …\nRegister <code>GPIO_QSPI_SS</code> writer\n3: <code>11</code>\n<code>11</code>\n0: <code>0</code>\n<code>0</code>\n1: <code>1</code>\n<code>1</code>\n2: <code>10</code>\n<code>10</code>\nWrites raw bits to the register.\nBits 4:5 - Drive strength.\nBits 4:5 - Drive strength.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 6 - Input enable\nBit 6 - Input enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 7 - Output disable. Has priority over output enable …\nBit 7 - Output disable. Has priority over output enable …\nBit 2 - Pull down enable\nBit 2 - Pull down enable\nBit 3 - Pull up enable\nBit 3 - Pull up enable\nBit 1 - Enable schmitt trigger\nBit 1 - Enable schmitt trigger\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nBit 0 - Slew rate control. 1 = Fast, 0 = Slow\nGet enumerated values variant\nRegister <code>VOLTAGE_SELECT</code> reader\nValue on reset: 0\nField <code>VOLTAGE_SELECT</code> reader -\nVoltage select. Per bank control\nField <code>VOLTAGE_SELECT</code> writer -\nRegister <code>VOLTAGE_SELECT</code> writer\n1: Set voltage to 1.8V (DVDD &lt;= 1V8)\nSet voltage to 1.8V (DVDD &lt;= 1V8)\n0: Set voltage to 3.3V (DVDD &gt;= 2V5)\nSet voltage to 3.3V (DVDD &gt;= 2V5)\nWrites raw bits to the register.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nSet voltage to 1.8V (DVDD &lt;= 1V8)\nSet voltage to 3.3V (DVDD &gt;= 2V5)\nGet enumerated values variant\nBit 0\nBit 0\nCTRL (rw) register accessor: PIO control register\nDBG_CFGINFO (r) register accessor: The PIO hardware has …\nDBG_PADOE (r) register accessor: Read to sample the pad …\nDBG_PADOUT (r) register accessor: Read to sample the pad …\nFDEBUG (rw) register accessor: FIFO debug register\nFLEVEL (r) register accessor: FIFO levels\nFSTAT (r) register accessor: FIFO status register\nINPUT_SYNC_BYPASS (rw) register accessor: There is a …\nINSTR_MEM (w) register accessor: Write-only access to …\nINTR (r) register accessor: Raw Interrupts\nIRQ (rw) register accessor: State machine IRQ flags …\nIRQ_FORCE (w) register accessor: Writing a 1 to each of …\nRXF (r) register accessor: Direct read access to the RX …\nRegister block\nCluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_…\nCluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_…\nTXF (w) register accessor: Direct write access to the TX …\nPIO control register\n0x00 - PIO control register\nThe PIO hardware has some free parameters that may vary …\n0x44 - The PIO hardware has some free parameters that may …\nRead to sample the pad output enables (direction) PIO is …\n0x40 - Read to sample the pad output enables (direction) …\nRead to sample the pad output values PIO is currently …\n0x3c - Read to sample the pad output values PIO is …\nFIFO debug register\n0x08 - FIFO debug register\nFIFO levels\n0x0c - FIFO levels\nReturns the argument unchanged.\nFIFO status register\n0x04 - FIFO status register\nThere is a 2-flipflop synchronizer on each GPIO input, …\n0x38 - There is a 2-flipflop synchronizer on each GPIO …\nWrite-only access to instruction memory location %s\n0x48..0xc8 - Write-only access to instruction memory …\nIterator for array of: 0x48..0xc8 - Write-only access to …\nCalls <code>U::from(self)</code>.\nRaw Interrupts\n0x128 - Raw Interrupts\nState machine IRQ flags register. Write 1 to clear. There …\n0x30 - State machine IRQ flags register. Write 1 to clear. …\nWriting a 1 to each of these bits will forcibly assert the …\n0x34 - Writing a 1 to each of these bits will forcibly …\nDirect read access to the RX FIFO for this state machine. …\n0x20..0x30 - Direct read access to the RX FIFO for this …\nIterator for array of: 0x20..0x30 - Direct read access to …\nCluster Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, …\n0xc8..0x128 - Cluster SM%s, containing SM*_CLKDIV, SM*_…\nCluster Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, …\n0x12c..0x144 - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*…\nIterator for array of: 0x12c..0x144 - Cluster SM_IRQ%s, …\nIterator for array of: 0xc8..0x128 - Cluster SM%s, …\nDirect write access to the TX FIFO for this state machine. …\n0x10..0x20 - Direct write access to the TX FIFO for this …\nIterator for array of: 0x10..0x20 - Direct write access to …\nField <code>CLKDIV_RESTART</code> reader - Restart a state machine’s …\nField <code>CLKDIV_RESTART</code> writer - Restart a state machine’s …\nPIO control register\nRegister <code>CTRL</code> reader\nField <code>SM_ENABLE</code> reader - Enable/disable each of the four …\nField <code>SM_ENABLE</code> writer - Enable/disable each of the four …\nField <code>SM_RESTART</code> reader - Write 1 to instantly clear …\nField <code>SM_RESTART</code> writer - Write 1 to instantly clear …\nRegister <code>CTRL</code> writer\nWrites raw bits to the register.\nBits 8:11 - Restart a state machine’s clock divider from …\nBits 8:11 - Restart a state machine’s clock divider from …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:3 - Enable/disable each of the four state machines …\nBits 0:3 - Enable/disable each of the four state machines …\nBits 4:7 - Write 1 to instantly clear internal SM state …\nBits 4:7 - Write 1 to instantly clear internal SM state …\nThe PIO hardware has some free parameters that may vary …\nField <code>FIFO_DEPTH</code> reader - The depth of the state machine …\nField <code>IMEM_SIZE</code> reader - The size of the instruction …\nRegister <code>DBG_CFGINFO</code> reader\nField <code>SM_COUNT</code> reader - The number of state machines this …\nBits 0:5 - The depth of the state machine TX/RX FIFOs, …\nReturns the argument unchanged.\nBits 16:21 - The size of the instruction memory, measured …\nCalls <code>U::from(self)</code>.\nBits 8:11 - The number of state machines this PIO instance …\nRead to sample the pad output enables (direction) PIO is …\nRegister <code>DBG_PADOE</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead to sample the pad output values PIO is currently …\nRegister <code>DBG_PADOUT</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nFIFO debug register\nRegister <code>FDEBUG</code> reader\nField <code>RXSTALL</code> reader - State machine has stalled on full …\nField <code>RXSTALL</code> writer - State machine has stalled on full …\nField <code>RXUNDER</code> reader - RX FIFO underflow (i.e. …\nField <code>RXUNDER</code> writer - RX FIFO underflow (i.e. …\nField <code>TXOVER</code> reader - TX FIFO overflow (i.e. write-on-full …\nField <code>TXOVER</code> writer - TX FIFO overflow (i.e. write-on-full …\nField <code>TXSTALL</code> reader - State machine has stalled on empty …\nField <code>TXSTALL</code> writer - State machine has stalled on empty …\nRegister <code>FDEBUG</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:3 - State machine has stalled on full RX FIFO …\nBits 0:3 - State machine has stalled on full RX FIFO …\nBits 8:11 - RX FIFO underflow (i.e. read-on-empty by the …\nBits 8:11 - RX FIFO underflow (i.e. read-on-empty by the …\nBits 16:19 - TX FIFO overflow (i.e. write-on-full by the …\nBits 16:19 - TX FIFO overflow (i.e. write-on-full by the …\nBits 24:27 - State machine has stalled on empty TX FIFO …\nBits 24:27 - State machine has stalled on empty TX FIFO …\nFIFO levels\nRegister <code>FLEVEL</code> reader\nField <code>RX0</code> reader -\nField <code>RX1</code> reader -\nField <code>RX2</code> reader -\nField <code>RX3</code> reader -\nField <code>TX0</code> reader -\nField <code>TX1</code> reader -\nField <code>TX2</code> reader -\nField <code>TX3</code> reader -\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 4:7\nBits 12:15\nBits 20:23\nBits 28:31\nBits 0:3\nBits 8:11\nBits 16:19\nBits 24:27\nFIFO status register\nRegister <code>FSTAT</code> reader\nField <code>RXEMPTY</code> reader - State machine RX FIFO is empty\nField <code>RXFULL</code> reader - State machine RX FIFO is full\nField <code>TXEMPTY</code> reader - State machine TX FIFO is empty\nField <code>TXFULL</code> reader - State machine TX FIFO is full\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 8:11 - State machine RX FIFO is empty\nBits 0:3 - State machine RX FIFO is full\nBits 24:27 - State machine TX FIFO is empty\nBits 16:19 - State machine TX FIFO is full\nThere is a 2-flipflop synchronizer on each GPIO input, …\nRegister <code>INPUT_SYNC_BYPASS</code> reader\nRegister <code>INPUT_SYNC_BYPASS</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>INSTR_MEM0</code> writer -\nWrite-only access to instruction memory location %s\nRegister <code>INSTR_MEM%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15\nCalls <code>U::from(self)</code>.\nRaw Interrupts\nRegister <code>INTR</code> reader\nField <code>SM0</code> reader -\nField <code>SM0_RXNEMPTY</code> reader -\nField <code>SM0_TXNFULL</code> reader -\nField <code>SM1</code> reader -\nField <code>SM1_RXNEMPTY</code> reader -\nField <code>SM1_TXNFULL</code> reader -\nField <code>SM2</code> reader -\nField <code>SM2_RXNEMPTY</code> reader -\nField <code>SM2_TXNFULL</code> reader -\nField <code>SM3</code> reader -\nField <code>SM3_RXNEMPTY</code> reader -\nField <code>SM3_TXNFULL</code> reader -\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 8\nBit 0\nBit 4\nBit 9\nBit 1\nBit 5\nBit 10\nBit 2\nBit 6\nBit 11\nBit 3\nBit 7\nField <code>IRQ</code> reader -\nState machine IRQ flags register. Write 1 to clear. There …\nField <code>IRQ</code> writer -\nRegister <code>IRQ</code> reader\nRegister <code>IRQ</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7\nBits 0:7\nWriting a 1 to each of these bits will forcibly assert the …\nField <code>IRQ_FORCE</code> writer -\nRegister <code>IRQ_FORCE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7\nRegister <code>RXF%s</code> reader\nDirect read access to the RX FIFO for this state machine. …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister block\nSM_ADDR (r) register accessor: Current instruction address …\nSM_CLKDIV (rw) register accessor: Clock divisor register …\nSM_EXECCTRL (rw) register accessor: Execution/behavioural …\nSM_INSTR (rw) register accessor: Read to see the …\nSM_PINCTRL (rw) register accessor: State machine pin …\nSM_SHIFTCTRL (rw) register accessor: Control behaviour of …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCurrent instruction address of state machine 0\n0x0c - Current instruction address of state machine 0\nClock divisor register for state machine 0 Frequency = …\n0x00 - Clock divisor register for state machine 0 …\nExecution/behavioural settings for state machine 0\n0x04 - Execution/behavioural settings for state machine 0\nRead to see the instruction currently addressed by state …\n0x10 - Read to see the instruction currently addressed by …\nState machine pin control\n0x14 - State machine pin control\nControl behaviour of the input/output shift registers for …\n0x08 - Control behaviour of the input/output shift …\nRegister <code>SM_ADDR</code> reader\nField <code>SM0_ADDR</code> reader -\nCurrent instruction address of state machine 0\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:4\nField <code>FRAC</code> reader - Fractional part of clock divisor\nField <code>FRAC</code> writer - Fractional part of clock divisor\nField <code>INT</code> reader - Effective frequency is sysclk/(int + …\nField <code>INT</code> writer - Effective frequency is sysclk/(int + …\nRegister <code>SM_CLKDIV</code> reader\nClock divisor register for state machine 0 Frequency = …\nRegister <code>SM_CLKDIV</code> writer\nWrites raw bits to the register.\nBits 8:15 - Fractional part of clock divisor\nBits 8:15 - Fractional part of clock divisor\nReturns the argument unchanged.\nBits 16:31 - Effective frequency is sysclk/(int + …\nBits 16:31 - Effective frequency is sysclk/(int + …\nCalls <code>U::from(self)</code>.\nField <code>EXEC_STALLED</code> reader - If 1, an instruction written …\nField <code>INLINE_OUT_EN</code> reader - If 1, use a bit of OUT data …\nField <code>INLINE_OUT_EN</code> writer - If 1, use a bit of OUT data …\nField <code>JMP_PIN</code> reader - The GPIO number to use as condition …\nField <code>JMP_PIN</code> writer - The GPIO number to use as condition …\nField <code>OUT_EN_SEL</code> reader - Which data bit to use for inline …\nField <code>OUT_EN_SEL</code> writer - Which data bit to use for inline …\nField <code>OUT_STICKY</code> reader - Continuously assert the most …\nField <code>OUT_STICKY</code> writer - Continuously assert the most …\nRegister <code>SM_EXECCTRL</code> reader\n1: All-ones if RX FIFO level &lt; N, otherwise all-zeroes\nField <code>SIDE_EN</code> reader - If 1, the MSB of the Delay/Side-set …\nField <code>SIDE_EN</code> writer - If 1, the MSB of the Delay/Side-set …\nField <code>SIDE_PINDIR</code> reader - If 1, side-set data is asserted …\nField <code>SIDE_PINDIR</code> writer - If 1, side-set data is asserted …\nExecution/behavioural settings for state machine 0\nField <code>STATUS_N</code> reader - Comparison level for the MOV x, …\nField <code>STATUS_N</code> writer - Comparison level for the MOV x, …\nComparison used for the MOV x, STATUS instruction.\nField <code>STATUS_SEL</code> reader - Comparison used for the MOV x, …\nField <code>STATUS_SEL</code> writer - Comparison used for the MOV x, …\n0: All-ones if TX FIFO level &lt; N, otherwise all-zeroes\nRegister <code>SM_EXECCTRL</code> writer\nField <code>WRAP_BOTTOM</code> reader - After reaching wrap_top, …\nField <code>WRAP_BOTTOM</code> writer - After reaching wrap_top, …\nField <code>WRAP_TOP</code> reader - After reaching this address, …\nField <code>WRAP_TOP</code> writer - After reaching this address, …\nWrites raw bits to the register.\nBit 31 - If 1, an instruction written to SMx_INSTR is …\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 18 - If 1, use a bit of OUT data as an auxiliary write …\nBit 18 - If 1, use a bit of OUT data as an auxiliary write …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nAll-ones if RX FIFO level &lt; N, otherwise all-zeroes\nAll-ones if TX FIFO level &lt; N, otherwise all-zeroes\nBits 24:28 - The GPIO number to use as condition for JMP …\nBits 24:28 - The GPIO number to use as condition for JMP …\nBits 19:23 - Which data bit to use for inline OUT enable\nBits 19:23 - Which data bit to use for inline OUT enable\nBit 17 - Continuously assert the most recent OUT/SET to …\nBit 17 - Continuously assert the most recent OUT/SET to …\nAll-ones if RX FIFO level &lt; N, otherwise all-zeroes\nBit 30 - If 1, the MSB of the Delay/Side-set instruction …\nBit 30 - If 1, the MSB of the Delay/Side-set instruction …\nBit 29 - If 1, side-set data is asserted to pin …\nBit 29 - If 1, side-set data is asserted to pin …\nBits 0:3 - Comparison level for the MOV x, STATUS …\nBits 0:3 - Comparison level for the MOV x, STATUS …\nBit 4 - Comparison used for the MOV x, STATUS instruction.\nBit 4 - Comparison used for the MOV x, STATUS instruction.\nAll-ones if TX FIFO level &lt; N, otherwise all-zeroes\nGet enumerated values variant\nBits 7:11 - After reaching wrap_top, execution is wrapped …\nBits 7:11 - After reaching wrap_top, execution is wrapped …\nBits 12:16 - After reaching this address, execution is …\nBits 12:16 - After reaching this address, execution is …\nRegister <code>SM_INSTR</code> reader\nField <code>SM0_INSTR</code> reader -\nField <code>SM0_INSTR</code> writer -\nRead to see the instruction currently addressed by state …\nRegister <code>SM_INSTR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15\nBits 0:15\nField <code>IN_BASE</code> reader - The pin which is mapped to the …\nField <code>IN_BASE</code> writer - The pin which is mapped to the …\nField <code>OUT_BASE</code> reader - The lowest-numbered pin that will …\nField <code>OUT_BASE</code> writer - The lowest-numbered pin that will …\nField <code>OUT_COUNT</code> reader - The number of pins asserted by an …\nField <code>OUT_COUNT</code> writer - The number of pins asserted by an …\nRegister <code>SM_PINCTRL</code> reader\nField <code>SET_BASE</code> reader - The lowest-numbered pin that will …\nField <code>SET_BASE</code> writer - The lowest-numbered pin that will …\nField <code>SET_COUNT</code> reader - The number of pins asserted by a …\nField <code>SET_COUNT</code> writer - The number of pins asserted by a …\nField <code>SIDESET_BASE</code> reader - The lowest-numbered pin that …\nField <code>SIDESET_BASE</code> writer - The lowest-numbered pin that …\nField <code>SIDESET_COUNT</code> reader - The number of MSBs of the …\nField <code>SIDESET_COUNT</code> writer - The number of MSBs of the …\nState machine pin control\nRegister <code>SM_PINCTRL</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 15:19 - The pin which is mapped to the …\nBits 15:19 - The pin which is mapped to the …\nCalls <code>U::from(self)</code>.\nBits 0:4 - The lowest-numbered pin that will be affected …\nBits 0:4 - The lowest-numbered pin that will be affected …\nBits 20:25 - The number of pins asserted by an OUT PINS, …\nBits 20:25 - The number of pins asserted by an OUT PINS, …\nBits 5:9 - The lowest-numbered pin that will be affected …\nBits 5:9 - The lowest-numbered pin that will be affected …\nBits 26:28 - The number of pins asserted by a SET. In the …\nBits 26:28 - The number of pins asserted by a SET. In the …\nBits 10:14 - The lowest-numbered pin that will be affected …\nBits 10:14 - The lowest-numbered pin that will be affected …\nBits 29:31 - The number of MSBs of the Delay/Side-set …\nBits 29:31 - The number of MSBs of the Delay/Side-set …\nField <code>AUTOPULL</code> reader - Pull automatically when the output …\nField <code>AUTOPULL</code> writer - Pull automatically when the output …\nField <code>AUTOPUSH</code> reader - Push automatically when the input …\nField <code>AUTOPUSH</code> writer - Push automatically when the input …\nField <code>FJOIN_RX</code> reader - When 1, RX FIFO steals the TX FIFO…\nField <code>FJOIN_RX</code> writer - When 1, RX FIFO steals the TX FIFO…\nField <code>FJOIN_TX</code> reader - When 1, TX FIFO steals the RX FIFO…\nField <code>FJOIN_TX</code> writer - When 1, TX FIFO steals the RX FIFO…\nField <code>IN_SHIFTDIR</code> reader - 1 = shift input shift register …\nField <code>IN_SHIFTDIR</code> writer - 1 = shift input shift register …\nField <code>OUT_SHIFTDIR</code> reader - 1 = shift out of output shift …\nField <code>OUT_SHIFTDIR</code> writer - 1 = shift out of output shift …\nField <code>PULL_THRESH</code> reader - Number of bits shifted out of …\nField <code>PULL_THRESH</code> writer - Number of bits shifted out of …\nField <code>PUSH_THRESH</code> reader - Number of bits shifted into ISR …\nField <code>PUSH_THRESH</code> writer - Number of bits shifted into ISR …\nRegister <code>SM_SHIFTCTRL</code> reader\nControl behaviour of the input/output shift registers for …\nRegister <code>SM_SHIFTCTRL</code> writer\nBit 17 - Pull automatically when the output shift register …\nBit 17 - Pull automatically when the output shift register …\nBit 16 - Push automatically when the input shift register …\nBit 16 - Push automatically when the input shift register …\nWrites raw bits to the register.\nBit 31 - When 1, RX FIFO steals the TX FIFO’s storage, …\nBit 31 - When 1, RX FIFO steals the TX FIFO’s storage, …\nBit 30 - When 1, TX FIFO steals the RX FIFO’s storage, …\nBit 30 - When 1, TX FIFO steals the RX FIFO’s storage, …\nReturns the argument unchanged.\nBit 18 - 1 = shift input shift register to right (data …\nBit 18 - 1 = shift input shift register to right (data …\nCalls <code>U::from(self)</code>.\nBit 19 - 1 = shift out of output shift register to right. …\nBit 19 - 1 = shift out of output shift register to right. …\nBits 25:29 - Number of bits shifted out of OSR before …\nBits 25:29 - Number of bits shifted out of OSR before …\nBits 20:24 - Number of bits shifted into ISR before …\nBits 20:24 - Number of bits shifted into ISR before …\nIRQ_INTE (rw) register accessor: Interrupt Enable for irq0\nIRQ_INTF (rw) register accessor: Interrupt Force for irq0\nIRQ_INTS (r) register accessor: Interrupt status after …\nRegister block\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nInterrupt Enable for irq0\n0x00 - Interrupt Enable for irq0\nInterrupt Force for irq0\n0x04 - Interrupt Force for irq0\nInterrupt status after masking &amp; forcing for irq0\n0x08 - Interrupt status after masking &amp; forcing for irq0\nInterrupt Enable for irq0\nRegister <code>IRQ_INTE</code> reader\nField <code>SM0</code> reader -\nField <code>SM0_RXNEMPTY</code> reader -\nField <code>SM0_RXNEMPTY</code> writer -\nField <code>SM0_TXNFULL</code> reader -\nField <code>SM0_TXNFULL</code> writer -\nField <code>SM0</code> writer -\nField <code>SM1</code> reader -\nField <code>SM1_RXNEMPTY</code> reader -\nField <code>SM1_RXNEMPTY</code> writer -\nField <code>SM1_TXNFULL</code> reader -\nField <code>SM1_TXNFULL</code> writer -\nField <code>SM1</code> writer -\nField <code>SM2</code> reader -\nField <code>SM2_RXNEMPTY</code> reader -\nField <code>SM2_RXNEMPTY</code> writer -\nField <code>SM2_TXNFULL</code> reader -\nField <code>SM2_TXNFULL</code> writer -\nField <code>SM2</code> writer -\nField <code>SM3</code> reader -\nField <code>SM3_RXNEMPTY</code> reader -\nField <code>SM3_RXNEMPTY</code> writer -\nField <code>SM3_TXNFULL</code> reader -\nField <code>SM3_TXNFULL</code> writer -\nField <code>SM3</code> writer -\nRegister <code>IRQ_INTE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 8\nBit 8\nBit 0\nBit 0\nBit 4\nBit 4\nBit 9\nBit 9\nBit 1\nBit 1\nBit 5\nBit 5\nBit 10\nBit 10\nBit 2\nBit 2\nBit 6\nBit 6\nBit 11\nBit 11\nBit 3\nBit 3\nBit 7\nBit 7\nInterrupt Force for irq0\nRegister <code>IRQ_INTF</code> reader\nField <code>SM0</code> reader -\nField <code>SM0_RXNEMPTY</code> reader -\nField <code>SM0_RXNEMPTY</code> writer -\nField <code>SM0_TXNFULL</code> reader -\nField <code>SM0_TXNFULL</code> writer -\nField <code>SM0</code> writer -\nField <code>SM1</code> reader -\nField <code>SM1_RXNEMPTY</code> reader -\nField <code>SM1_RXNEMPTY</code> writer -\nField <code>SM1_TXNFULL</code> reader -\nField <code>SM1_TXNFULL</code> writer -\nField <code>SM1</code> writer -\nField <code>SM2</code> reader -\nField <code>SM2_RXNEMPTY</code> reader -\nField <code>SM2_RXNEMPTY</code> writer -\nField <code>SM2_TXNFULL</code> reader -\nField <code>SM2_TXNFULL</code> writer -\nField <code>SM2</code> writer -\nField <code>SM3</code> reader -\nField <code>SM3_RXNEMPTY</code> reader -\nField <code>SM3_RXNEMPTY</code> writer -\nField <code>SM3_TXNFULL</code> reader -\nField <code>SM3_TXNFULL</code> writer -\nField <code>SM3</code> writer -\nRegister <code>IRQ_INTF</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 8\nBit 8\nBit 0\nBit 0\nBit 4\nBit 4\nBit 9\nBit 9\nBit 1\nBit 1\nBit 5\nBit 5\nBit 10\nBit 10\nBit 2\nBit 2\nBit 6\nBit 6\nBit 11\nBit 11\nBit 3\nBit 3\nBit 7\nBit 7\nInterrupt status after masking &amp; forcing for irq0\nRegister <code>IRQ_INTS</code> reader\nField <code>SM0</code> reader -\nField <code>SM0_RXNEMPTY</code> reader -\nField <code>SM0_TXNFULL</code> reader -\nField <code>SM1</code> reader -\nField <code>SM1_RXNEMPTY</code> reader -\nField <code>SM1_TXNFULL</code> reader -\nField <code>SM2</code> reader -\nField <code>SM2_RXNEMPTY</code> reader -\nField <code>SM2_TXNFULL</code> reader -\nField <code>SM3</code> reader -\nField <code>SM3_RXNEMPTY</code> reader -\nField <code>SM3_TXNFULL</code> reader -\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 8\nBit 0\nBit 4\nBit 9\nBit 1\nBit 5\nBit 10\nBit 2\nBit 6\nBit 11\nBit 3\nBit 7\nDirect write access to the TX FIFO for this state machine. …\nRegister <code>TXF%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCS (rw) register accessor: Control and Status GENERAL …\nFBDIV_INT (rw) register accessor: Feedback divisor (note: …\nPRIM (rw) register accessor: Controls the PLL post …\nPWR (rw) register accessor: Controls the PLL power modes.\nRegister block\nControl and Status GENERAL CONSTRAINTS: Reference clock …\n0x00 - Control and Status GENERAL CONSTRAINTS: Reference …\nFeedback divisor (note: this PLL does not support …\n0x08 - Feedback divisor (note: this PLL does not support …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nControls the PLL post dividers for the primary output …\n0x0c - Controls the PLL post dividers for the primary …\nControls the PLL power modes.\n0x04 - Controls the PLL power modes.\nField <code>BYPASS</code> reader - Passes the reference clock to the …\nField <code>BYPASS</code> writer - Passes the reference clock to the …\nControl and Status GENERAL CONSTRAINTS: Reference clock …\nField <code>LOCK</code> reader - PLL is locked\nRegister <code>CS</code> reader\nField <code>REFDIV</code> reader - Divides the PLL input reference …\nField <code>REFDIV</code> writer - Divides the PLL input reference …\nRegister <code>CS</code> writer\nWrites raw bits to the register.\nBit 8 - Passes the reference clock to the output instead …\nBit 8 - Passes the reference clock to the output instead …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 31 - PLL is locked\nBits 0:5 - Divides the PLL input reference clock. …\nBits 0:5 - Divides the PLL input reference clock. …\nField <code>FBDIV_INT</code> reader - see ctrl reg description for …\nFeedback divisor (note: this PLL does not support …\nField <code>FBDIV_INT</code> writer - see ctrl reg description for …\nRegister <code>FBDIV_INT</code> reader\nRegister <code>FBDIV_INT</code> writer\nWrites raw bits to the register.\nBits 0:11 - see ctrl reg description for constraints\nBits 0:11 - see ctrl reg description for constraints\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>POSTDIV1</code> reader - divide by 1-7\nField <code>POSTDIV1</code> writer - divide by 1-7\nField <code>POSTDIV2</code> reader - divide by 1-7\nField <code>POSTDIV2</code> writer - divide by 1-7\nControls the PLL post dividers for the primary output …\nRegister <code>PRIM</code> reader\nRegister <code>PRIM</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 16:18 - divide by 1-7\nBits 16:18 - divide by 1-7\nBits 12:14 - divide by 1-7\nBits 12:14 - divide by 1-7\nField <code>DSMPD</code> reader - PLL DSM powerdown Nothing is achieved …\nField <code>DSMPD</code> writer - PLL DSM powerdown Nothing is achieved …\nField <code>PD</code> reader - PLL powerdown To save power set high …\nField <code>PD</code> writer - PLL powerdown To save power set high …\nField <code>POSTDIVPD</code> reader - PLL post divider powerdown To …\nField <code>POSTDIVPD</code> writer - PLL post divider powerdown To …\nControls the PLL power modes.\nRegister <code>PWR</code> reader\nField <code>VCOPD</code> reader - PLL VCO powerdown To save power set …\nField <code>VCOPD</code> writer - PLL VCO powerdown To save power set …\nRegister <code>PWR</code> writer\nWrites raw bits to the register.\nBit 2 - PLL DSM powerdown Nothing is achieved by setting …\nBit 2 - PLL DSM powerdown Nothing is achieved by setting …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - PLL powerdown To save power set high when PLL …\nBit 0 - PLL powerdown To save power set high when PLL …\nBit 3 - PLL post divider powerdown To save power set high …\nBit 3 - PLL post divider powerdown To save power set high …\nBit 5 - PLL VCO powerdown To save power set high when PLL …\nBit 5 - PLL VCO powerdown To save power set high when PLL …\nAIRCR (rw) register accessor: Use the Application …\nCCR (r) register accessor: The Configuration and Control …\nCPUID (r) register accessor: Read the CPU ID Base Register …\nICSR (rw) register accessor: Use the Interrupt Control …\nMPU_CTRL (rw) register accessor: Use the MPU Control …\nMPU_RASR (rw) register accessor: Use the MPU Region …\nMPU_RBAR (rw) register accessor: Read the MPU Region Base …\nMPU_RNR (rw) register accessor: Use the MPU Region Number …\nMPU_TYPE (r) register accessor: Read the MPU Type Register …\nNVIC_ICER (rw) register accessor: Use the Interrupt …\nNVIC_ICPR (rw) register accessor: Use the Interrupt …\nNVIC_IPR0 (rw) register accessor: Use the Interrupt …\nNVIC_IPR1 (rw) register accessor: Use the Interrupt …\nNVIC_IPR2 (rw) register accessor: Use the Interrupt …\nNVIC_IPR3 (rw) register accessor: Use the Interrupt …\nNVIC_IPR4 (rw) register accessor: Use the Interrupt …\nNVIC_IPR5 (rw) register accessor: Use the Interrupt …\nNVIC_IPR6 (rw) register accessor: Use the Interrupt …\nNVIC_IPR7 (rw) register accessor: Use the Interrupt …\nNVIC_ISER (rw) register accessor: Use the Interrupt …\nNVIC_ISPR (rw) register accessor: The NVIC_ISPR forces …\nRegister block\nSCR (rw) register accessor: System Control Register. Use …\nSHCSR (rw) register accessor: Use the System Handler …\nSHPR2 (rw) register accessor: System handlers are a …\nSHPR3 (rw) register accessor: System handlers are a …\nSYST_CALIB (r) register accessor: Use the SysTick …\nSYST_CSR (rw) register accessor: Use the SysTick Control …\nSYST_CVR (rw) register accessor: Use the SysTick Current …\nSYST_RVR (rw) register accessor: Use the SysTick Reload …\nVTOR (rw) register accessor: The VTOR holds the vector …\nUse the Application Interrupt and Reset Control Register …\n0xed0c - Use the Application Interrupt and Reset Control …\nThe Configuration and Control Register permanently enables …\n0xed14 - The Configuration and Control Register …\nRead the CPU ID Base Register to determine: the ID number …\n0xed00 - Read the CPU ID Base Register to determine: the …\nReturns the argument unchanged.\nUse the Interrupt Control State Register to set a pending …\n0xed04 - Use the Interrupt Control State Register to set a …\nCalls <code>U::from(self)</code>.\nUse the MPU Control Register to enable and disable the …\n0xed94 - Use the MPU Control Register to enable and …\nUse the MPU Region Attribute and Size Register to define …\n0xeda0 - Use the MPU Region Attribute and Size Register to …\nRead the MPU Region Base Address Register to determine the …\n0xed9c - Read the MPU Region Base Address Register to …\nUse the MPU Region Number Register to select the region …\n0xed98 - Use the MPU Region Number Register to select the …\nRead the MPU Type Register to determine if the processor …\n0xed90 - Read the MPU Type Register to determine if the …\nUse the Interrupt Clear-Enable Registers to disable …\n0xe180 - Use the Interrupt Clear-Enable Registers to …\nUse the Interrupt Clear-Pending Register to clear pending …\n0xe280 - Use the Interrupt Clear-Pending Register to clear …\nUse the Interrupt Priority Registers to assign a priority …\n0xe400 - Use the Interrupt Priority Registers to assign a …\nUse the Interrupt Priority Registers to assign a priority …\n0xe404 - Use the Interrupt Priority Registers to assign a …\nUse the Interrupt Priority Registers to assign a priority …\n0xe408 - Use the Interrupt Priority Registers to assign a …\nUse the Interrupt Priority Registers to assign a priority …\n0xe40c - Use the Interrupt Priority Registers to assign a …\nUse the Interrupt Priority Registers to assign a priority …\n0xe410 - Use the Interrupt Priority Registers to assign a …\nUse the Interrupt Priority Registers to assign a priority …\n0xe414 - Use the Interrupt Priority Registers to assign a …\nUse the Interrupt Priority Registers to assign a priority …\n0xe418 - Use the Interrupt Priority Registers to assign a …\nUse the Interrupt Priority Registers to assign a priority …\n0xe41c - Use the Interrupt Priority Registers to assign a …\nUse the Interrupt Set-Enable Register to enable interrupts …\n0xe100 - Use the Interrupt Set-Enable Register to enable …\nThe NVIC_ISPR forces interrupts into the pending state, …\n0xe200 - The NVIC_ISPR forces interrupts into the pending …\nSystem Control Register. Use the System Control Register …\n0xed10 - System Control Register. Use the System Control …\nUse the System Handler Control and State Register to …\n0xed24 - Use the System Handler Control and State Register …\nSystem handlers are a special class of exception handler …\n0xed1c - System handlers are a special class of exception …\nSystem handlers are a special class of exception handler …\n0xed20 - System handlers are a special class of exception …\nUse the SysTick Calibration Value Register to enable …\n0xe01c - Use the SysTick Calibration Value Register to …\nUse the SysTick Control and Status Register to enable the …\n0xe010 - Use the SysTick Control and Status Register to …\nUse the SysTick Current Value Register to find the current …\n0xe018 - Use the SysTick Current Value Register to find …\nUse the SysTick Reload Value Register to specify the start …\n0xe014 - Use the SysTick Reload Value Register to specify …\nThe VTOR holds the vector table offset address.\n0xed08 - The VTOR holds the vector table offset address.\nUse the Application Interrupt and Reset Control Register …\nField <code>ENDIANESS</code> reader - Data endianness implemented: 0 = …\nRegister <code>AIRCR</code> reader\nField <code>SYSRESETREQ</code> reader - Writing 1 to this bit causes …\nField <code>SYSRESETREQ</code> writer - Writing 1 to this bit causes …\nField <code>VECTCLRACTIVE</code> reader - Clears all active state …\nField <code>VECTCLRACTIVE</code> writer - Clears all active state …\nField <code>VECTKEY</code> reader - Register key: Reads as Unknown On …\nField <code>VECTKEY</code> writer - Register key: Reads as Unknown On …\nRegister <code>AIRCR</code> writer\nWrites raw bits to the register.\nBit 15 - Data endianness implemented: 0 = Little-endian.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 2 - Writing 1 to this bit causes the SYSRESETREQ …\nBit 2 - Writing 1 to this bit causes the SYSRESETREQ …\nBit 1 - Clears all active state information for fixed and …\nBit 1 - Clears all active state information for fixed and …\nBits 16:31 - Register key: Reads as Unknown On writes, …\nBits 16:31 - Register key: Reads as Unknown On writes, …\nThe Configuration and Control Register permanently enables …\nRegister <code>CCR</code> reader\nField <code>STKALIGN</code> reader - Always reads as one, indicates …\nField <code>UNALIGN_TRP</code> reader - Always reads as one, indicates …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 9 - Always reads as one, indicates 8-byte stack …\nBit 3 - Always reads as one, indicates that all unaligned …\nField <code>ARCHITECTURE</code> reader - Constant that defines the …\nRead the CPU ID Base Register to determine: the ID number …\nField <code>IMPLEMENTER</code> reader - Implementor code: 0x41 = ARM\nField <code>PARTNO</code> reader - Number of processor within family: …\nRegister <code>CPUID</code> reader\nField <code>REVISION</code> reader - Minor revision number m in the …\nField <code>VARIANT</code> reader - Major revision number n in the rnpm …\nBits 16:19 - Constant that defines the architecture of the …\nReturns the argument unchanged.\nBits 24:31 - Implementor code: 0x41 = ARM\nCalls <code>U::from(self)</code>.\nBits 4:15 - Number of processor within family: 0xC60 = …\nBits 0:3 - Minor revision number m in the rnpm revision …\nBits 20:23 - Major revision number n in the rnpm revision …\nUse the Interrupt Control State Register to set a pending …\nField <code>ISRPENDING</code> reader - External interrupt pending flag\nField <code>ISRPREEMPT</code> reader - The system can only access this …\nField <code>NMIPENDSET</code> reader - Setting this bit will activate …\nField <code>NMIPENDSET</code> writer - Setting this bit will activate …\nField <code>PENDSTCLR</code> reader - SysTick exception clear-pending …\nField <code>PENDSTCLR</code> writer - SysTick exception clear-pending …\nField <code>PENDSTSET</code> reader - SysTick exception set-pending bit.\nField <code>PENDSTSET</code> writer - SysTick exception set-pending bit.\nField <code>PENDSVCLR</code> reader - PendSV clear-pending bit. Write: …\nField <code>PENDSVCLR</code> writer - PendSV clear-pending bit. Write: …\nField <code>PENDSVSET</code> reader - PendSV set-pending bit. Write: 0 …\nField <code>PENDSVSET</code> writer - PendSV set-pending bit. Write: 0 …\nRegister <code>ICSR</code> reader\nField <code>VECTACTIVE</code> reader - Active exception number field. …\nField <code>VECTPENDING</code> reader - Indicates the exception number …\nRegister <code>ICSR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 22 - External interrupt pending flag\nBit 23 - The system can only access this bit when the core …\nBit 31 - Setting this bit will activate an NMI. Since NMI …\nBit 31 - Setting this bit will activate an NMI. Since NMI …\nBit 25 - SysTick exception clear-pending bit. Write: 0 = …\nBit 25 - SysTick exception clear-pending bit. Write: 0 = …\nBit 26 - SysTick exception set-pending bit. Write: 0 = No …\nBit 26 - SysTick exception set-pending bit. Write: 0 = No …\nBit 27 - PendSV clear-pending bit. Write: 0 = No effect. 1 …\nBit 27 - PendSV clear-pending bit. Write: 0 = No effect. 1 …\nBit 28 - PendSV set-pending bit. Write: 0 = No effect. 1 = …\nBit 28 - PendSV set-pending bit. Write: 0 = No effect. 1 = …\nBits 0:8 - Active exception number field. Reset clears the …\nBits 12:20 - Indicates the exception number for the …\nField <code>ENABLE</code> reader - Enables the MPU. If the MPU is …\nField <code>ENABLE</code> writer - Enables the MPU. If the MPU is …\nField <code>HFNMIENA</code> reader - Controls the use of the MPU for …\nField <code>HFNMIENA</code> writer - Controls the use of the MPU for …\nUse the MPU Control Register to enable and disable the …\nField <code>PRIVDEFENA</code> reader - Controls whether the default …\nField <code>PRIVDEFENA</code> writer - Controls whether the default …\nRegister <code>MPU_CTRL</code> reader\nRegister <code>MPU_CTRL</code> writer\nWrites raw bits to the register.\nBit 0 - Enables the MPU. If the MPU is disabled, …\nBit 0 - Enables the MPU. If the MPU is disabled, …\nReturns the argument unchanged.\nBit 1 - Controls the use of the MPU for HardFaults and …\nBit 1 - Controls the use of the MPU for HardFaults and …\nCalls <code>U::from(self)</code>.\nBit 2 - Controls whether the default memory map is enabled …\nBit 2 - Controls whether the default memory map is enabled …\nField <code>ATTRS</code> reader - The MPU Region Attribute field. Use …\nField <code>ATTRS</code> writer - The MPU Region Attribute field. Use …\nField <code>ENABLE</code> reader - Enables the region.\nField <code>ENABLE</code> writer - Enables the region.\nUse the MPU Region Attribute and Size Register to define …\nRegister <code>MPU_RASR</code> reader\nField <code>SIZE</code> reader - Indicates the region size. Region size …\nField <code>SIZE</code> writer - Indicates the region size. Region size …\nField <code>SRD</code> reader - Subregion Disable. For regions of 256 …\nField <code>SRD</code> writer - Subregion Disable. For regions of 256 …\nRegister <code>MPU_RASR</code> writer\nBits 16:31 - The MPU Region Attribute field. Use to define …\nBits 16:31 - The MPU Region Attribute field. Use to define …\nWrites raw bits to the register.\nBit 0 - Enables the region.\nBit 0 - Enables the region.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 1:5 - Indicates the region size. Region size in bytes …\nBits 1:5 - Indicates the region size. Region size in bytes …\nBits 8:15 - Subregion Disable. For regions of 256 bytes or …\nBits 8:15 - Subregion Disable. For regions of 256 bytes or …\nField <code>ADDR</code> reader - Base address of the region.\nField <code>ADDR</code> writer - Base address of the region.\nRead the MPU Region Base Address Register to determine the …\nRegister <code>MPU_RBAR</code> reader\nField <code>REGION</code> reader - On writes, specifies the number of …\nField <code>REGION</code> writer - On writes, specifies the number of …\nField <code>VALID</code> reader - On writes, indicates whether the …\nField <code>VALID</code> writer - On writes, indicates whether the …\nRegister <code>MPU_RBAR</code> writer\nBits 8:31 - Base address of the region.\nBits 8:31 - Base address of the region.\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:3 - On writes, specifies the number of the region …\nBits 0:3 - On writes, specifies the number of the region …\nBit 4 - On writes, indicates whether the write must update …\nBit 4 - On writes, indicates whether the write must update …\nUse the MPU Region Number Register to select the region …\nRegister <code>MPU_RNR</code> reader\nField <code>REGION</code> reader - Indicates the MPU region referenced …\nField <code>REGION</code> writer - Indicates the MPU region referenced …\nRegister <code>MPU_RNR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:3 - Indicates the MPU region referenced by the …\nBits 0:3 - Indicates the MPU region referenced by the …\nField <code>DREGION</code> reader - Number of regions supported by the …\nField <code>IREGION</code> reader - Instruction region. Reads as zero …\nRead the MPU Type Register to determine if the processor …\nRegister <code>MPU_TYPE</code> reader\nField <code>SEPARATE</code> reader - Indicates support for separate …\nBits 8:15 - Number of regions supported by the MPU.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 16:23 - Instruction region. Reads as zero as ARMv6-M …\nBit 0 - Indicates support for separate instruction and …\nField <code>CLRENA</code> reader - Interrupt clear-enable bits. Write: …\nField <code>CLRENA</code> writer - Interrupt clear-enable bits. Write: …\nUse the Interrupt Clear-Enable Registers to disable …\nRegister <code>NVIC_ICER</code> reader\nRegister <code>NVIC_ICER</code> writer\nWrites raw bits to the register.\nBits 0:31 - Interrupt clear-enable bits. Write: 0 = No …\nBits 0:31 - Interrupt clear-enable bits. Write: 0 = No …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLRPEND</code> reader - Interrupt clear-pending bits. Write:\nField <code>CLRPEND</code> writer - Interrupt clear-pending bits. Write:\nUse the Interrupt Clear-Pending Register to clear pending …\nRegister <code>NVIC_ICPR</code> reader\nRegister <code>NVIC_ICPR</code> writer\nWrites raw bits to the register.\nBits 0:31 - Interrupt clear-pending bits. Write: 0 = No …\nBits 0:31 - Interrupt clear-pending bits. Write: 0 = No …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>IP_0</code> reader - Priority of interrupt 0\nField <code>IP_0</code> writer - Priority of interrupt 0\nField <code>IP_1</code> reader - Priority of interrupt 1\nField <code>IP_1</code> writer - Priority of interrupt 1\nField <code>IP_2</code> reader - Priority of interrupt 2\nField <code>IP_2</code> writer - Priority of interrupt 2\nField <code>IP_3</code> reader - Priority of interrupt 3\nField <code>IP_3</code> writer - Priority of interrupt 3\nUse the Interrupt Priority Registers to assign a priority …\nRegister <code>NVIC_IPR0</code> reader\nRegister <code>NVIC_IPR0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 6:7 - Priority of interrupt 0\nBits 6:7 - Priority of interrupt 0\nBits 14:15 - Priority of interrupt 1\nBits 14:15 - Priority of interrupt 1\nBits 22:23 - Priority of interrupt 2\nBits 22:23 - Priority of interrupt 2\nBits 30:31 - Priority of interrupt 3\nBits 30:31 - Priority of interrupt 3\nField <code>IP_4</code> reader - Priority of interrupt 4\nField <code>IP_4</code> writer - Priority of interrupt 4\nField <code>IP_5</code> reader - Priority of interrupt 5\nField <code>IP_5</code> writer - Priority of interrupt 5\nField <code>IP_6</code> reader - Priority of interrupt 6\nField <code>IP_6</code> writer - Priority of interrupt 6\nField <code>IP_7</code> reader - Priority of interrupt 7\nField <code>IP_7</code> writer - Priority of interrupt 7\nUse the Interrupt Priority Registers to assign a priority …\nRegister <code>NVIC_IPR1</code> reader\nRegister <code>NVIC_IPR1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 6:7 - Priority of interrupt 4\nBits 6:7 - Priority of interrupt 4\nBits 14:15 - Priority of interrupt 5\nBits 14:15 - Priority of interrupt 5\nBits 22:23 - Priority of interrupt 6\nBits 22:23 - Priority of interrupt 6\nBits 30:31 - Priority of interrupt 7\nBits 30:31 - Priority of interrupt 7\nField <code>IP_10</code> reader - Priority of interrupt 10\nField <code>IP_10</code> writer - Priority of interrupt 10\nField <code>IP_11</code> reader - Priority of interrupt 11\nField <code>IP_11</code> writer - Priority of interrupt 11\nField <code>IP_8</code> reader - Priority of interrupt 8\nField <code>IP_8</code> writer - Priority of interrupt 8\nField <code>IP_9</code> reader - Priority of interrupt 9\nField <code>IP_9</code> writer - Priority of interrupt 9\nUse the Interrupt Priority Registers to assign a priority …\nRegister <code>NVIC_IPR2</code> reader\nRegister <code>NVIC_IPR2</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 22:23 - Priority of interrupt 10\nBits 22:23 - Priority of interrupt 10\nBits 30:31 - Priority of interrupt 11\nBits 30:31 - Priority of interrupt 11\nBits 6:7 - Priority of interrupt 8\nBits 6:7 - Priority of interrupt 8\nBits 14:15 - Priority of interrupt 9\nBits 14:15 - Priority of interrupt 9\nField <code>IP_12</code> reader - Priority of interrupt 12\nField <code>IP_12</code> writer - Priority of interrupt 12\nField <code>IP_13</code> reader - Priority of interrupt 13\nField <code>IP_13</code> writer - Priority of interrupt 13\nField <code>IP_14</code> reader - Priority of interrupt 14\nField <code>IP_14</code> writer - Priority of interrupt 14\nField <code>IP_15</code> reader - Priority of interrupt 15\nField <code>IP_15</code> writer - Priority of interrupt 15\nUse the Interrupt Priority Registers to assign a priority …\nRegister <code>NVIC_IPR3</code> reader\nRegister <code>NVIC_IPR3</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 6:7 - Priority of interrupt 12\nBits 6:7 - Priority of interrupt 12\nBits 14:15 - Priority of interrupt 13\nBits 14:15 - Priority of interrupt 13\nBits 22:23 - Priority of interrupt 14\nBits 22:23 - Priority of interrupt 14\nBits 30:31 - Priority of interrupt 15\nBits 30:31 - Priority of interrupt 15\nField <code>IP_16</code> reader - Priority of interrupt 16\nField <code>IP_16</code> writer - Priority of interrupt 16\nField <code>IP_17</code> reader - Priority of interrupt 17\nField <code>IP_17</code> writer - Priority of interrupt 17\nField <code>IP_18</code> reader - Priority of interrupt 18\nField <code>IP_18</code> writer - Priority of interrupt 18\nField <code>IP_19</code> reader - Priority of interrupt 19\nField <code>IP_19</code> writer - Priority of interrupt 19\nUse the Interrupt Priority Registers to assign a priority …\nRegister <code>NVIC_IPR4</code> reader\nRegister <code>NVIC_IPR4</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 6:7 - Priority of interrupt 16\nBits 6:7 - Priority of interrupt 16\nBits 14:15 - Priority of interrupt 17\nBits 14:15 - Priority of interrupt 17\nBits 22:23 - Priority of interrupt 18\nBits 22:23 - Priority of interrupt 18\nBits 30:31 - Priority of interrupt 19\nBits 30:31 - Priority of interrupt 19\nField <code>IP_20</code> reader - Priority of interrupt 20\nField <code>IP_20</code> writer - Priority of interrupt 20\nField <code>IP_21</code> reader - Priority of interrupt 21\nField <code>IP_21</code> writer - Priority of interrupt 21\nField <code>IP_22</code> reader - Priority of interrupt 22\nField <code>IP_22</code> writer - Priority of interrupt 22\nField <code>IP_23</code> reader - Priority of interrupt 23\nField <code>IP_23</code> writer - Priority of interrupt 23\nUse the Interrupt Priority Registers to assign a priority …\nRegister <code>NVIC_IPR5</code> reader\nRegister <code>NVIC_IPR5</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 6:7 - Priority of interrupt 20\nBits 6:7 - Priority of interrupt 20\nBits 14:15 - Priority of interrupt 21\nBits 14:15 - Priority of interrupt 21\nBits 22:23 - Priority of interrupt 22\nBits 22:23 - Priority of interrupt 22\nBits 30:31 - Priority of interrupt 23\nBits 30:31 - Priority of interrupt 23\nField <code>IP_24</code> reader - Priority of interrupt 24\nField <code>IP_24</code> writer - Priority of interrupt 24\nField <code>IP_25</code> reader - Priority of interrupt 25\nField <code>IP_25</code> writer - Priority of interrupt 25\nField <code>IP_26</code> reader - Priority of interrupt 26\nField <code>IP_26</code> writer - Priority of interrupt 26\nField <code>IP_27</code> reader - Priority of interrupt 27\nField <code>IP_27</code> writer - Priority of interrupt 27\nUse the Interrupt Priority Registers to assign a priority …\nRegister <code>NVIC_IPR6</code> reader\nRegister <code>NVIC_IPR6</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 6:7 - Priority of interrupt 24\nBits 6:7 - Priority of interrupt 24\nBits 14:15 - Priority of interrupt 25\nBits 14:15 - Priority of interrupt 25\nBits 22:23 - Priority of interrupt 26\nBits 22:23 - Priority of interrupt 26\nBits 30:31 - Priority of interrupt 27\nBits 30:31 - Priority of interrupt 27\nField <code>IP_28</code> reader - Priority of interrupt 28\nField <code>IP_28</code> writer - Priority of interrupt 28\nField <code>IP_29</code> reader - Priority of interrupt 29\nField <code>IP_29</code> writer - Priority of interrupt 29\nField <code>IP_30</code> reader - Priority of interrupt 30\nField <code>IP_30</code> writer - Priority of interrupt 30\nField <code>IP_31</code> reader - Priority of interrupt 31\nField <code>IP_31</code> writer - Priority of interrupt 31\nUse the Interrupt Priority Registers to assign a priority …\nRegister <code>NVIC_IPR7</code> reader\nRegister <code>NVIC_IPR7</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 6:7 - Priority of interrupt 28\nBits 6:7 - Priority of interrupt 28\nBits 14:15 - Priority of interrupt 29\nBits 14:15 - Priority of interrupt 29\nBits 22:23 - Priority of interrupt 30\nBits 22:23 - Priority of interrupt 30\nBits 30:31 - Priority of interrupt 31\nBits 30:31 - Priority of interrupt 31\nUse the Interrupt Set-Enable Register to enable interrupts …\nRegister <code>NVIC_ISER</code> reader\nField <code>SETENA</code> reader - Interrupt set-enable bits. Write: 0 …\nField <code>SETENA</code> writer - Interrupt set-enable bits. Write: 0 …\nRegister <code>NVIC_ISER</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:31 - Interrupt set-enable bits. Write: 0 = No …\nBits 0:31 - Interrupt set-enable bits. Write: 0 = No …\nThe NVIC_ISPR forces interrupts into the pending state, …\nRegister <code>NVIC_ISPR</code> reader\nField <code>SETPEND</code> reader - Interrupt set-pending bits. Write: …\nField <code>SETPEND</code> writer - Interrupt set-pending bits. Write: …\nRegister <code>NVIC_ISPR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:31 - Interrupt set-pending bits. Write: 0 = No …\nBits 0:31 - Interrupt set-pending bits. Write: 0 = No …\nRegister <code>SCR</code> reader\nSystem Control Register. Use the System Control Register …\nField <code>SEVONPEND</code> reader - Send Event on Pending bit: 0 = …\nField <code>SEVONPEND</code> writer - Send Event on Pending bit: 0 = …\nField <code>SLEEPDEEP</code> reader - Controls whether the processor …\nField <code>SLEEPDEEP</code> writer - Controls whether the processor …\nField <code>SLEEPONEXIT</code> reader - Indicates sleep-on-exit when …\nField <code>SLEEPONEXIT</code> writer - Indicates sleep-on-exit when …\nRegister <code>SCR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 4 - Send Event on Pending bit: 0 = Only enabled …\nBit 4 - Send Event on Pending bit: 0 = Only enabled …\nBit 2 - Controls whether the processor uses sleep or deep …\nBit 2 - Controls whether the processor uses sleep or deep …\nBit 1 - Indicates sleep-on-exit when returning from …\nBit 1 - Indicates sleep-on-exit when returning from …\nRegister <code>SHCSR</code> reader\nUse the System Handler Control and State Register to …\nField <code>SVCALLPENDED</code> reader - Reads as 1 if SVCall is …\nField <code>SVCALLPENDED</code> writer - Reads as 1 if SVCall is …\nRegister <code>SHCSR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 15 - Reads as 1 if SVCall is Pending. Write 1 to set …\nBit 15 - Reads as 1 if SVCall is Pending. Write 1 to set …\nField <code>PRI_11</code> reader - Priority of system handler 11, SVCall\nField <code>PRI_11</code> writer - Priority of system handler 11, SVCall\nRegister <code>SHPR2</code> reader\nSystem handlers are a special class of exception handler …\nRegister <code>SHPR2</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 30:31 - Priority of system handler 11, SVCall\nBits 30:31 - Priority of system handler 11, SVCall\nField <code>PRI_14</code> reader - Priority of system handler 14, PendSV\nField <code>PRI_14</code> writer - Priority of system handler 14, PendSV\nField <code>PRI_15</code> reader - Priority of system handler 15, …\nField <code>PRI_15</code> writer - Priority of system handler 15, …\nRegister <code>SHPR3</code> reader\nSystem handlers are a special class of exception handler …\nRegister <code>SHPR3</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 22:23 - Priority of system handler 14, PendSV\nBits 22:23 - Priority of system handler 14, PendSV\nBits 30:31 - Priority of system handler 15, SysTick\nBits 30:31 - Priority of system handler 15, SysTick\nField <code>NOREF</code> reader - If reads as 1, the Reference clock is …\nRegister <code>SYST_CALIB</code> reader\nField <code>SKEW</code> reader - If reads as 1, the calibration value …\nUse the SysTick Calibration Value Register to enable …\nField <code>TENMS</code> reader - An optional Reload value to be used …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 31 - If reads as 1, the Reference clock is not …\nBit 30 - If reads as 1, the calibration value for 10ms is …\nBits 0:23 - An optional Reload value to be used for 10ms …\nField <code>CLKSOURCE</code> reader - SysTick clock source. Always …\nField <code>CLKSOURCE</code> writer - SysTick clock source. Always …\nField <code>COUNTFLAG</code> reader - Returns 1 if timer counted to 0 …\nField <code>ENABLE</code> reader - Enable SysTick counter: 0 = Counter …\nField <code>ENABLE</code> writer - Enable SysTick counter: 0 = Counter …\nRegister <code>SYST_CSR</code> reader\nUse the SysTick Control and Status Register to enable the …\nField <code>TICKINT</code> reader - Enables SysTick exception request: …\nField <code>TICKINT</code> writer - Enables SysTick exception request: …\nRegister <code>SYST_CSR</code> writer\nWrites raw bits to the register.\nBit 2 - SysTick clock source. Always reads as one if …\nBit 2 - SysTick clock source. Always reads as one if …\nBit 16 - Returns 1 if timer counted to 0 since last time …\nBit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = …\nBit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 1 - Enables SysTick exception request: 0 = Counting …\nBit 1 - Enables SysTick exception request: 0 = Counting …\nField <code>CURRENT</code> reader - Reads return the current value of …\nField <code>CURRENT</code> writer - Reads return the current value of …\nRegister <code>SYST_CVR</code> reader\nUse the SysTick Current Value Register to find the current …\nRegister <code>SYST_CVR</code> writer\nWrites raw bits to the register.\nBits 0:23 - Reads return the current value of the SysTick …\nBits 0:23 - Reads return the current value of the SysTick …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SYST_RVR</code> reader\nField <code>RELOAD</code> reader - Value to load into the SysTick …\nField <code>RELOAD</code> writer - Value to load into the SysTick …\nUse the SysTick Reload Value Register to specify the start …\nRegister <code>SYST_RVR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:23 - Value to load into the SysTick Current Value …\nBits 0:23 - Value to load into the SysTick Current Value …\nRegister <code>VTOR</code> reader\nField <code>TBLOFF</code> reader - Bits [31:8] of the indicate the …\nField <code>TBLOFF</code> writer - Bits [31:8] of the indicate the …\nThe VTOR holds the vector table offset address.\nRegister <code>VTOR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 8:31 - Bits [31:8] of the indicate the vector table …\nBits 8:31 - Bits [31:8] of the indicate the vector table …\nDONE (r) register accessor: Indicates the peripheral’s …\nFRCE_OFF (rw) register accessor: Force into reset (i.e. …\nFRCE_ON (rw) register accessor: Force block out of reset …\nRegister block\nWDSEL (rw) register accessor: Set to 1 if this peripheral …\nIndicates the peripheral’s registers are ready to access.\n0x0c - Indicates the peripheral’s registers are ready to …\nForce into reset (i.e. power it off)\n0x04 - Force into reset (i.e. power it off)\nForce block out of reset (i.e. power it on)\n0x00 - Force block out of reset (i.e. power it on)\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nSet to 1 if this peripheral should be reset when the …\n0x08 - Set to 1 if this peripheral should be reset when …\nField <code>busfabric</code> reader -\nField <code>clocks</code> reader -\nIndicates the peripheral’s registers are ready to access.\nField <code>proc0</code> reader -\nField <code>proc1</code> reader -\nRegister <code>DONE</code> reader\nField <code>resets</code> reader -\nField <code>rom</code> reader -\nField <code>rosc</code> reader -\nField <code>sio</code> reader -\nField <code>sram0</code> reader -\nField <code>sram1</code> reader -\nField <code>sram2</code> reader -\nField <code>sram3</code> reader -\nField <code>sram4</code> reader -\nField <code>sram5</code> reader -\nField <code>vreg_and_chip_reset</code> reader -\nField <code>xip</code> reader -\nField <code>xosc</code> reader -\nBit 4\nBit 2\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 15\nBit 16\nBit 3\nBit 5\nBit 0\nBit 14\nBit 6\nBit 7\nBit 8\nBit 9\nBit 10\nBit 11\nBit 13\nBit 12\nBit 1\nField <code>busfabric</code> reader -\nField <code>busfabric</code> writer -\nField <code>clocks</code> reader -\nField <code>clocks</code> writer -\nForce into reset (i.e. power it off)\nField <code>proc0</code> reader -\nField <code>proc0</code> writer -\nField <code>proc1</code> reader -\nField <code>proc1</code> writer -\nRegister <code>FRCE_OFF</code> reader\nField <code>resets</code> reader -\nField <code>resets</code> writer -\nField <code>rom</code> reader -\nField <code>rom</code> writer -\nField <code>rosc</code> reader -\nField <code>rosc</code> writer -\nField <code>sio</code> reader -\nField <code>sio</code> writer -\nField <code>sram0</code> reader -\nField <code>sram0</code> writer -\nField <code>sram1</code> reader -\nField <code>sram1</code> writer -\nField <code>sram2</code> reader -\nField <code>sram2</code> writer -\nField <code>sram3</code> reader -\nField <code>sram3</code> writer -\nField <code>sram4</code> reader -\nField <code>sram4</code> writer -\nField <code>sram5</code> reader -\nField <code>sram5</code> writer -\nField <code>vreg_and_chip_reset</code> reader -\nField <code>vreg_and_chip_reset</code> writer -\nRegister <code>FRCE_OFF</code> writer\nField <code>xip</code> reader -\nField <code>xip</code> writer -\nField <code>xosc</code> reader -\nField <code>xosc</code> writer -\nWrites raw bits to the register.\nBit 4\nBit 4\nBit 2\nBit 2\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 15\nBit 15\nBit 16\nBit 16\nBit 3\nBit 3\nBit 5\nBit 5\nBit 0\nBit 0\nBit 14\nBit 14\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 13\nBit 13\nBit 12\nBit 12\nBit 1\nBit 1\nField <code>busfabric</code> reader -\nField <code>busfabric</code> writer -\nField <code>clocks</code> reader -\nField <code>clocks</code> writer -\nForce block out of reset (i.e. power it on)\nField <code>proc0</code> reader -\nField <code>proc0</code> writer -\nField <code>proc1</code> reader -\nField <code>proc1</code> writer -\nRegister <code>FRCE_ON</code> reader\nField <code>resets</code> reader -\nField <code>resets</code> writer -\nField <code>rom</code> reader -\nField <code>rom</code> writer -\nField <code>rosc</code> reader -\nField <code>rosc</code> writer -\nField <code>sio</code> reader -\nField <code>sio</code> writer -\nField <code>sram0</code> reader -\nField <code>sram0</code> writer -\nField <code>sram1</code> reader -\nField <code>sram1</code> writer -\nField <code>sram2</code> reader -\nField <code>sram2</code> writer -\nField <code>sram3</code> reader -\nField <code>sram3</code> writer -\nField <code>sram4</code> reader -\nField <code>sram4</code> writer -\nField <code>sram5</code> reader -\nField <code>sram5</code> writer -\nField <code>vreg_and_chip_reset</code> reader -\nField <code>vreg_and_chip_reset</code> writer -\nRegister <code>FRCE_ON</code> writer\nField <code>xip</code> reader -\nField <code>xip</code> writer -\nField <code>xosc</code> reader -\nField <code>xosc</code> writer -\nWrites raw bits to the register.\nBit 4\nBit 4\nBit 2\nBit 2\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 15\nBit 15\nBit 16\nBit 16\nBit 3\nBit 3\nBit 5\nBit 5\nBit 0\nBit 0\nBit 14\nBit 14\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 13\nBit 13\nBit 12\nBit 12\nBit 1\nBit 1\nField <code>busfabric</code> reader -\nField <code>busfabric</code> writer -\nField <code>clocks</code> reader -\nField <code>clocks</code> writer -\nField <code>proc0</code> reader -\nField <code>proc0</code> writer -\nField <code>proc1</code> reader -\nField <code>proc1</code> writer -\nRegister <code>WDSEL</code> reader\nField <code>resets</code> reader -\nField <code>resets</code> writer -\nField <code>rom</code> reader -\nField <code>rom</code> writer -\nField <code>rosc</code> reader -\nField <code>rosc</code> writer -\nField <code>sio</code> reader -\nField <code>sio</code> writer -\nField <code>sram0</code> reader -\nField <code>sram0</code> writer -\nField <code>sram1</code> reader -\nField <code>sram1</code> writer -\nField <code>sram2</code> reader -\nField <code>sram2</code> writer -\nField <code>sram3</code> reader -\nField <code>sram3</code> writer -\nField <code>sram4</code> reader -\nField <code>sram4</code> writer -\nField <code>sram5</code> reader -\nField <code>sram5</code> writer -\nField <code>vreg_and_chip_reset</code> reader -\nField <code>vreg_and_chip_reset</code> writer -\nRegister <code>WDSEL</code> writer\nSet to 1 if this peripheral should be reset when the …\nField <code>xip</code> reader -\nField <code>xip</code> writer -\nField <code>xosc</code> reader -\nField <code>xosc</code> writer -\nWrites raw bits to the register.\nBit 4\nBit 4\nBit 2\nBit 2\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 15\nBit 15\nBit 16\nBit 16\nBit 3\nBit 3\nBit 5\nBit 5\nBit 0\nBit 0\nBit 14\nBit 14\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 13\nBit 13\nBit 12\nBit 12\nBit 1\nBit 1\nCluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_…\nEN (rw) register accessor: This register aliases the …\nINTE (rw) register accessor: Interrupt Enable\nINTF (rw) register accessor: Interrupt Force\nINTR (rw) register accessor: Raw Interrupts\nINTS (r) register accessor: Interrupt status after masking …\nRegister block\nCluster Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, …\n0x00..0xa0 - Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_…\nIterator for array of: 0x00..0xa0 - Cluster CH%s, …\nThis register aliases the CSR_EN bits for all channels. …\n0xa0 - This register aliases the CSR_EN bits for all …\nReturns the argument unchanged.\nInterrupt Enable\n0xa8 - Interrupt Enable\nInterrupt Force\n0xac - Interrupt Force\nCalls <code>U::from(self)</code>.\nRaw Interrupts\n0xa4 - Raw Interrupts\nInterrupt status after masking &amp; forcing\n0xb0 - Interrupt status after masking &amp; forcing\nCC (rw) register accessor: Counter compare values\nRegister block\nCSR (rw) register accessor: Control and status register\nCTR (rw) register accessor: Direct access to the PWM …\nDIV (rw) register accessor: INT and FRAC form a …\nTOP (rw) register accessor: Counter wrap value\nCounter compare values\n0x0c - Counter compare values\nControl and status register\n0x00 - Control and status register\nDirect access to the PWM counter\n0x08 - Direct access to the PWM counter\nINT and FRAC form a fixed-point fractional number. …\n0x04 - INT and FRAC form a fixed-point fractional number. …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCounter wrap value\n0x10 - Counter wrap value\nField <code>A</code> reader -\nField <code>A</code> writer -\nField <code>B</code> reader -\nField <code>B</code> writer -\nCounter compare values\nRegister <code>CC</code> reader\nRegister <code>CC</code> writer\nBits 0:15\nBits 0:15\nBits 16:31\nBits 16:31\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>A_INV</code> reader - Invert output A\nField <code>A_INV</code> writer - Invert output A\nField <code>B_INV</code> reader - Invert output B\nField <code>B_INV</code> writer - Invert output B\nControl and status register\n0: Free-running counting at rate dictated by fractional …\nValue on reset: 0\nField <code>DIVMODE</code> reader -\nField <code>DIVMODE</code> writer -\nField <code>EN</code> reader - Enable the PWM channel.\nField <code>EN</code> writer - Enable the PWM channel.\n3: Counter advances with each falling edge of the PWM B …\n1: Fractional divider operation is gated by the PWM B pin.\nField <code>PH_ADV</code> reader - Advance the phase of the counter by …\nField <code>PH_ADV</code> writer - Advance the phase of the counter by …\nField <code>PH_CORRECT</code> reader - 1: Enable phase-correct …\nField <code>PH_CORRECT</code> writer - 1: Enable phase-correct …\nField <code>PH_RET</code> reader - Retard the phase of the counter by 1 …\nField <code>PH_RET</code> writer - Retard the phase of the counter by 1 …\nRegister <code>CSR</code> reader\n2: Counter advances with each rising edge of the PWM B pin.\nRegister <code>CSR</code> writer\nBit 2 - Invert output A\nBit 2 - Invert output A\nBit 3 - Invert output B\nBit 3 - Invert output B\nWrites raw bits to the register.\nFree-running counting at rate dictated by fractional …\nBits 4:5\nBits 4:5\nBit 0 - Enable the PWM channel.\nBit 0 - Enable the PWM channel.\nCounter advances with each falling edge of the PWM B pin.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nFree-running counting at rate dictated by fractional …\nCounter advances with each falling edge of the PWM B pin.\nFractional divider operation is gated by the PWM B pin.\nCounter advances with each rising edge of the PWM B pin.\nFractional divider operation is gated by the PWM B pin.\nBit 7 - Advance the phase of the counter by 1 count, while …\nBit 7 - Advance the phase of the counter by 1 count, while …\nBit 1 - 1: Enable phase-correct modulation. 0: …\nBit 1 - 1: Enable phase-correct modulation. 0: …\nBit 6 - Retard the phase of the counter by 1 count, while …\nBit 6 - Retard the phase of the counter by 1 count, while …\nCounter advances with each rising edge of the PWM B pin.\nGet enumerated values variant\nField <code>CTR</code> reader -\nDirect access to the PWM counter\nField <code>CTR</code> writer -\nRegister <code>CTR</code> reader\nRegister <code>CTR</code> writer\nWrites raw bits to the register.\nBits 0:15\nBits 0:15\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nINT and FRAC form a fixed-point fractional number. …\nField <code>FRAC</code> reader -\nField <code>FRAC</code> writer -\nField <code>INT</code> reader -\nField <code>INT</code> writer -\nRegister <code>DIV</code> reader\nRegister <code>DIV</code> writer\nWrites raw bits to the register.\nBits 0:3\nBits 0:3\nReturns the argument unchanged.\nBits 4:11\nBits 4:11\nCalls <code>U::from(self)</code>.\nRegister <code>TOP</code> reader\nField <code>TOP</code> reader -\nCounter wrap value\nField <code>TOP</code> writer -\nRegister <code>TOP</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15\nBits 0:15\nField <code>CH0</code> reader -\nField <code>CH0</code> writer -\nField <code>CH1</code> reader -\nField <code>CH1</code> writer -\nField <code>CH2</code> reader -\nField <code>CH2</code> writer -\nField <code>CH3</code> reader -\nField <code>CH3</code> writer -\nField <code>CH4</code> reader -\nField <code>CH4</code> writer -\nField <code>CH5</code> reader -\nField <code>CH5</code> writer -\nField <code>CH6</code> reader -\nField <code>CH6</code> writer -\nField <code>CH7</code> reader -\nField <code>CH7</code> writer -\nThis register aliases the CSR_EN bits for all channels. …\nRegister <code>EN</code> reader\nRegister <code>EN</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CH0</code> reader -\nField <code>CH0</code> writer -\nField <code>CH1</code> reader -\nField <code>CH1</code> writer -\nField <code>CH2</code> reader -\nField <code>CH2</code> writer -\nField <code>CH3</code> reader -\nField <code>CH3</code> writer -\nField <code>CH4</code> reader -\nField <code>CH4</code> writer -\nField <code>CH5</code> reader -\nField <code>CH5</code> writer -\nField <code>CH6</code> reader -\nField <code>CH6</code> writer -\nField <code>CH7</code> reader -\nField <code>CH7</code> writer -\nInterrupt Enable\nRegister <code>INTE</code> reader\nRegister <code>INTE</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CH0</code> reader -\nField <code>CH0</code> writer -\nField <code>CH1</code> reader -\nField <code>CH1</code> writer -\nField <code>CH2</code> reader -\nField <code>CH2</code> writer -\nField <code>CH3</code> reader -\nField <code>CH3</code> writer -\nField <code>CH4</code> reader -\nField <code>CH4</code> writer -\nField <code>CH5</code> reader -\nField <code>CH5</code> writer -\nField <code>CH6</code> reader -\nField <code>CH6</code> writer -\nField <code>CH7</code> reader -\nField <code>CH7</code> writer -\nInterrupt Force\nRegister <code>INTF</code> reader\nRegister <code>INTF</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CH0</code> reader -\nField <code>CH0</code> writer -\nField <code>CH1</code> reader -\nField <code>CH1</code> writer -\nField <code>CH2</code> reader -\nField <code>CH2</code> writer -\nField <code>CH3</code> reader -\nField <code>CH3</code> writer -\nField <code>CH4</code> reader -\nField <code>CH4</code> writer -\nField <code>CH5</code> reader -\nField <code>CH5</code> writer -\nField <code>CH6</code> reader -\nField <code>CH6</code> writer -\nField <code>CH7</code> reader -\nField <code>CH7</code> writer -\nRaw Interrupts\nRegister <code>INTR</code> reader\nRegister <code>INTR</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CH0</code> reader -\nField <code>CH1</code> reader -\nField <code>CH2</code> reader -\nField <code>CH3</code> reader -\nField <code>CH4</code> reader -\nField <code>CH5</code> reader -\nField <code>CH6</code> reader -\nField <code>CH7</code> reader -\nInterrupt status after masking &amp; forcing\nRegister <code>INTS</code> reader\nBit 0\nBit 1\nBit 2\nBit 3\nBit 4\nBit 5\nBit 6\nBit 7\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRESET (rw) register accessor: Reset control. If a bit is …\nRESET_DONE (r) register accessor: Reset done. If a bit is …\nRegister block\nWDSEL (rw) register accessor: Watchdog select. If a bit is …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nReset control. If a bit is set it means the peripheral is …\n0x00 - Reset control. If a bit is set it means the …\nReset done. If a bit is set then a reset done signal has …\n0x08 - Reset done. If a bit is set then a reset done …\nWatchdog select. If a bit is set then the watchdog will …\n0x04 - Watchdog select. If a bit is set then the watchdog …\nField <code>adc</code> reader -\nField <code>adc</code> writer -\nField <code>busctrl</code> reader -\nField <code>busctrl</code> writer -\nField <code>dma</code> reader -\nField <code>dma</code> writer -\nField <code>i2c0</code> reader -\nField <code>i2c0</code> writer -\nField <code>i2c1</code> reader -\nField <code>i2c1</code> writer -\nField <code>io_bank0</code> reader -\nField <code>io_bank0</code> writer -\nField <code>io_qspi</code> reader -\nField <code>io_qspi</code> writer -\nField <code>jtag</code> reader -\nField <code>jtag</code> writer -\nField <code>pads_bank0</code> reader -\nField <code>pads_bank0</code> writer -\nField <code>pads_qspi</code> reader -\nField <code>pads_qspi</code> writer -\nField <code>pio0</code> reader -\nField <code>pio0</code> writer -\nField <code>pio1</code> reader -\nField <code>pio1</code> writer -\nField <code>pll_sys</code> reader -\nField <code>pll_sys</code> writer -\nField <code>pll_usb</code> reader -\nField <code>pll_usb</code> writer -\nField <code>pwm</code> reader -\nField <code>pwm</code> writer -\nRegister <code>RESET</code> reader\nReset control. If a bit is set it means the peripheral is …\nField <code>rtc</code> reader -\nField <code>rtc</code> writer -\nField <code>spi0</code> reader -\nField <code>spi0</code> writer -\nField <code>spi1</code> reader -\nField <code>spi1</code> writer -\nField <code>syscfg</code> reader -\nField <code>syscfg</code> writer -\nField <code>sysinfo</code> reader -\nField <code>sysinfo</code> writer -\nField <code>tbman</code> reader -\nField <code>tbman</code> writer -\nField <code>timer</code> reader -\nField <code>timer</code> writer -\nField <code>uart0</code> reader -\nField <code>uart0</code> writer -\nField <code>uart1</code> reader -\nField <code>uart1</code> writer -\nField <code>usbctrl</code> reader -\nField <code>usbctrl</code> writer -\nRegister <code>RESET</code> writer\nBit 0\nBit 0\nWrites raw bits to the register.\nBit 1\nBit 1\nBit 2\nBit 2\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 4\nBit 4\nCalls <code>U::from(self)</code>.\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 12\nBit 12\nBit 13\nBit 13\nBit 14\nBit 14\nBit 15\nBit 15\nBit 16\nBit 16\nBit 17\nBit 17\nBit 18\nBit 18\nBit 19\nBit 19\nBit 20\nBit 20\nBit 21\nBit 21\nBit 22\nBit 22\nBit 23\nBit 23\nBit 24\nBit 24\nField <code>adc</code> reader -\nField <code>busctrl</code> reader -\nField <code>dma</code> reader -\nField <code>i2c0</code> reader -\nField <code>i2c1</code> reader -\nField <code>io_bank0</code> reader -\nField <code>io_qspi</code> reader -\nField <code>jtag</code> reader -\nField <code>pads_bank0</code> reader -\nField <code>pads_qspi</code> reader -\nField <code>pio0</code> reader -\nField <code>pio1</code> reader -\nField <code>pll_sys</code> reader -\nField <code>pll_usb</code> reader -\nField <code>pwm</code> reader -\nRegister <code>RESET_DONE</code> reader\nReset done. If a bit is set then a reset done signal has …\nField <code>rtc</code> reader -\nField <code>spi0</code> reader -\nField <code>spi1</code> reader -\nField <code>syscfg</code> reader -\nField <code>sysinfo</code> reader -\nField <code>tbman</code> reader -\nField <code>timer</code> reader -\nField <code>uart0</code> reader -\nField <code>uart1</code> reader -\nField <code>usbctrl</code> reader -\nBit 0\nBit 1\nBit 2\nReturns the argument unchanged.\nBit 3\nBit 4\nCalls <code>U::from(self)</code>.\nBit 5\nBit 6\nBit 7\nBit 8\nBit 9\nBit 10\nBit 11\nBit 12\nBit 13\nBit 14\nBit 15\nBit 16\nBit 17\nBit 18\nBit 19\nBit 20\nBit 21\nBit 22\nBit 23\nBit 24\nField <code>adc</code> reader -\nField <code>adc</code> writer -\nField <code>busctrl</code> reader -\nField <code>busctrl</code> writer -\nField <code>dma</code> reader -\nField <code>dma</code> writer -\nField <code>i2c0</code> reader -\nField <code>i2c0</code> writer -\nField <code>i2c1</code> reader -\nField <code>i2c1</code> writer -\nField <code>io_bank0</code> reader -\nField <code>io_bank0</code> writer -\nField <code>io_qspi</code> reader -\nField <code>io_qspi</code> writer -\nField <code>jtag</code> reader -\nField <code>jtag</code> writer -\nField <code>pads_bank0</code> reader -\nField <code>pads_bank0</code> writer -\nField <code>pads_qspi</code> reader -\nField <code>pads_qspi</code> writer -\nField <code>pio0</code> reader -\nField <code>pio0</code> writer -\nField <code>pio1</code> reader -\nField <code>pio1</code> writer -\nField <code>pll_sys</code> reader -\nField <code>pll_sys</code> writer -\nField <code>pll_usb</code> reader -\nField <code>pll_usb</code> writer -\nField <code>pwm</code> reader -\nField <code>pwm</code> writer -\nRegister <code>WDSEL</code> reader\nField <code>rtc</code> reader -\nField <code>rtc</code> writer -\nField <code>spi0</code> reader -\nField <code>spi0</code> writer -\nField <code>spi1</code> reader -\nField <code>spi1</code> writer -\nField <code>syscfg</code> reader -\nField <code>syscfg</code> writer -\nField <code>sysinfo</code> reader -\nField <code>sysinfo</code> writer -\nField <code>tbman</code> reader -\nField <code>tbman</code> writer -\nField <code>timer</code> reader -\nField <code>timer</code> writer -\nField <code>uart0</code> reader -\nField <code>uart0</code> writer -\nField <code>uart1</code> reader -\nField <code>uart1</code> writer -\nField <code>usbctrl</code> reader -\nField <code>usbctrl</code> writer -\nRegister <code>WDSEL</code> writer\nWatchdog select. If a bit is set then the watchdog will …\nBit 0\nBit 0\nWrites raw bits to the register.\nBit 1\nBit 1\nBit 2\nBit 2\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 4\nBit 4\nCalls <code>U::from(self)</code>.\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 12\nBit 12\nBit 13\nBit 13\nBit 14\nBit 14\nBit 15\nBit 15\nBit 16\nBit 16\nBit 17\nBit 17\nBit 18\nBit 18\nBit 19\nBit 19\nBit 20\nBit 20\nBit 21\nBit 21\nBit 22\nBit 22\nBit 23\nBit 23\nBit 24\nBit 24\nCTRL (rw) register accessor: Ring Oscillator control\nDIV (rw) register accessor: Controls the output divider\nDORMANT (rw) register accessor: Ring Oscillator pause …\nFREQA (rw) register accessor: The FREQA &amp; FREQB registers …\nFREQB (rw) register accessor: For a detailed description …\nPHASE (rw) register accessor: Controls the phase shifted …\nRANDOMBIT (r) register accessor: This just reads the state …\nRegister block\nSTATUS (r) register accessor: Ring Oscillator Status\nRing Oscillator control\n0x00 - Ring Oscillator control\nControls the output divider\n0x10 - Controls the output divider\nRing Oscillator pause control This is used to save power …\n0x0c - Ring Oscillator pause control This is used to save …\nThe FREQA &amp; FREQB registers control the frequency by …\n0x04 - The FREQA &amp; FREQB registers control the frequency …")
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