rtic/2/api/search.desc/imxrt_ral/imxrt_ral-desc-3-.js

searchState.loadedDescShard("imxrt_ral", 3, "PMIC On Request Enable The value written to PK_EN will be …\nPMIC On Request Override The value written to PK_OVERRIDE …\nPower Glitch Enable By default the detection of a power …\nSecure Real Time Counter Enabled and Valid When set, the …\nIf this bit is 1, in the case of a security violation the …\nTurn off System Power Asserting this bit causes a signal …\nSmart PMIC enabled.\nDumb PMIC enabled.\nSRTC Time calibration is disabled.\nSRTC Time calibration is enabled.\n+0 counts per each 32768 ticks of the counter clock\n+1 counts per each 32768 ticks of the counter clock\n+15 counts per each 32768 ticks of the counter clock\n-16 counts per each 32768 ticks of the counter clock\n-15 counts per each 32768 ticks of the counter clock\n+2 counts per each 32768 ticks of the counter clock\n-2 counts per each 32768 ticks of the counter clock\n-1 counts per each 32768 ticks of the counter clock\nLP time alarm interrupt is disabled.\nLP time alarm interrupt is enabled.\nMC is disabled or invalid.\nMC is enabled and valid.\nSRTC is disabled or invalid.\nSRTC is enabled and valid.\nSRTC stays valid in the case of security violation.\nSRTC is invalidated in the case of security violation.\nLeave system power on.\nTurn off system power.\nGeneral Purpose Register When GPR_SL or GPR_HL bit is set, …\nGeneral Purpose Register When GPR_SL or GPR_HL bit is set, …\nGeneral Purpose Register When GPR_SL or GPR_HL bit is set, …\nGeneral Purpose Register Hard Lock When set, prevents any …\nLP Calibration Hard Lock When set, prevents any writes to …\nLP Security Violation Control Register Hard Lock When set, …\nLP Tamper Detectors Configuration Register Hard Lock When …\nMonotonic Counter Hard Lock When set, prevents any writes …\nMaster Key Select Hard Lock When set, prevents any writes …\nSecure Real Time Counter Hard Lock When set, prevents any …\nZeroizable Master Key Read Hard Lock When set, prevents …\nZeroizable Master Key Write Hard Lock When set, prevents …\nWrite access is allowed.\nWrite access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nWrite access (increment) is allowed.\nWrite access (increment) is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nRead access is allowed (only in software programming mode).\nRead access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nMaster Key Select These bits select the SNVS Master Key …\nZeroizable Master Key Error Correcting Code Check Enable …\nZeroizable Master Key Error Correcting Code Value This …\nZeroizable Master Key hardware Programming mode When set, …\nZeroizable Master Key Valid When set, the ZMK value can be …\nSelect one time programmable master key.\nSelect zeroizable master key when MKS_EN bit is set .\nSelect combined master key when MKS_EN bit is set .\nZMK ECC check is disabled.\nZMK ECC check is enabled.\nZMK is in the software programming mode.\nZMK is in the hardware programming mode.\nZMK is not valid.\nZMK is valid.\nPower Glitch Detector Value\nMonotonic Counter bits The MC is incremented by one when: …\nMonotonic Counter Era Bits These bits are inputs to the …\nMonotonic Counter most-significant 16 Bits The MC is …\nEmergency Off This bit is set when a power off is …\nExternal Security Violation Detected Indicates that a …\nExternal Tampering 1 Detected\nLP Section is Non-Secured Indicates that LP section was …\nLP Section is Secured Indicates that the LP section is …\nLP Time Alarm\nMonotonic Counter Rollover\nPower Supply Glitch Detected 0 No power supply glitch. 1 …\nScan Exit Detected\nSet Power Off The SPO bit is set when the power button is …\nSecure Real Time Counter Rollover\nEmergency off was not detected.\nEmergency off was detected.\nNo external security violation.\nExternal security violation is detected.\nExternal tampering 1 not detected.\nExternal tampering 1 detected.\nLP section was not programmed in the non-secure state.\nLP section was programmed in the non-secure state.\nLP section was not programmed in secure or trusted state.\nLP section was programmed in secure or trusted state.\nNo time alarm interrupt occurred.\nA time alarm interrupt occurred.\nMC has not reached its maximum value.\nMC has reached its maximum value.\nScan exit was not detected.\nScan exit was detected.\nSet Power Off was not detected.\nSet Power Off was detected.\nSRTC has not reached its maximum value.\nSRTC has reached its maximum value.\nLP Secure Real Time Counter least-significant 32 bits This …\nLP Secure Real Time Counter The most-significant 15 bits …\nSecurity Violation 0 Enable This bit enables Security …\nSecurity Violation 1 Enable This bit enables Security …\nSecurity Violation 2 Enable This bit enables Security …\nSecurity Violation 3 Enable This bit enables Security …\nSecurity Violation 4 Enable This bit enables Security …\nSecurity Violation 5 Enable This bit enables Security …\nSecurity Violation 0 is disabled in the LP domain.\nSecurity Violation 0 is enabled in the LP domain.\nSecurity Violation 1 is disabled in the LP domain.\nSecurity Violation 1 is enabled in the LP domain.\nSecurity Violation 2 is disabled in the LP domain.\nSecurity Violation 2 is enabled in the LP domain.\nSecurity Violation 3 is disabled in the LP domain.\nSecurity Violation 3 is enabled in the LP domain.\nSecurity Violation 4 is disabled in the LP domain.\nSecurity Violation 4 is enabled in the LP domain.\nSecurity Violation 5 is disabled in the LP domain.\nSecurity Violation 5 is enabled in the LP domain.\nLP Time Alarm This register can be programmed only when …\nExternal Tampering 1 Polarity This bit is used to …\nExternal Tampering 1 Enable When set, external tampering 1 …\nMC Rollover Enable When set, an MC Rollover event …\nOscillator Bypass When OSCB=1 the osc_bypass signal is …\nSystem Power Fail Detector (PFD) Observability Flop The …\nPower On Reset (POR) Observability Flop The asynchronous …\nSRTC Rollover Enable When set, an SRTC rollover event …\nExternal tamper 1 is active low.\nExternal tamper 1 is active high.\nExternal tamper 1 is disabled.\nExternal tamper 1 is enabled.\nMC rollover is disabled.\nMC rollover is enabled.\nNormal SRTC clock oscillator not bypassed.\nNormal SRTC clock oscillator bypassed. Alternate clock can …\nSRTC rollover is disabled.\nSRTC rollover is enabled.\nZeroizable Master Key Each of these registers contains 32 …\nSPDIF\nSPDIF Configuration Register\nSPDIF Configuration Register\nInterruptClear Register\nInterruptClear Register\nInterruptEn Register\nInterruptEn Register\nSPDIF\nCDText Control Register\nCDText Control Register\nSPDIFRxCChannel_h Register\nSPDIFRxCChannel_h Register\nSPDIFRxCChannel_l Register\nSPDIFRxCChannel_l Register\nFreqMeas Register\nFreqMeas Register\nSPDIFRxLeft Register\nSPDIFRxLeft Register\nPhaseConfig Register\nPhaseConfig Register\nQchannelRx Register\nQchannelRx Register\nSPDIFRxRight Register\nSPDIFRxRight Register\nUchannelRx Register\nUchannelRx Register\nSPDIFTxClk Register\nSPDIFTxClk Register\nSPDIFTxCChannelCons_h Register\nSPDIFTxCChannelCons_h Register\nSPDIFTxCChannelCons_l Register\nSPDIFTxCChannelCons_l Register\nSPDIFTxLeft Register\nSPDIFTxLeft Register\nSPDIFTxRight Register\nSPDIFTxRight Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDMA Receive Request Enable (RX FIFO full)\nDMA Transmit Request Enable (Tx FIFO empty)\nWhen write 1 to this bit, it will cause SPDIF enter …\nno description available\nno description available\nno description available\nno description available\nno description available\nWhen write 1 to this bit, it will cause SPDIF software …\nno description available\nno description available\nno description available\nno description available\nno description available\nno description available\nRx FIFO auto sync off\nRxFIFO auto sync on\nFull interrupt if at least 1 sample in Rx left and right …\nFull interrupt if at least 4 sample in Rx left and right …\nFull interrupt if at least 8 sample in Rx left and right …\nFull interrupt if at least 16 sample in Rx left and right …\nNormal operation\nAlways read zero from Rx data register\nSPDIF Rx FIFO is on\nSPDIF Rx FIFO is off. Does not accept data from interface\nNormal operation\nReset register to 1 sample remaining\nTx FIFO auto sync off\nTx FIFO auto sync on\nEmpty interrupt if 0 sample in Tx left and right FIFOs\nEmpty interrupt if at most 4 sample in Tx left and right …\nEmpty interrupt if at most 8 sample in Tx left and right …\nEmpty interrupt if at most 12 sample in Tx left and right …\nSend out digital zero on SPDIF Tx\nTx Normal operation\nReset to 1 sample remaining\nOff and output 0\nFeed-through SPDIFIN\nTx Normal operation\nNo embedded U channel\nU channel from SPDIF receive block (CD mode)\nU channel from on chip transmitter\nOutgoing Validity always set\nOutgoing Validity always clear\nSPDIF receiver found parity bit error\nSPDIF receive change in value of control channel\nSPDIF receiver’s DPLL is locked\nSPDIF receiver loss of lock\nQ Channel receive register overrun\nRx FIFO resync\nRx FIFO underrun/overrun\nSPDIF receiver found illegal symbol\nSPDIF Tx FIFO resync\nSPDIF Tx FIFO under/overrun\nU/Q Channel framing error\nU/Q Channel sync found\nU Channel receive register overrun\nSPDIF validity flag no good\nSPDIF receiver found parity bit error\nSPDIF receive change in value of control channel\nSPDIF receiver’s DPLL is locked\nSPDIF receiver loss of lock\nQ Channel receive register full, can’t be cleared with …\nQ Channel receive register overrun\nSPDIF Rx FIFO full, can’t be cleared with reg. IntClear. …\nRx FIFO resync\nRx FIFO underrun/overrun\nSPDIF receiver found illegal symbol\nSPDIF Tx FIFO empty, can’t be cleared with reg. …\nSPDIF Tx FIFO resync\nSPDIF Tx FIFO under/overrun\nU/Q Channel framing error\nU/Q Channel sync found\nU Channel receive register full, can’t be cleared with …\nU Channel receive register overrun\nSPDIF validity flag no good\nno description available\nNon-CD data\nCD user channel subcode\nSPDIF receive C channel register, contains first 24 bits …\nSPDIF receive C channel register, contains next 24 bits of …\nFrequency measurement data\nProcessor receive SPDIF data left\nClock source selection, all other settings not shown are …\nGain selection:\nLOCK bit to show that the internal DPLL is locked, read …\nif (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)\nif (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)\nif (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK\nREF_CLK_32K (XTALOSC)\ntx_clk (SPDIF0_CLK_ROOT)\nSPDIF_EXT_CLK\n24*(2**10)\n16*(2**10)\n12*(2**10)\n8*(2**10)\n6*(2**10)\n4*(2**10)\n3*(2**10)\nSPDIF receive Q channel register, contains next 3 Q …\nProcessor receive SPDIF data right\nSPDIF receive U channel register, contains next 3 U …\nsystem clock divider factor, 2~512.\nDivider factor (1-128)\nno description available\nSpdif transfer clock enable. When data is going to be …\nno clock signal\ndivider factor is 2\ndivider factor is 512\ndivider factor is 1\ndivider factor is 2\ndivider factor is 128\nXTALOSC input (XTALOSC clock)\ntx_clk input (from SPDIF0_CLK_ROOT. See CCM.)\ntx_clk1 (from SAI1)\ntx_clk2 SPDIF_EXT_CLK, from pads\ntx_clk3 (from SAI2)\nipg_clk input (frequency divided)\ntx_clk4 (from SAI3)\ndisable transfer clock.\nenable transfer clock.\nSPDIF transmit Cons\nSPDIF transmit Cons\nSPDIF transmit left channel data. It is write-only, and …\nSPDIF transmit right channel data. It is write-only, and …\nSRC General Purpose Register 1\nSRC General Purpose Register 1\nSRC General Purpose Register 10\nSRC General Purpose Register 10\nSRC General Purpose Register 2\nSRC General Purpose Register 2\nSRC General Purpose Register 3\nSRC General Purpose Register 4\nSRC General Purpose Register 5\nSRC General Purpose Register 6\nSRC General Purpose Register 7\nSRC General Purpose Register 8\nSRC General Purpose Register 9\nSRC\nSRC Boot Mode Register 1\nSRC Boot Mode Register 1\nSRC Boot Mode Register 2\nSRC Boot Mode Register 2\nSRC Control Register\nSRC Control Register\nSRC\nSRC Reset Status Register\nSRC Reset Status Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nHolds entry function for core0 for waking-up from low …\nThis field identifies which image must be used - 0/1/2/3\nThis bit identifies which image must be used - primary and …\nHolds argument of entry function for core0 for waking-up …\nRefer to fusemap.\nRefer to fusemap.\nRefer to fusemap.\nRefer to fusemap.\nBMOD[1:0] shows the latched state of the BOOT_MODE1 and …\nBT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the …\nDIR_BT_DIS shows the state of the DIR_BT_DIS fuse\nSECONFIG[1] shows the state of the SECONFIG[1] fuse\nSoftware reset for core0 debug only\nSoftware reset for core0 only\nDo not assert debug resets after power gating event of core\nlockup reset enable bit\nMask wdog3_rst_b source\nMask wdog_rst_b source\ndo not assert core0 debug reset\nassert core0 debug reset\ndo not assert core0 reset\nassert core0 reset\ndo not mask core debug resets (debug resets will be …\nmask core debug resets (debug resets won’t be asserted …\ndisabled\nenabled\nwdog3_rst_b is not masked\nwdog3_rst_b is masked\nwdog_rst_b is not masked (default)\nwdog_rst_b is masked\nIndicates whether the reset was the result of the …\nIndicates whether reset was the result of ipp_reset_b pin …\nIndicates whether the reset was the result of the …\nHIGH - Z JTAG reset. Indicates whether the reset was the …\nJTAG software reset\nIndicates a reset has been caused by CPU lockup.\nIndicates a reset has been caused by CPU lockup.\nTemper Sensor software reset\nIC Watchdog3 Time-out reset\nIC Watchdog Time-out reset\nReset is not a result of the csu_reset_b event.\nReset is a result of the csu_reset_b event.\nReset is not a result of ipp_reset_b pin.\nReset is a result of ipp_reset_b pin.\nReset is not a result of the ipp_user_reset_b qualified as …\nReset is a result of the ipp_user_reset_b qualified as …\nReset is not a result of HIGH-Z reset from JTAG.\nReset is a result of HIGH-Z reset from JTAG.\nReset is not a result of the mentioned case.\nReset is not a result of the mentioned case.\nReset is not a result of the mentioned case.\nReset is a result of the mentioned case.\nReset is not a result of the mentioned case.\nReset is a result of the mentioned case.\nReset is not a result of software reset from Temperature …\nReset is a result of software reset from Temperature …\nReset is not a result of the watchdog3 time-out event.\nReset is a result of the watchdog3 time-out event.\nReset is not a result of the watchdog time-out event.\nReset is a result of the watchdog time-out event.\nTemperature Monitor\nTemperature Monitor\nTempsensor Control Register 0\nTempsensor Control Register 0\nTempsensor Control Register 0\nTempsensor Control Register 0\nTempsensor Control Register 0\nTempsensor Control Register 0\nTempsensor Control Register 0\nTempsensor Control Register 0\nTempsensor Control Register 1\nTempsensor Control Register 1\nTempsensor Control Register 1\nTempsensor Control Register 1\nTempsensor Control Register 1\nTempsensor Control Register 1\nTempsensor Control Register 1\nTempsensor Control Register 1\nTempsensor Control Register 2\nTempsensor Control Register 2\nTempsensor Control Register 2\nTempsensor Control Register 2\nTempsensor Control Register 2\nTempsensor Control Register 2\nTempsensor Control Register 2\nTempsensor Control Register 2\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nThis bit field contains the temperature count (raw sensor …\nIndicates that the latest temp is valid\nStarts the measurement process\nThis bit powers down the temperature sensor.\nThis bit field contains the last measured temperature …\nLast measurement is not ready yet.\nLast measurement is valid.\nStart the measurement process.\nDo not start the measurement process.\nPower down the temperature sensor.\nEnable power to the temperature sensor.\nThis bit field contains the temperature count (raw sensor …\nIndicates that the latest temp is valid\nStarts the measurement process\nThis bit powers down the temperature sensor.\nThis bit field contains the last measured temperature …\nLast measurement is not ready yet.\nLast measurement is valid.\nStart the measurement process.\nDo not start the measurement process.\nPower down the temperature sensor.\nEnable power to the temperature sensor.\nThis bit field contains the temperature count (raw sensor …\nIndicates that the latest temp is valid\nStarts the measurement process\nThis bit powers down the temperature sensor.\nThis bit field contains the last measured temperature …\nLast measurement is not ready yet.\nLast measurement is valid.\nStart the measurement process.\nDo not start the measurement process.\nPower down the temperature sensor.\nEnable power to the temperature sensor.\nThis bit field contains the temperature count (raw sensor …\nIndicates that the latest temp is valid\nStarts the measurement process\nThis bit powers down the temperature sensor.\nThis bit field contains the last measured temperature …\nLast measurement is not ready yet.\nLast measurement is valid.\nStart the measurement process.\nDo not start the measurement process.\nPower down the temperature sensor.\nEnable power to the temperature sensor.\nThis bits determines how many RTC clocks to wait before …\nThis bits determines how many RTC clocks to wait before …\nThis bits determines how many RTC clocks to wait before …\nThis bits determines how many RTC clocks to wait before …\nThis bit field contains the temperature count that will …\nThis bit field contains the temperature count that will …\nThis bit field contains the temperature count that will …\nThis bit field contains the temperature count that will …\nThis bit field contains the temperature count that will …\nThis bit field contains the temperature count that will …\nThis bit field contains the temperature count that will …\nThis bit field contains the temperature count that will …\nEntropy Read Register\nEntropy Read Register\nFrequency Count Maximum Limit Register\nFrequency Count Maximum Limit Register\nFrequency Count Minimum Limit Register\nFrequency Count Minimum Limit Register\nInterrupt Control Register\nInterrupt Control Register\nMask Register\nMask Register\nInterrupt Status Register\nInterrupt Status Register\nMiscellaneous Control Register\nMiscellaneous Control Register\nStatistical Check Poker Count 1 and 0 Register\nStatistical Check Poker Count 1 and 0 Register\nStatistical Check Poker Count 3 and 2 Register\nStatistical Check Poker Count 3 and 2 Register\nStatistical Check Poker Count 5 and 4 Register\nStatistical Check Poker Count 5 and 4 Register\nStatistical Check Poker Count 7 and 6 Register\nStatistical Check Poker Count 7 and 6 Register\nStatistical Check Poker Count 9 and 8 Register\nStatistical Check Poker Count 9 and 8 Register\nStatistical Check Poker Count B and A Register\nStatistical Check Poker Count B and A Register\nStatistical Check Poker Count D and C Register\nStatistical Check Poker Count D and C Register\nStatistical Check Poker Count F and E Register\nStatistical Check Poker Count F and E Register\nPoker Maximum Limit Register\nPoker Maximum Limit Register\nPoker Range Register\nPoker Range Register\nTRNG\nSparse Bit Limit Register\nSparse Bit Limit Register\nStatistical Check Miscellaneous Register\nStatistical Check Miscellaneous Register\nStatistical Check Monobit Limit Register\nStatistical Check Monobit Limit Register\nStatistical Check Run Length 1 Limit Register\nStatistical Check Run Length 1 Limit Register\nStatistical Check Run Length 2 Limit Register\nStatistical Check Run Length 2 Limit Register\nStatistical Check Run Length 3 Limit Register\nStatistical Check Run Length 3 Limit Register\nStatistical Check Run Length 4 Limit Register\nStatistical Check Run Length 4 Limit Register\nStatistical Check Run Length 5 Limit Register\nStatistical Check Run Length 5 Limit Register\nStatistical Check Run Length 6+ Limit Register\nStatistical Check Run Length 6+ Limit Register\nSeed Control Register\nSeed Control Register\nSecurity Configuration Register\nSecurity Configuration Register\nStatus Register\nStatus Register\nTRNG\nVersion ID Register (MS)\nVersion ID Register (MS)\nVersion ID Register (LS)\nVersion ID Register (LS)\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nEntropy Value\nFrequency Counter Maximum Limit\nFrequency Count Minimum Limit\nSame behavior as bit 0 of this register.\nSame behavior as bit 0 of this register.\nBit position that can be cleared if corresponding bit of …\nSame behavior as bit 0 of this register.\nSame behavior as bit 0 of this register.\nSame behavior as bit 0 of this register.\nSame behavior as bit 0 of this register.\nCorresponding bit of INT_STATUS register cleared.\nCorresponding bit of INT_STATUS register active.\nSame behavior as bit 0 of this register.\nSame behavior as bit 0 of this register.\nBit position that can be cleared if corresponding bit of …\nSame behavior as bit 0 of this register.\nSame behavior as bit 0 of this register.\nSame behavior as bit 0 of this register.\nSame behavior as bit 0 of this register.\nCorresponding interrupt of INT_STATUS is masked.\nCorresponding bit of INT_STATUS is active.\nRead only: Entropy Valid\nRead only: Frequency Count Fail\nRead: Error status\nBusy generation entropy. Any value read is invalid.\nTRNG can be stopped and entropy is valid if read.\nNo hardware nor self test frequency errors.\nThe frequency counter has detected a failure.\nno error\nerror detected.\nRead only: Entropy Valid\nRead: Error status\nRead only: Frequency Count Fail\nRead only: Frequency Count Valid. Indicates that a valid …\nForce System Clock\nLong run count continues between entropy generations\nOscillator Divide\nProgramming Mode Select\nReset Defaults\nSample Mode\nTRNG_OK_TO_STOP\nRead only: Test point inside ring oscillator.\nThis bit is unused. Always reads zero.\nThis bit is unused. Always reads zero.\nuse ring oscillator with no divide\nuse ring oscillator divided-by-2\nuse ring oscillator divided-by-4\nuse ring oscillator divided-by-8\nuse Von Neumann data into both Entropy shifter and …\nuse raw data into both Entropy shifter and Statistical …\nuse Von Neumann data into Entropy shifter. Use raw data …\nundefined/reserved.\nPoker 0h Count\nPoker 1h Count\nPoker 2h Count\nPoker 3h Count\nPoker 4h Count\nPoker 5h Count\nPoker 6h Count\nPoker 7h Count\nPoker 8h Count\nPoker 9h Count\nPoker Ah Count\nPoker Bh Count\nPoker Ch Count\nPoker Dh Count\nPoker Eh Count\nPoker Fh Count\nPoker Maximum Limit.\nPoker Range\nSparse Bit Limit\nLONG RUN MAX LIMIT\nRETRY COUNT\nMonobit Maximum Limit\nMonobit Range\nRun Length 1 Maximum Limit\nRun Length 1 Range\nRun Length 2 Maximum Limit\nRun Length 2 Range\nRun Length 3 Maximum Limit\nRun Length 3 Range\nRun Length 4 Maximum Limit\nRun Length 4 Range\nRun Length 5 Maximum Limit\nRun Length 5 Range\nRun Length 6+ Maximum Limit\nRun Length 6+ Range\nEntropy Delay\nSample Size\nIf set, the TRNG registers cannot be programmed\nThis bit is unused. Ignore.\nThis bit is unused. Ignore.\nProgramability of registers controlled only by the …\nOverides Miscellaneous Control Register access mode and …\nRETRY COUNT\nTest Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit …\nTest Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit …\nTest Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit …\nTest Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit …\nTest Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit …\nTest Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit …\nTest Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit …\nTest Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit …\nTest Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit …\nTest Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit …\nTest Fail, 6 Plus Bit Run, Sampling 0s\nTest Fail, 6 Plus Bit Run, Sampling 1s\nTest Fail, Long Run. If TFLR=1, the Long Run Test has …\nTest Fail, Mono Bit. If TFMB=1, the Mono Bit Test has …\nTest Fail, Poker. If TFP=1, the Poker Test has failed.\nTest Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has …\nShows the IP ID.\nShows the IP’s Major revision of the TRNG.\nShows the IP’s Minor revision of the TRNG.\nID for TRNG.\nMajor revision number for TRNG.\nMinor revision number for TRNG.\nShows the IP’s Configuaration options for the TRNG.\nShows the IP’s ECO revision of the TRNG.\nShows the compile options for the TRNG.\nShows the integration options for the TRNG.\nTRNG_CONFIG_OPT for TRNG.\nTRNG_ECO_REV for TRNG.\nCOMPILE_OPT for TRNG.\nINTG_OPT for TRNG.\nNext Asynch. Address\nNext Asynch. Address\nProgrammable Burst Size\nProgrammable Burst Size\nCapability Registers Length\nCapability Registers Length\nConfigure Flag Register\nConfigure Flag Register\nDevice Controller Capability Parameters\nDevice Controller Capability Parameters\nDevice Controller Interface Version\nDevice Controller Interface Version\nDevice Address\nDevice Address\nEndpoint Complete\nEndpoint Complete\nEndpoint Control\nEndpoint Control\nEndpoint Control0\nEndpoint Control0\nEndpoint Flush\nEndpoint Flush\nEndpoint NAK\nEndpoint NAK\nEndpoint NAK Enable\nEndpoint NAK Enable\nEndpoint Prime\nEndpoint Prime\nEndpoint Setup Status\nEndpoint Setup Status\nEndpoint Status\nEndpoint Status\nUSB Frame Index\nUSB Frame Index\nGeneral Purpose Timer #0 Controller\nGeneral Purpose Timer #0 Controller\nGeneral Purpose Timer #0 Load\nGeneral Purpose Timer #0 Load\nGeneral Purpose Timer #1 Controller\nGeneral Purpose Timer #1 Controller\nGeneral Purpose Timer #1 Load\nGeneral Purpose Timer #1 Load\nHost Controller Capability Parameters\nHost Controller Capability Parameters\nHost Controller Interface Version\nHost Controller Interface Version\nHost Controller Structural Parameters\nHost Controller Structural Parameters\nDevice Hardware Parameters\nDevice Hardware Parameters\nHardware General\nHardware General\nHost Hardware Parameters\nHost Hardware Parameters\nRX Buffer Hardware Parameters\nRX Buffer Hardware Parameters\nTX Buffer Hardware Parameters\nTX Buffer Hardware Parameters\nIdentification register\nIdentification register\nOn-The-Go Status &amp; control\nOn-The-Go Status &amp; control\nPort Status &amp; Control\nPort Status &amp; Control\nUSB\nSystem Bus Config\nSystem Bus Config\nTX FIFO Fill Tuning\nTX FIFO Fill Tuning\nUSB\nUSB Command Register\nUSB Command Register\nInterrupt Enable Register\nInterrupt Enable Register\nUSB Device Mode\nUSB Device Mode\nUSB Status Register\nUSB Status Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nLink Pointer Low (LPL)\nProgrammable RX Burst Size\nProgrammable TX Burst Size\nThese bits are used as an offset to add to register base …\nConfigure Flag Host software sets this bit as the last …\nPort routing control logic default-routes each port to an …\nPort routing control logic default-routes all ports to …\nDevice Capable When this bit is 1, this controller is …\nDevice Endpoint Number This field indicates the number of …\nHost Capable When this bit is 1, this controller is …\nDevice Controller Interface Version Number Default value …\nDevice Address. These bits correspond to the USB device …\nDevice Address Advance\nEndpoint Receive Complete Event - RW/C\nEndpoint Transmit Complete Event - R/WC\nRX Endpoint Data Sink - Read/Write 0 Dual Port Memory …\nRX Endpoint Enable 0 Disabled [Default] 1 Enabled An …\nRX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This …\nRX Data Toggle Reset (WS) Write 1 - Reset PID Sequence …\nRX Endpoint Stall - Read/Write 0 End Point OK\nRX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 …\nTX Endpoint Data Source - Read/Write 0 Dual Port Memory …\nTX Endpoint Enable 0 Disabled [Default] 1 Enabled An …\nTX Data Toggle Inhibit 0 PID Sequencing Enabled\nTX Data Toggle Reset (WS) Write 1 - Reset PID Sequence …\nTX Endpoint Stall - Read/Write 0 End Point OK 1 End Point …\nTX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 …\nRX Endpoint Enable 1 Enabled Endpoint0 is always enabled.\nRX Endpoint Stall - Read/Write 0 End Point OK\nRX Endpoint Type - Read/Write 00 Control Endpoint0 is …\nTX Endpoint Enable 1 Enabled Endpoint0 is always enabled.\nTX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 …\nTX Endpoint Type - Read/Write 00 - Control Endpoint0 is …\nFlush Endpoint Receive Buffer - R/WS\nFlush Endpoint Transmit Buffer - R/WS\nRX Endpoint NAK - R/WC\nTX Endpoint NAK - R/WC\nRX Endpoint NAK Enable - R/W\nTX Endpoint NAK Enable - R/W\nPrime Endpoint Receive Buffer - R/WS\nPrime Endpoint Transmit Buffer - R/WS\nSetup Endpoint Status\nEndpoint Receive Buffer Ready – Read Only\nEndpoint Transmit Buffer Ready – Read Only\nFrame Index\n(1024) 12\n(512) 11\n(256) 10\n(128) 9\n(64) 8\n(32) 7\n(16) 6\n(8) 5\nGeneral Purpose Timer Counter. This field is the count …\nGeneral Purpose Timer Mode In one shot mode, the timer …\nGeneral Purpose Timer Reset\nGeneral Purpose Timer Run GPTCNT bits are not effected …\nOne Shot Mode\nRepeat Mode\nNo action\nLoad counter value from GPTLD bits in n_GPTIMER0LD\nStop counting\nRun\nGeneral Purpose Timer Load Value These bit fields are …\nGeneral Purpose Timer Counter. This field is the count …\nGeneral Purpose Timer Mode In one shot mode, the timer …\nGeneral Purpose Timer Reset\nGeneral Purpose Timer Run GPTCNT bits are not effected …\nOne Shot Mode\nRepeat Mode\nNo action\nLoad counter value from GPTLD bits in USB_n_GPTIMER0LD\nStop counting\nRun\nGeneral Purpose Timer Load Value These bit fields are …\n64-bit Addressing Capability This bit is set ‘0b’ in …\nAsynchronous Schedule Park Capability If this bit is set …\nEHCI Extended Capabilities Pointer\nIsochronous Scheduling Threshold\nProgrammable Frame List Flag If this bit is set to zero, …\nHost Controller Interface Version Number Default value is …\nNumber of Companion Controller (N_CC)\nNumber of Ports per Companion Controller This field …\nNumber of downstream ports\nNumber of Ports per Transaction Translator (N_PTT)\nNumber of Transaction Translators (N_TT)\nPort Indicators (P INDICATOR) This bit indicates whether …\nPort Power Control This field indicates whether the host …\nThere is no internal Companion Controller and …\nThere are internal companion controller(s) and …\nDevice Capable. Indicating whether device operation mode …\nDevice Endpoint Number\nNot supported\nSupported\nTransciever type\nData width of the transciever connected to the controller …\nSerial interface mode capability\nUTMI/UMTI+\nULPI DDR\nULPI\nSerial Only\nSoftware programmable - reset to UTMI/UTMI+\nSoftware programmable - reset to ULPI DDR\nSoftware programmable - reset to ULPI\nSoftware programmable - reset to Serial\n8 bit wide data bus Software non-programmable\n16 bit wide data bus Software non-programmable\nReset to 8 bit wide data bus Software programmable\nReset to 16 bit wide data bus Software programmable\nNo Serial Engine, always use parallel signalling.\nSerial Engine present, always use serial signalling for …\nSoftware programmable - Reset to use parallel signalling …\nSoftware programmable - Reset to use serial signalling for …\nHost Capable. Indicating whether host operation mode is …\nThe Nmber of downstream ports supported by the host …\nNot supported\nSupported\nBuffer total size for all receive endpoints is (2^RXADD)\nDefault burst size for memory to RX buffer transfer\nDefault burst size for memory to TX buffer transfer\nTX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes\nConfiguration number\nComplement version of ID\nRevision number of the controller core.\nA Session Valid - Read Only. Indicates VBus is above the A …\nA Session Valid Interrupt Enable - Read/Write\nA Session Valid Interrupt Status - Read/Write to Clear\nA VBus Valid - Read Only. Indicates VBus is above the A …\nA VBus Valid Interrupt Enable - Read/Write. Setting this …\nA VBus Valid Interrupt Status - Read/Write to Clear\nB Session End - Read Only. Indicates VBus is below the B …\nB Session End Interrupt Enable - Read/Write. Setting this …\nB Session End Interrupt Status - Read/Write to Clear\nB Session Valid - Read Only. Indicates VBus is above the B …\nB Session Valid Interrupt Enable - Read/Write\nB Session Valid Interrupt Status - Read/Write to Clear\nData Pulsing - Read/Write\nData Pulse Interrupt Enable\nData Pulse Interrupt Status - Read/Write to Clear\nData Bus Pulsing Status - Read Only\n1 millisecond timer Interrupt Enable - Read/Write\nUSB ID - Read Only. 0 = A device, 1 = B device\nUSB ID Interrupt Enable - Read/Write. Setting this bit …\nUSB ID Interrupt Status - Read/Write\nID Pullup - Read/Write This bit provide control over the …\nOTG Termination - Read/Write\n1 millisecond timer Interrupt Status - Read/Write to Clear\n1 millisecond timer toggle - Read Only. This bit toggles …\nVBUS Charge - Read/Write\nVBUS_Discharge - Read/Write. Setting this bit causes VBus …\nCurrent Connect Status-Read Only\nConnect Status Change-R/WC\nForce Port Resume -Read/Write\nHigh-Speed Port - Read Only\nLine Status-Read Only\nOver-current Active-Read Only\nOver-current Change-R/WC\nPort Enabled/Disabled-Read/Write\nPort Enable/Disable Change-R/WC\nPort Force Full Speed Connect - Read/Write\nPHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write\nPort Indicator Control - Read/Write\nPort Owner-Read/Write\nPort Power (PP)-Read/Write or Read Only\nPort Reset - Read/Write or Read Only\nPort Speed - Read Only. This register field indicates the …\nPort Test Control - Read/Write\nAll USB port interface modes are listed in this field …\nSee description at bits 31-30\nParallel Transceiver Width This bit has no effect if …\nSerial Transceiver Select 1 Serial Interface Engine is …\nSuspend - Read/Write or Read Only\nWake on Connect Enable (WKCNNT_E) - Read/Write\nWake on Disconnect Enable (WKDSCNNT_E) - Read/Write\nWake on Over-current Enable (WKOC_E) - Read/Write\nSE0\nK-state\nJ-state\nUndefined\nThis port does not have an over-current condition.\nThis port currently has an over-current condition\nNormal operation\nForced to full speed\nEnable PHY clock\nDisable PHY clock\nPort indicators are off\nAmber\nGreen\nUndefined\nFull Speed\nLow Speed\nHigh Speed\nUndefined\nTEST_MODE_DISABLE\nJ_STATE\nK_STATE\nSE0 (host) / NAK (device)\nPacket\nFORCE_ENABLE_HS\nFORCE_ENABLE_FS\nFORCE_ENABLE_LS\nSelect the 8-bit UTMI interface [60MHz]\nSelect the 16-bit UTMI interface [30MHz]\nAHB master interface Burst configuration These bits …\nIncremental burst of unspecified length only\nINCR4 burst, then single transfer\nINCR8 burst, INCR4 burst, then single transfer\nINCR16 burst, INCR8 burst, INCR4 burst, then single …\nINCR4 burst, then incremental burst of unspecified length\nINCR8 burst, INCR4 burst, then incremental burst of …\nINCR16 burst, INCR8 burst, INCR4 burst, then incremental …\nFIFO Burst Threshold\nScheduler Health Counter\nScheduler Overhead\nAsynchronous Schedule Enable - Read/Write\nAsynchronous Schedule Park Mode Count - Read/Write\nAsynchronous Schedule Park Mode Enable - Read/Write\nAdd dTD TripWire - Read/Write\nSee description at bit 15\nFrame List Size - (Read/Write or Read Only)\nInterrupt on Async Advance Doorbell - Read/Write\nInterrupt Threshold Control -Read/Write\nPeriodic Schedule Enable- Read/Write\nRun/Stop (RS) - Read/Write\nController Reset (RESET) - Read/Write\nSetup TripWire - Read/Write\nDo not process the Asynchronous Schedule.\nUse the ASYNCLISTADDR register to access the Asynchronous …\nImmediate (no threshold)\n1 micro-frame\n16 micro-frames\n2 micro-frames\n32 micro-frames\n4 micro-frames\n64 micro-frames\n8 micro-frames\nDo not process the Periodic Schedule\nUse the PERIODICLISTBASE register to access the Periodic …\nAsync Advance Interrupt Enable When this bit is one and …\nFrame List Rollover Interrupt Enable When this bit is one …\nNAK Interrupt Enable When this bit is one and the NAKI bit …\nPort Change Detect Interrupt Enable When this bit is one …\nSystem Error Interrupt Enable When this bit is one and the …\nSleep Interrupt Enable When this bit is one and the SLI …\nSOF Received Interrupt Enable When this bit is one and the …\nGeneral Purpose Timer #0 Interrupt Enable When this bit is …\nGeneral Purpose Timer #1 Interrupt Enable When this bit is …\nUSB Host Asynchronous Interrupt Enable When this bit is …\nUSB Interrupt Enable When this bit is one and the UI bit …\nUSB Error Interrupt Enable When this bit is one and the …\nULPI Interrupt Enable When this bit is one and the UPLII …\nUSB Host Periodic Interrupt Enable When this bit is one, …\nUSB Reset Interrupt Enable When this bit is one and the …\nController Mode - R/WO\nEndian Select - Read/Write\nStream Disable Mode\nSetup Lockout Mode\nIdle [Default for combination host/device]\nDevice Controller [Default for device only controller]\nHost Controller [Default for host only controller]\nLittle Endian [Default]\nBig Endian\nSetup Lockouts On (default);\nSetup Lockouts Off (DCD requires use of Setup Data Buffer …\nInterrupt on Async Advance - R/WC\nAsynchronous Schedule Status - Read Only\nFrame List Rollover - R/WC\nHCHaIted - Read Only\nNAK Interrupt Bit–RO\nPort Change Detect - R/WC\nPeriodic Schedule Status - Read Only\nReclamation - Read Only\nSystem Error- R/WC\nDCSuspend - R/WC\nSOF Received - R/WC\nGeneral Purpose Timer Interrupt 0(GPTINT0)–R/WC\nGeneral Purpose Timer Interrupt 1(GPTINT1)–R/WC\nUSB Error Interrupt (USBERRINT) - R/WC\nUSB Interrupt (USBINT) - R/WC\nULPI Interrupt - R/WC\nUSB Reset Received - R/WC\nChip Silicon Version\nChip Silicon Version\nUSB Analog\nUSB Charger Detect Register\nUSB Charger Detect Register\nUSB Charger Detect Register\nUSB Charger Detect Register\nUSB Charger Detect Register\nUSB Charger Detect Register\nUSB Charger Detect Status Register\nUSB Charger Detect Status Register\nUSB Charger Detect Register\nUSB Charger Detect Register\nUSB Loopback Test Register\nUSB Loopback Test Register\nUSB Loopback Test Register\nUSB Loopback Test Register\nUSB Loopback Test Register\nUSB Loopback Test Register\nUSB Loopback Test Register\nUSB Loopback Test Register\nUSB Misc Register\nUSB Misc Register\nUSB Misc Register\nUSB Misc Register\nUSB Misc Register\nUSB Misc Register\nUSB Misc Register\nUSB Misc Register\nUSB VBUS Detect Register\nUSB VBUS Detect Register\nUSB VBUS Detect Register\nUSB VBUS Detect Register\nUSB VBUS Detect Register\nUSB VBUS Detect Register\nUSB VBUS Detect Status Register\nUSB VBUS Detect Status Register\nUSB VBUS Detect Register\nUSB VBUS Detect Register\nUSB Analog\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nChip silicon revision\nSilicon revision 1.0\nCheck the charger connection\nCheck the contact of USB plug\nControl the charger detector.\nCheck whether a charger (either a dedicated charger or a …\nDo not check whether a charger is connected to the USB …\nCheck whether the USB plug has been in contact with each …\nDo not check the contact of USB plug.\nDisable the charger detector.\nEnable the charger detector.\nCheck the charger connection\nCheck the contact of USB plug\nControl the charger detector.\nCheck whether a charger (either a dedicated charger or a …\nDo not check whether a charger is connected to the USB …\nCheck whether the USB plug has been in contact with each …\nDo not check the contact of USB plug.\nDisable the charger detector.\nEnable the charger detector.\nCheck the charger connection\nCheck the contact of USB plug\nControl the charger detector.\nCheck whether a charger (either a dedicated charger or a …\nDo not check whether a charger is connected to the USB …\nCheck whether the USB plug has been in contact with each …\nDo not check the contact of USB plug.\nDisable the charger detector.\nEnable the charger detector.\nState of charger detection. This bit is a read only …\nDM line state output of the charger detector.\nDP line state output of the charger detector.\nState of the USB plug contact detector.\nThe USB port is not connected to a charger.\nA charger (either a dedicated charger or a host charger) …\nThe USB plug has made good contact.\nThe USB plug has not made contact.\nCheck the charger connection\nCheck the contact of USB plug\nControl the charger detector.\nCheck whether a charger (either a dedicated charger or a …\nDo not check whether a charger is connected to the USB …\nCheck whether the USB plug has been in contact with each …\nDo not check the contact of USB plug.\nDisable the charger detector.\nEnable the charger detector.\nSetting this bit can enable 1\nSetting this bit can enable 1\nSetting this bit can enable 1\nSetting this bit can enable 1\nEnables the clk to the UTMI block.\nEnable the deglitching circuit of the USB PLL output.\nUse external resistor to generate the current bias for the …\nEnables the clk to the UTMI block.\nEnable the deglitching circuit of the USB PLL output.\nUse external resistor to generate the current bias for the …\nEnables the clk to the UTMI block.\nEnable the deglitching circuit of the USB PLL output.\nUse external resistor to generate the current bias for the …\nEnables the clk to the UTMI block.\nEnable the deglitching circuit of the USB PLL output.\nUse external resistor to generate the current bias for the …\nUSB OTG charge VBUS.\nUSB OTG discharge VBUS.\nPowers up comparators for vbus_valid detector.\nSet the threshold for the VBUSVALID comparator\n4.0V\n4.1V\n4.2V\n4.3V\n4.4V (default)\n4.5V\n4.6V\n4.7V\nUSB OTG charge VBUS.\nUSB OTG discharge VBUS.\nPowers up comparators for vbus_valid detector.\nSet the threshold for the VBUSVALID comparator\n4.0V\n4.1V\n4.2V\n4.3V\n4.4V (default)\n4.5V\n4.6V\n4.7V\nUSB OTG charge VBUS.\nUSB OTG discharge VBUS.\nPowers up comparators for vbus_valid detector.\nSet the threshold for the VBUSVALID comparator\n4.0V\n4.1V\n4.2V\n4.3V\n4.4V (default)\n4.5V\n4.6V\n4.7V\nIndicates VBus is valid for a A-peripheral\nIndicates VBus is valid for a B-peripheral\nSession End for USB OTG\nVBus valid for USB OTG\nUSB OTG charge VBUS.\nUSB OTG discharge VBUS.\nPowers up comparators for vbus_valid detector.\nSet the threshold for the VBUSVALID comparator\n4.0V\n4.1V\n4.2V\n4.3V\n4.4V (default)\n4.5V\n4.6V\n4.7V\nUSB\nUSB\nUSB OTG1 Control Register\nUSB OTG1 Control Register\nOTG1 UTMI PHY Control 0 Register\nOTG1 UTMI PHY Control 0 Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDisable OTG1 Overcurrent Detection\nOTG1 Polarity of Overcurrent The polarity of OTG1 port …\nOTG1 Power Polarity This bit should be set according to …\nOTG1 Wake-up Interrupt Enable This bit enables or disables …\nOTG1 Wake-up Interrupt Request This bit indicates that a …\nWake-up on DPDM change enable\nOTG1 Wake-up on ID change enable\nOTG1 Software Wake-up\nOTG1 Software Wake-up Enable\nOTG1 wake-up on VBUS change enable\nEnables overcurrent detection\nDisables overcurrent detection\nHigh active (high on this signal represents an overcurrent …\nLow active (low on this signal represents an overcurrent …\nPMIC Power Pin is Low active.\nPMIC Power Pin is High active.\nInterrupt Disabled\nInterrupt Enabled\nNo wake-up interrupt request received\nWake-up Interrupt Request received\nDPDM changes wake-up to be disabled only when VBUS is 0.\n(Default) DPDM changes wake-up to be enabled, it is for …\nDisable\nEnable\nInactive\nForce wake-up\nDisable\nEnable\nDisable\nEnable\nIndicating whether OTG1 UTMI PHY clock is valid\nInvalid\nValid\nUSB PHY General Control Register\nUSB PHY General Control Register\nUSB PHY General Control Register\nUSB PHY General Control Register\nUSB PHY General Control Register\nUSB PHY General Control Register\nUSB PHY General Control Register\nUSB PHY General Control Register\nUSB PHY Debug Register\nUSB PHY Debug Register\nUTMI Debug Status Register 0\nUTMI Debug Status Register 0\nUTMI Debug Status Register 1\nUTMI Debug Status Register 1\nUTMI Debug Status Register 1\nUTMI Debug Status Register 1\nUTMI Debug Status Register 1\nUTMI Debug Status Register 1\nUTMI Debug Status Register 1\nUTMI Debug Status Register 1\nUSB PHY Debug Register\nUSB PHY Debug Register\nUSB PHY Debug Register\nUSB PHY Debug Register\nUSB PHY Debug Register\nUSB PHY Debug Register\nUSB PHY Power-Down Register\nUSB PHY Power-Down Register\nUSB PHY Power-Down Register\nUSB PHY Power-Down Register\nUSB PHY Power-Down Register\nUSB PHY Power-Down Register\nUSB PHY Power-Down Register\nUSB PHY Power-Down Register\nUSB PHY Receiver Control Register\nUSB PHY Receiver Control Register\nUSB PHY Receiver Control Register\nUSB PHY Receiver Control Register\nUSB PHY Receiver Control Register\nUSB PHY Receiver Control Register\nUSB PHY Receiver Control Register\nUSB PHY Receiver Control Register\nUSBPHY Register Reference Index\nUSB PHY Status Register\nUSB PHY Status Register\nUSB PHY Transmitter Control Register\nUSB PHY Transmitter Control Register\nUSB PHY Transmitter Control Register\nUSB PHY Transmitter Control Register\nUSB PHY Transmitter Control Register\nUSB PHY Transmitter Control Register\nUSB PHY Transmitter Control Register\nUSB PHY Transmitter Control Register\nUSBPHY Register Reference Index\nUTMI RTL Version\nUTMI RTL Version\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nGate UTMI Clocks\nEnables the LRADC to monitor USB_DP and USB_DM. This is …\nIndicates that the device is connected\nFor device mode, if this bit is cleared to 0, then it …\nEnables the feature to auto-clear the CLKGATE bit if there …\nEnables the feature to auto-clear the PWD register bits in …\nEnables the feature to auto-enable the POWER bit of …\nFor device mode, enables 200-KOhm pullups for detecting …\nEnables the feature to wakeup USB if DP/DM is toggled when …\nFor host mode, enables high-speed disconnect detector\nEnables the feature to wakeup USB if ID is toggled when …\nEnables interrupt for the detection of connectivity to the …\nEnables interrupt for detection of disconnection to Device …\nEnables interrupt for detection of a non-J state on the …\nEnables interrupt for the wakeup events.\nEnables circuit to detect resistance of MiniAB ID pin.\nEnable OTG_ID_CHG_IRQ.\nEnables UTMI+ Level2. This should be enabled if needs to …\nEnables UTMI+ Level3\nEnables the feature to wakeup USB if VBUS is toggled when …\nEnables the feature to reset the FSDLL lock detection …\nIndicates that the device has disconnected in high-speed …\nForces the next FS packet that is transmitted to have a …\nOTG ID change interrupt. Indicates the value of ID pin …\nAlmost same as OTGID_STATUS in USBPHYx_STATUS Register\nSet to 1 will make RESUME_IRQ bit a sticky bit until …\nIndicates that the host is sending a wake-up after suspend\nReserved.\nWriting a 1 to this bit will soft-reset the USBPHYx_PWD, …\nUsed by the PHY to indicate a powered-down state\nIndicates that there is a wakeup event\nGate UTMI Clocks\nEnables the LRADC to monitor USB_DP and USB_DM. This is …\nIndicates that the device is connected\nFor device mode, if this bit is cleared to 0, then it …\nEnables the feature to auto-clear the CLKGATE bit if there …\nEnables the feature to auto-clear the PWD register bits in …\nEnables the feature to auto-enable the POWER bit of …\nFor device mode, enables 200-KOhm pullups for detecting …\nEnables the feature to wakeup USB if DP/DM is toggled when …\nFor host mode, enables high-speed disconnect detector\nEnables the feature to wakeup USB if ID is toggled when …\nEnables interrupt for the detection of connectivity to the …\nEnables interrupt for detection of disconnection to Device …\nEnables interrupt for detection of a non-J state on the …\nEnables interrupt for the wakeup events.\nEnables circuit to detect resistance of MiniAB ID pin.\nEnable OTG_ID_CHG_IRQ.\nEnables UTMI+ Level2. This should be enabled if needs to …\nEnables UTMI+ Level3\nEnables the feature to wakeup USB if VBUS is toggled when …\nEnables the feature to reset the FSDLL lock detection …\nIndicates that the device has disconnected in high-speed …\nForces the next FS packet that is transmitted to have a …\nOTG ID change interrupt. Indicates the value of ID pin …\nAlmost same as OTGID_STATUS in USBPHYx_STATUS Register\nSet to 1 will make RESUME_IRQ bit a sticky bit until …\nIndicates that the host is sending a wake-up after suspend\nReserved.\nWriting a 1 to this bit will soft-reset the USBPHYx_PWD, …\nUsed by the PHY to indicate a powered-down state\nIndicates that there is a wakeup event\nGate UTMI Clocks\nEnables the LRADC to monitor USB_DP and USB_DM. This is …\nIndicates that the device is connected\nFor device mode, if this bit is cleared to 0, then it …\nEnables the feature to auto-clear the CLKGATE bit if there …\nEnables the feature to auto-clear the PWD register bits in …\nEnables the feature to auto-enable the POWER bit of …\nFor device mode, enables 200-KOhm pullups for detecting …\nEnables the feature to wakeup USB if DP/DM is toggled when …\nFor host mode, enables high-speed disconnect detector\nEnables the feature to wakeup USB if ID is toggled when …\nEnables interrupt for the detection of connectivity to the …\nEnables interrupt for detection of disconnection to Device …\nEnables interrupt for detection of a non-J state on the …\nEnables interrupt for the wakeup events.\nEnables circuit to detect resistance of MiniAB ID pin.\nEnable OTG_ID_CHG_IRQ.\nEnables UTMI+ Level2. This should be enabled if needs to …\nEnables UTMI+ Level3\nEnables the feature to wakeup USB if VBUS is toggled when …\nEnables the feature to reset the FSDLL lock detection …\nIndicates that the device has disconnected in high-speed …\nForces the next FS packet that is transmitted to have a …\nOTG ID change interrupt. Indicates the value of ID pin …\nAlmost same as OTGID_STATUS in USBPHYx_STATUS Register\nSet to 1 will make RESUME_IRQ bit a sticky bit until …\nIndicates that the host is sending a wake-up after suspend\nReserved.\nWriting a 1 to this bit will soft-reset the USBPHYx_PWD, …\nUsed by the PHY to indicate a powered-down state\nIndicates that there is a wakeup event\nGate UTMI Clocks\nEnables the LRADC to monitor USB_DP and USB_DM. This is …\nIndicates that the device is connected\nFor device mode, if this bit is cleared to 0, then it …\nEnables the feature to auto-clear the CLKGATE bit if there …\nEnables the feature to auto-clear the PWD register bits in …\nEnables the feature to auto-enable the POWER bit of …\nFor device mode, enables 200-KOhm pullups for detecting …\nEnables the feature to wakeup USB if DP/DM is toggled when …\nFor host mode, enables high-speed disconnect detector\nEnables the feature to wakeup USB if ID is toggled when …\nEnables interrupt for the detection of connectivity to the …\nEnables interrupt for detection of disconnection to Device …\nEnables interrupt for detection of a non-J state on the …\nEnables interrupt for the wakeup events.\nEnables circuit to detect resistance of MiniAB ID pin.\nEnable OTG_ID_CHG_IRQ.\nEnables UTMI+ Level2. This should be enabled if needs to …\nEnables UTMI+ Level3\nEnables the feature to wakeup USB if VBUS is toggled when …\nEnables the feature to reset the FSDLL lock detection …\nIndicates that the device has disconnected in high-speed …\nForces the next FS packet that is transmitted to have a …\nOTG ID change interrupt. Indicates the value of ID pin …\nAlmost same as OTGID_STATUS in USBPHYx_STATUS Register\nSet to 1 will make RESUME_IRQ bit a sticky bit until …\nIndicates that the host is sending a wake-up after suspend\nReserved.\nWriting a 1 to this bit will soft-reset the USBPHYx_PWD, …\nUsed by the PHY to indicate a powered-down state\nIndicates that there is a wakeup event\nGate Test Clocks\nUse holding registers to assist in timing for external …\nSet bit 5 to 1 to override the control of the USB_DP …\nSet bit to allow squelch to reset high-speed receive.\nSet this bit to allow a countdown to transition in between …\nChoose to trigger the host resume SE0 with …\nSet bit 3 to 1 to pull down 15-KOhm on USB_DP line\nOnce OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to …\nReserved.\nReserved.\nReserved.\nReserved.\nDelay in between the detection of squelch to the reset of …\nDuration of RESET in terms of the number of 480-MHz cycles.\nDelay in between the end of transmit to the beginning of …\nRunning count of the failed pseudo-random generator …\nRunning count of the squelch reset instead of normal end …\nRunning count of the UTMI_RXERROR.\nDelay increment of the rise of squelch: 00 = Delay is …\nReserved. Note: This bit should remain clear.\nReserved.\nDelay increment of the rise of squelch: 00 = Delay is …\nReserved. Note: This bit should remain clear.\nReserved.\nDelay increment of the rise of squelch: 00 = Delay is …\nReserved. Note: This bit should remain clear.\nReserved.\nDelay increment of the rise of squelch: 00 = Delay is …\nReserved. Note: This bit should remain clear.\nReserved.\nGate Test Clocks\nUse holding registers to assist in timing for external …\nSet bit 5 to 1 to override the control of the USB_DP …\nSet bit to allow squelch to reset high-speed receive.\nSet this bit to allow a countdown to transition in between …\nChoose to trigger the host resume SE0 with …\nSet bit 3 to 1 to pull down 15-KOhm on USB_DP line\nOnce OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to …\nReserved.\nReserved.\nReserved.\nReserved.\nDelay in between the detection of squelch to the reset of …\nDuration of RESET in terms of the number of 480-MHz cycles.\nDelay in between the end of transmit to the beginning of …\nGate Test Clocks\nUse holding registers to assist in timing for external …\nSet bit 5 to 1 to override the control of the USB_DP …\nSet bit to allow squelch to reset high-speed receive.\nSet this bit to allow a countdown to transition in between …\nChoose to trigger the host resume SE0 with …\nSet bit 3 to 1 to pull down 15-KOhm on USB_DP line\nOnce OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to …\nReserved.\nReserved.\nReserved.\nReserved.\nDelay in between the detection of squelch to the reset of …\nDuration of RESET in terms of the number of 480-MHz cycles.\nDelay in between the end of transmit to the beginning of …\nGate Test Clocks\nUse holding registers to assist in timing for external …\nSet bit 5 to 1 to override the control of the USB_DP …\nSet bit to allow squelch to reset high-speed receive.\nSet this bit to allow a countdown to transition in between …\nChoose to trigger the host resume SE0 with …\nSet bit 3 to 1 to pull down 15-KOhm on USB_DP line\nOnce OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to …\nReserved.\nReserved.\nReserved.\nReserved.\nDelay in between the detection of squelch to the reset of …\nDuration of RESET in terms of the number of 480-MHz cycles.\nDelay in between the end of transmit to the beginning of …\nReserved.\nReserved.\nReserved.\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\nReserved.\nReserved.\nReserved.\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\nReserved.\nReserved.\nReserved.\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\nReserved.\nReserved.\nReserved.\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\n0 = Normal operation\nThe DISCONADJ field adjusts the trip point for the …\nThe ENVADJ field adjusts the trip point for the envelope …\nReserved.\nReserved.\nReserved.\n0 = Normal operation\nThe DISCONADJ field adjusts the trip point for the …\nThe ENVADJ field adjusts the trip point for the envelope …\nReserved.\nReserved.\nReserved.\n0 = Normal operation\nThe DISCONADJ field adjusts the trip point for the …\nThe ENVADJ field adjusts the trip point for the envelope …\nReserved.\nReserved.\nReserved.\n0 = Normal operation\nThe DISCONADJ field adjusts the trip point for the …\nThe ENVADJ field adjusts the trip point for the envelope …\nReserved.\nReserved.\nReserved.\n0 = Normal operation\nIndicates that the device has been connected on the USB_DP …\nIndicates that the device has disconnected while in …\nIndicates the results of ID pin on MiniAB plug\nIndicates that the host is sending a wake-up after suspend …\nReserved.\nReserved.\nReserved.\nReserved.\nReserved.\nResistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = …\nReserved. Note: This bit should remain clear.\nReserved. Note: This bit should remain clear.\nReserved.\nReserved.\nDecode to select a 45-Ohm resistance to the USB_DN output …\nDecode to select a 45-Ohm resistance to the USB_DP output …\nControls the edge-rate of the current sensing transistors …\nResistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = …\nReserved. Note: This bit should remain clear.\nReserved. Note: This bit should remain clear.\nReserved.\nReserved.\nDecode to select a 45-Ohm resistance to the USB_DN output …\nDecode to select a 45-Ohm resistance to the USB_DP output …\nControls the edge-rate of the current sensing transistors …\nResistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = …\nReserved. Note: This bit should remain clear.\nReserved. Note: This bit should remain clear.\nReserved.\nReserved.\nDecode to select a 45-Ohm resistance to the USB_DN output …\nDecode to select a 45-Ohm resistance to the USB_DP output …\nControls the edge-rate of the current sensing transistors …\nResistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = …\nReserved. Note: This bit should remain clear.\nReserved. Note: This bit should remain clear.\nReserved.\nReserved.\nDecode to select a 45-Ohm resistance to the USB_DN output …\nDecode to select a 45-Ohm resistance to the USB_DP output …\nControls the edge-rate of the current sensing transistors …\nFixed read-only value reflecting the MAJOR field of the …\nFixed read-only value reflecting the MINOR field of the …\nFixed read-only value reflecting the stepping of the RTL …\nWDOG\nWatchdog Control Register\nWatchdog Control Register\nWDOG\nWDOG\nWatchdog Interrupt Control Register\nWatchdog Interrupt Control Register\nWatchdog Miscellaneous Control Register\nWatchdog Miscellaneous Control Register\nWatchdog Reset Status Register\nWatchdog Reset Status Register\nWatchdog Service Register\nWatchdog Service Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nsoftware reset extension, an option way to generate …\nSRS\nWDA\nWDBG\nWDE\nWDT\nWDW\nWDZST\nWT\nusing original way to generate software reset (default)\nusing new way to generate software reset.\nAssert system reset signal.\nNo effect on the system (Default).\nAssert WDOG_B output.\nNo effect on system (Default).\nContinue WDOG timer operation (Default).\nSuspend the watchdog timer.\nDisable the Watchdog (Default).\nEnable the Watchdog.\nNo effect on WDOG_B (Default).\nAssert WDOG_B upon a Watchdog Time-out event.\nContinue WDOG timer operation (Default).\nSuspend WDOG timer operation.\nContinue timer operation (Default).\nSuspend the watchdog timer.\n0.5 Seconds (Default).\n1.0 Seconds.\n1.5 Seconds.\n128 Seconds.\n2.0 Seconds.\nWICT\nWIE\nWTIS\nWICT[7:0] = Time duration between interrupt and time-out …\nWICT[7:0] = Time duration between interrupt and time-out …\nWICT[7:0] = Time duration between interrupt and time-out …\nWICT[7:0] = Time duration between interrupt and time-out …\nDisable Interrupt (Default).\nEnable Interrupt.\nNo interrupt has occurred (Default).\nInterrupt has occurred\nPDE\nPower Down Counter of WDOG is disabled.\nPower Down Counter of WDOG is enabled (Default).\nPOR\nSFTW\nTOUT\nReset is not the result of a power on reset.\nReset is the result of a power on reset.\nReset is not the result of a software reset.\nReset is the result of a software reset.\nReset is not the result of a WDOG timeout.\nReset is the result of a WDOG timeout.\nWSR\nWrite to the Watchdog Service Register (WDOG_WSR).\nWrite to the Watchdog Service Register (WDOG_WSR).\nCrossbar A Control Register 0\nCrossbar A Control Register 0\nCrossbar A Control Register 1\nCrossbar A Control Register 1\nCrossbar Switch\nCrossbar A Select Register 0\nCrossbar A Select Register 0\nCrossbar A Select Register 1\nCrossbar A Select Register 1\nCrossbar A Select Register 10\nCrossbar A Select Register 10\nCrossbar A Select Register 11\nCrossbar A Select Register 11\nCrossbar A Select Register 12\nCrossbar A Select Register 12\nCrossbar A Select Register 13\nCrossbar A Select Register 13\nCrossbar A Select Register 14\nCrossbar A Select Register 14\nCrossbar A Select Register 15\nCrossbar A Select Register 15\nCrossbar A Select Register 16\nCrossbar A Select Register 16\nCrossbar A Select Register 17\nCrossbar A Select Register 17\nCrossbar A Select Register 18\nCrossbar A Select Register 18\nCrossbar A Select Register 19\nCrossbar A Select Register 19\nCrossbar A Select Register 2\nCrossbar A Select Register 2\nCrossbar A Select Register 20\nCrossbar A Select Register 20\nCrossbar A Select Register 21\nCrossbar A Select Register 21\nCrossbar A Select Register 22\nCrossbar A Select Register 22\nCrossbar A Select Register 23\nCrossbar A Select Register 23\nCrossbar A Select Register 24\nCrossbar A Select Register 24\nCrossbar A Select Register 25\nCrossbar A Select Register 25\nCrossbar A Select Register 26\nCrossbar A Select Register 26\nCrossbar A Select Register 27\nCrossbar A Select Register 27\nCrossbar A Select Register 28\nCrossbar A Select Register 28\nCrossbar A Select Register 29\nCrossbar A Select Register 29\nCrossbar A Select Register 3\nCrossbar A Select Register 3\nCrossbar A Select Register 30\nCrossbar A Select Register 30\nCrossbar A Select Register 31\nCrossbar A Select Register 31\nCrossbar A Select Register 32\nCrossbar A Select Register 32\nCrossbar A Select Register 33\nCrossbar A Select Register 33\nCrossbar A Select Register 34\nCrossbar A Select Register 34\nCrossbar A Select Register 35\nCrossbar A Select Register 35\nCrossbar A Select Register 36\nCrossbar A Select Register 36\nCrossbar A Select Register 37\nCrossbar A Select Register 37\nCrossbar A Select Register 38\nCrossbar A Select Register 38\nCrossbar A Select Register 39\nCrossbar A Select Register 39\nCrossbar A Select Register 4\nCrossbar A Select Register 4\nCrossbar A Select Register 40\nCrossbar A Select Register 40\nCrossbar A Select Register 41\nCrossbar A Select Register 41\nCrossbar A Select Register 42\nCrossbar A Select Register 42\nCrossbar A Select Register 43\nCrossbar A Select Register 43\nCrossbar A Select Register 44\nCrossbar A Select Register 44\nCrossbar A Select Register 45\nCrossbar A Select Register 45\nCrossbar A Select Register 46\nCrossbar A Select Register 46\nCrossbar A Select Register 47\nCrossbar A Select Register 47\nCrossbar A Select Register 48\nCrossbar A Select Register 48\nCrossbar A Select Register 49\nCrossbar A Select Register 49\nCrossbar A Select Register 5\nCrossbar A Select Register 5\nCrossbar A Select Register 50\nCrossbar A Select Register 50\nCrossbar A Select Register 51\nCrossbar A Select Register 51\nCrossbar A Select Register 52\nCrossbar A Select Register 52\nCrossbar A Select Register 53\nCrossbar A Select Register 53\nCrossbar A Select Register 54\nCrossbar A Select Register 54\nCrossbar A Select Register 55\nCrossbar A Select Register 55\nCrossbar A Select Register 56\nCrossbar A Select Register 56\nCrossbar A Select Register 57\nCrossbar A Select Register 57\nCrossbar A Select Register 58\nCrossbar A Select Register 58\nCrossbar A Select Register 59\nCrossbar A Select Register 59\nCrossbar A Select Register 6\nCrossbar A Select Register 6\nCrossbar A Select Register 60\nCrossbar A Select Register 60\nCrossbar A Select Register 61\nCrossbar A Select Register 61\nCrossbar A Select Register 62\nCrossbar A Select Register 62\nCrossbar A Select Register 63\nCrossbar A Select Register 63\nCrossbar A Select Register 64\nCrossbar A Select Register 64\nCrossbar A Select Register 65\nCrossbar A Select Register 65\nCrossbar A Select Register 7\nCrossbar A Select Register 7\nCrossbar A Select Register 8\nCrossbar A Select Register 8\nCrossbar A Select Register 9\nCrossbar A Select Register 9\nCrossbar Switch\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDMA Enable for XBAR_OUT0\nDMA Enable for XBAR_OUT1\nActive edge for edge detection on XBAR_OUT0\nActive edge for edge detection on XBAR_OUT1\nInterrupt Enable for XBAR_OUT0\nInterrupt Enable for XBAR_OUT1\nEdge detection status for XBAR_OUT0\nEdge detection status for XBAR_OUT1\nDMA disabled\nDMA enabled\nDMA disabled\nDMA enabled\nSTS0 never asserts\nSTS0 asserts on rising edges of XBAR_OUT0\nSTS0 asserts on falling edges of XBAR_OUT0\nSTS0 asserts on rising and falling edges of XBAR_OUT0\nSTS1 never asserts\nSTS1 asserts on rising edges of XBAR_OUT1\nSTS1 asserts on falling edges of XBAR_OUT1\nSTS1 asserts on rising and falling edges of XBAR_OUT1\nInterrupt disabled\nInterrupt enabled\nInterrupt disabled\nInterrupt enabled\nActive edge not yet detected on XBAR_OUT0\nActive edge detected on XBAR_OUT0\nActive edge not yet detected on XBAR_OUT1\nActive edge detected on XBAR_OUT1\nDMA Enable for XBAR_OUT2\nDMA Enable for XBAR_OUT3\nActive edge for edge detection on XBAR_OUT2\nActive edge for edge detection on XBAR_OUT3\nInterrupt Enable for XBAR_OUT2\nInterrupt Enable for XBAR_OUT3\nEdge detection status for XBAR_OUT2\nEdge detection status for XBAR_OUT3\nDMA disabled\nDMA enabled\nDMA disabled\nDMA enabled\nSTS2 never asserts\nSTS2 asserts on rising edges of XBAR_OUT2\nSTS2 asserts on falling edges of XBAR_OUT2\nSTS2 asserts on rising and falling edges of XBAR_OUT2\nSTS3 never asserts\nSTS3 asserts on rising edges of XBAR_OUT3\nSTS3 asserts on falling edges of XBAR_OUT3\nSTS3 asserts on rising and falling edges of XBAR_OUT3\nInterrupt disabled\nInterrupt enabled\nInterrupt disabled\nInterrupt enabled\nActive edge not yet detected on XBAR_OUT2\nActive edge detected on XBAR_OUT2\nActive edge not yet detected on XBAR_OUT3\nActive edge detected on XBAR_OUT3\nInput (XBARA_INn) to be muxed to XBARA_OUT0 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT1 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT2 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT3 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT20 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT21 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT22 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT23 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT24 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT25 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT26 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT27 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT28 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT29 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT30 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT31 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT32 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT33 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT34 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT35 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT36 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT37 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT38 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT39 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT4 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT5 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT40 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT41 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT42 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT43 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT44 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT45 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT46 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT47 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT48 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT49 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT50 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT51 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT52 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT53 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT54 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT55 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT56 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT57 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT58 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT59 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT6 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT7 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT60 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT61 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT62 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT63 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT64 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT65 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT66 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT67 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT68 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT69 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT70 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT71 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT72 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT73 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT74 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT75 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT76 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT77 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT78 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT79 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT8 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT9 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT80 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT81 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT82 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT83 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT84 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT85 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT86 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT87 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT88 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT89 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT90 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT91 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT92 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT93 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT94 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT95 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT96 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT97 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT98 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT99 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT10 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT11 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT100 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT101 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT102 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT103 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT104 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT105 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT106 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT107 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT108 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT109 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT110 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT111 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT112 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT113 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT114 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT115 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT116 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT117 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT118 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT119 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT12 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT13 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT120 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT121 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT122 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT123 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT124 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT125 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT126 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT127 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT128 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT129 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT130 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT131 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT14 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT15 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT16 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT17 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT18 (refer to …\nInput (XBARA_INn) to be muxed to XBARA_OUT19 (refer to …\nXTAL OSC (LP) Control Register\nXTAL OSC (LP) Control Register\nXTAL OSC (LP) Control Register\nXTAL OSC (LP) Control Register\nXTAL OSC (LP) Control Register\nXTAL OSC (LP) Control Register\nXTAL OSC (LP) Control Register\nXTAL OSC (LP) Control Register\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nXTAL OSC Configuration 0 Register\nXTAL OSC Configuration 0 Register\nXTAL OSC Configuration 0 Register\nXTAL OSC Configuration 0 Register\nXTAL OSC Configuration 0 Register\nXTAL OSC Configuration 0 Register\nXTAL OSC Configuration 0 Register\nXTAL OSC Configuration 0 Register\nXTAL OSC Configuration 1 Register\nXTAL OSC Configuration 1 Register\nXTAL OSC Configuration 1 Register\nXTAL OSC Configuration 1 Register\nXTAL OSC Configuration 1 Register\nXTAL OSC Configuration 1 Register\nXTAL OSC Configuration 1 Register\nXTAL OSC Configuration 1 Register\nXTAL OSC Configuration 2 Register\nXTAL OSC Configuration 2 Register\nXTAL OSC Configuration 2 Register\nXTAL OSC Configuration 2 Register\nXTAL OSC Configuration 2 Register\nXTAL OSC Configuration 2 Register\nXTAL OSC Configuration 2 Register\nXTAL OSC Configuration 2 Register\nXTALOSC24M\nXTALOSC24M\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nCPU power gate control. Used as software override. Test …\nDisplay logic power gate control. Used as software …\nGPU power gate control. Used as software mask. Set to zero …\nL1 power gate control. Used as software override. Not …\nL2 power gate control. Used as software override. Not …\nBandgap select. Not related to oscillator.\nLow power bandgap test bit. Not related to oscillator.\nDisplay power gate control. Used as software mask. Set to …\nSelect the source for the 24MHz clock.\nFor debug purposes only\nRC Osc. enable control.\nLow power reftop ibias disable. Not related to oscillator.\nSpecifies the time delay between when the 24MHz xtal is …\nStatus of the 24MHz xtal oscillator.\nNormal power bandgap\nLow power bandgap\nXTAL OSC\nRC OSC\nUse XTAL OSC to source the 24MHz clock\nUse RC OSC\n0.25ms\n0.5ms\n1ms\n2ms\nNot stable\nStable and ready to use\nCPU power gate control. Used as software override. Test …\nDisplay logic power gate control. Used as software …\nGPU power gate control. Used as software mask. Set to zero …\nL1 power gate control. Used as software override. Not …\nL2 power gate control. Used as software override. Not …\nBandgap select. Not related to oscillator.\nLow power bandgap test bit. Not related to oscillator.\nDisplay power gate control. Used as software mask. Set to …\nSelect the source for the 24MHz clock.\nFor debug purposes only\nRC Osc. enable control.\nLow power reftop ibias disable. Not related to oscillator.\nSpecifies the time delay between when the 24MHz xtal is …\nStatus of the 24MHz xtal oscillator.\nNormal power bandgap\nLow power bandgap\nXTAL OSC\nRC OSC\nUse XTAL OSC to source the 24MHz clock\nUse RC OSC\n0.25ms\n0.5ms\n1ms\n2ms\nNot stable\nStable and ready to use\nCPU power gate control. Used as software override. Test …\nDisplay logic power gate control. Used as software …\nGPU power gate control. Used as software mask. Set to zero …\nL1 power gate control. Used as software override. Not …\nL2 power gate control. Used as software override. Not …\nBandgap select. Not related to oscillator.\nLow power bandgap test bit. Not related to oscillator.\nDisplay power gate control. Used as software mask. Set to …\nSelect the source for the 24MHz clock.\nFor debug purposes only\nRC Osc. enable control.\nLow power reftop ibias disable. Not related to oscillator.\nSpecifies the time delay between when the 24MHz xtal is …\nStatus of the 24MHz xtal oscillator.\nNormal power bandgap\nLow power bandgap\nXTAL OSC\nRC OSC\nUse XTAL OSC to source the 24MHz clock\nUse RC OSC\n0.25ms\n0.5ms\n1ms\n2ms\nNot stable\nStable and ready to use\nCPU power gate control. Used as software override. Test …\nDisplay logic power gate control. Used as software …\nGPU power gate control. Used as software mask. Set to zero …\nL1 power gate control. Used as software override. Not …\nL2 power gate control. Used as software override. Not …\nBandgap select. Not related to oscillator.\nLow power bandgap test bit. Not related to oscillator.\nDisplay power gate control. Used as software mask. Set to …\nSelect the source for the 24MHz clock.\nFor debug purposes only\nRC Osc. enable control.\nLow power reftop ibias disable. Not related to oscillator.\nSpecifies the time delay between when the 24MHz xtal is …\nStatus of the 24MHz xtal oscillator.\nNormal power bandgap\nLow power bandgap\nXTAL OSC\nRC OSC\nUse XTAL OSC to source the 24MHz clock\nUse RC OSC\n0.25ms\n0.5ms\n1ms\n2ms\nNot stable\nStable and ready to use\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to power-down the analog bandgap reference …\nControl bit to disable the self-bias circuit in the analog …\nNot related to oscillator.\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.Not related to …\nPredivider for the source clock of the PLL’s. Not …\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAll analog except rtc powered down on stop mode assertion. …\nCertain analog functions such as certain regulators left …\nXtalOsc=off, RCOsc=on, Old BG=on, New BG=off.\nXtalOsc=off, RCOsc=on, Old BG=off, New BG=on.\nDivide by 1\nDivide by 2\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to power-down the analog bandgap reference …\nControl bit to disable the self-bias circuit in the analog …\nNot related to oscillator.\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.Not related to …\nPredivider for the source clock of the PLL’s. Not …\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAll analog except rtc powered down on stop mode assertion. …\nCertain analog functions such as certain regulators left …\nXtalOsc=off, RCOsc=on, Old BG=on, New BG=off.\nXtalOsc=off, RCOsc=on, Old BG=off, New BG=on.\nDivide by 1\nDivide by 2\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to power-down the analog bandgap reference …\nControl bit to disable the self-bias circuit in the analog …\nNot related to oscillator.\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.Not related to …\nPredivider for the source clock of the PLL’s. Not …\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAll analog except rtc powered down on stop mode assertion. …\nCertain analog functions such as certain regulators left …\nXtalOsc=off, RCOsc=on, Old BG=on, New BG=off.\nXtalOsc=off, RCOsc=on, Old BG=off, New BG=on.\nDivide by 1\nDivide by 2\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to power-down the analog bandgap reference …\nControl bit to disable the self-bias circuit in the analog …\nNot related to oscillator.\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.Not related to …\nPredivider for the source clock of the PLL’s. Not …\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAll analog except rtc powered down on stop mode assertion. …\nCertain analog functions such as certain regulators left …\nXtalOsc=off, RCOsc=on, Old BG=on, New BG=off.\nXtalOsc=off, RCOsc=on, Old BG=off, New BG=on.\nDivide by 1\nDivide by 2\nBypasses any calculated RC tuning value and uses the …\nEnables the tuning logic to calculate new RC tuning values\nNegative hysteresis value\nPositive hysteresis value\nInvert the stepping of the calculated RC tuning value.\nRC osc. tuning values.\nThe current tuning value in use.\nStart/stop bit for the RC tuning calculation logic. If …\nBypasses any calculated RC tuning value and uses the …\nEnables the tuning logic to calculate new RC tuning values\nNegative hysteresis value\nPositive hysteresis value\nInvert the stepping of the calculated RC tuning value.\nRC osc. tuning values.\nThe current tuning value in use.\nStart/stop bit for the RC tuning calculation logic. If …\nBypasses any calculated RC tuning value and uses the …\nEnables the tuning logic to calculate new RC tuning values\nNegative hysteresis value\nPositive hysteresis value\nInvert the stepping of the calculated RC tuning value.\nRC osc. tuning values.\nThe current tuning value in use.\nStart/stop bit for the RC tuning calculation logic. If …\nBypasses any calculated RC tuning value and uses the …\nEnables the tuning logic to calculate new RC tuning values\nNegative hysteresis value\nPositive hysteresis value\nInvert the stepping of the calculated RC tuning value.\nRC osc. tuning values.\nThe current tuning value in use.\nStart/stop bit for the RC tuning calculation logic. If …\nThe current tuning value in use.\nThe target count used to tune the RC OSC frequency\nThe current tuning value in use.\nThe target count used to tune the RC OSC frequency\nThe current tuning value in use.\nThe target count used to tune the RC OSC frequency\nThe current tuning value in use.\nThe target count used to tune the RC OSC frequency\nFlag indicates that the count_1m count wasn’t reached …\nThe target count used to tune the 1MHz clock frequency\nEnable the 1MHz clock output. 0 - disabled; 1 - enabled.\nMux the corrected or uncorrected 1MHz clock to the output\nFlag indicates that the count_1m count wasn’t reached …\nThe target count used to tune the 1MHz clock frequency\nEnable the 1MHz clock output. 0 - disabled; 1 - enabled.\nMux the corrected or uncorrected 1MHz clock to the output\nFlag indicates that the count_1m count wasn’t reached …\nThe target count used to tune the 1MHz clock frequency\nEnable the 1MHz clock output. 0 - disabled; 1 - enabled.\nMux the corrected or uncorrected 1MHz clock to the output\nFlag indicates that the count_1m count wasn’t reached …\nThe target count used to tune the 1MHz clock frequency\nEnable the 1MHz clock output. 0 - disabled; 1 - enabled.\nMux the corrected or uncorrected 1MHz clock to the output")