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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="DW_apb_i2c address block"><title>rp2040_pac::i2c0 - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module i2c0</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#modules">Modules</a></li><li><a href="#structs">Structs</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../index.html">rp2040_pac</a>::<wbr><a class="mod" href="#">i2c0</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../src/rp2040_pac/i2c0.rs.html#1-862">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>DW_apb_i2c address block</p>
<p>List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are <em>fixed</em> values, set at hardware design time):</p>
<p>IC_ULTRA_FAST_MODE ……………. 0x0<br />
IC_UFM_TBUF_CNT_DEFAULT ……….. 0x8<br />
IC_UFM_SCL_LOW_COUNT ………….. 0x0008<br />
IC_UFM_SCL_HIGH_COUNT …………. 0x0006<br />
IC_TX_TL …………………….. 0x0<br />
IC_TX_CMD_BLOCK ………………. 0x1<br />
IC_HAS_DMA …………………… 0x1<br />
IC_HAS_ASYNC_FIFO …………….. 0x0<br />
IC_SMBUS_ARP …………………. 0x0<br />
IC_FIRST_DATA_BYTE_STATUS ……… 0x1<br />
IC_INTR_IO …………………… 0x1<br />
IC_MASTER_MODE ……………….. 0x1<br />
IC_DEFAULT_ACK_GENERAL_CALL ……. 0x1<br />
IC_INTR_POL ………………….. 0x1<br />
IC_OPTIONAL_SAR ………………. 0x0<br />
IC_DEFAULT_TAR_SLAVE_ADDR ……… 0x055<br />
IC_DEFAULT_SLAVE_ADDR …………. 0x055<br />
IC_DEFAULT_HS_SPKLEN ………….. 0x1<br />
IC_FS_SCL_HIGH_COUNT ………….. 0x0006<br />
IC_HS_SCL_LOW_COUNT …………… 0x0008<br />
IC_DEVICE_ID_VALUE ……………. 0x0<br />
IC_10BITADDR_MASTER …………… 0x0<br />
IC_CLK_FREQ_OPTIMIZATION ………. 0x0<br />
IC_DEFAULT_FS_SPKLEN ………….. 0x7<br />
IC_ADD_ENCODED_PARAMS …………. 0x0<br />
IC_DEFAULT_SDA_HOLD …………… 0x000001<br />
IC_DEFAULT_SDA_SETUP ………….. 0x64<br />
IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0<br />
IC_CLOCK_PERIOD ………………. 100<br />
IC_EMPTYFIFO_HOLD_MASTER_EN ……. 1<br />
IC_RESTART_EN ………………… 0x1<br />
IC_TX_CMD_BLOCK_DEFAULT ……….. 0x0<br />
IC_BUS_CLEAR_FEATURE ………….. 0x0<br />
IC_CAP_LOADING ……………….. 100<br />
IC_FS_SCL_LOW_COUNT …………… 0x000d<br />
APB_DATA_WIDTH ……………….. 32<br />
IC_SDA_STUCK_TIMEOUT_DEFAULT …… 0xffffffff<br />
IC_SLV_DATA_NACK_ONLY …………. 0x1<br />
IC_10BITADDR_SLAVE ……………. 0x0<br />
IC_CLK_TYPE ………………….. 0x0<br />
IC_SMBUS_UDID_MSB …………….. 0x0<br />
IC_SMBUS_SUSPEND_ALERT ………… 0x0<br />
IC_HS_SCL_HIGH_COUNT ………….. 0x0006<br />
IC_SLV_RESTART_DET_EN …………. 0x1<br />
IC_SMBUS …………………….. 0x0<br />
IC_OPTIONAL_SAR_DEFAULT ……….. 0x0<br />
IC_PERSISTANT_SLV_ADDR_DEFAULT …. 0x0<br />
IC_USE_COUNTS ………………… 0x0<br />
IC_RX_BUFFER_DEPTH ……………. 16<br />
IC_SCL_STUCK_TIMEOUT_DEFAULT …… 0xffffffff<br />
IC_RX_FULL_HLD_BUS_EN …………. 0x1<br />
IC_SLAVE_DISABLE ……………… 0x1<br />
IC_RX_TL …………………….. 0x0<br />
IC_DEVICE_ID …………………. 0x0<br />
IC_HC_COUNT_VALUES ……………. 0x0<br />
I2C_DYNAMIC_TAR_UPDATE ………… 0<br />
IC_SMBUS_CLK_LOW_MEXT_DEFAULT ….. 0xffffffff<br />
IC_SMBUS_CLK_LOW_SEXT_DEFAULT ….. 0xffffffff<br />
IC_HS_MASTER_CODE …………….. 0x1<br />
IC_SMBUS_RST_IDLE_CNT_DEFAULT ….. 0xffff<br />
IC_SMBUS_UDID_LSB_DEFAULT ……… 0xffffffff<br />
IC_SS_SCL_HIGH_COUNT ………….. 0x0028<br />
IC_SS_SCL_LOW_COUNT …………… 0x002f<br />
IC_MAX_SPEED_MODE …………….. 0x2<br />
IC_STAT_FOR_CLK_STRETCH ……….. 0x0<br />
IC_STOP_DET_IF_MASTER_ACTIVE …… 0x0<br />
IC_DEFAULT_UFM_SPKLEN …………. 0x1<br />
IC_TX_BUFFER_DEPTH ……………. 16</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="ic_ack_general_call/index.html" title="mod rp2040_pac::i2c0::ic_ack_general_call">ic_<wbr>ack_<wbr>general_<wbr>call</a></div><div class="desc docblock-short">I2C ACK General Call Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_activity/index.html" title="mod rp2040_pac::i2c0::ic_clr_activity">ic_<wbr>clr_<wbr>activity</a></div><div class="desc docblock-short">Clear ACTIVITY Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_gen_call/index.html" title="mod rp2040_pac::i2c0::ic_clr_gen_call">ic_<wbr>clr_<wbr>gen_<wbr>call</a></div><div class="desc docblock-short">Clear GEN_CALL Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_intr/index.html" title="mod rp2040_pac::i2c0::ic_clr_intr">ic_<wbr>clr_<wbr>intr</a></div><div class="desc docblock-short">Clear Combined and Individual Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_rd_req/index.html" title="mod rp2040_pac::i2c0::ic_clr_rd_req">ic_<wbr>clr_<wbr>rd_<wbr>req</a></div><div class="desc docblock-short">Clear RD_REQ Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_restart_det/index.html" title="mod rp2040_pac::i2c0::ic_clr_restart_det">ic_<wbr>clr_<wbr>restart_<wbr>det</a></div><div class="desc docblock-short">Clear RESTART_DET Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_rx_done/index.html" title="mod rp2040_pac::i2c0::ic_clr_rx_done">ic_<wbr>clr_<wbr>rx_<wbr>done</a></div><div class="desc docblock-short">Clear RX_DONE Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_rx_over/index.html" title="mod rp2040_pac::i2c0::ic_clr_rx_over">ic_<wbr>clr_<wbr>rx_<wbr>over</a></div><div class="desc docblock-short">Clear RX_OVER Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_rx_under/index.html" title="mod rp2040_pac::i2c0::ic_clr_rx_under">ic_<wbr>clr_<wbr>rx_<wbr>under</a></div><div class="desc docblock-short">Clear RX_UNDER Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_start_det/index.html" title="mod rp2040_pac::i2c0::ic_clr_start_det">ic_<wbr>clr_<wbr>start_<wbr>det</a></div><div class="desc docblock-short">Clear START_DET Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_stop_det/index.html" title="mod rp2040_pac::i2c0::ic_clr_stop_det">ic_<wbr>clr_<wbr>stop_<wbr>det</a></div><div class="desc docblock-short">Clear STOP_DET Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_tx_abrt/index.html" title="mod rp2040_pac::i2c0::ic_clr_tx_abrt">ic_<wbr>clr_<wbr>tx_<wbr>abrt</a></div><div class="desc docblock-short">Clear TX_ABRT Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_clr_tx_over/index.html" title="mod rp2040_pac::i2c0::ic_clr_tx_over">ic_<wbr>clr_<wbr>tx_<wbr>over</a></div><div class="desc docblock-short">Clear TX_OVER Interrupt Register</div></li><li><div class="item-name"><a class="mod" href="ic_comp_param_1/index.html" title="mod rp2040_pac::i2c0::ic_comp_param_1">ic_<wbr>comp_<wbr>param_<wbr>1</a></div><div class="desc docblock-short">Component Parameter Register 1</div></li><li><div class="item-name"><a class="mod" href="ic_comp_type/index.html" title="mod rp2040_pac::i2c0::ic_comp_type">ic_<wbr>comp_<wbr>type</a></div><div class="desc docblock-short">I2C Component Type Register</div></li><li><div class="item-name"><a class="mod" href="ic_comp_version/index.html" title="mod rp2040_pac::i2c0::ic_comp_version">ic_<wbr>comp_<wbr>version</a></div><div class="desc docblock-short">I2C Component Version Register</div></li><li><div class="item-name"><a class="mod" href="ic_con/index.html" title="mod rp2040_pac::i2c0::ic_con">ic_con</a></div><div class="desc docblock-short">I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0]
register being set to 0. Writes at other times have no effect.</div></li><li><div class="item-name"><a class="mod" href="ic_data_cmd/index.html" title="mod rp2040_pac::i2c0::ic_data_cmd">ic_<wbr>data_<wbr>cmd</a></div><div class="desc docblock-short">I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.</div></li><li><div class="item-name"><a class="mod" href="ic_dma_cr/index.html" title="mod rp2040_pac::i2c0::ic_dma_cr">ic_<wbr>dma_<wbr>cr</a></div><div class="desc docblock-short">DMA Control Register</div></li><li><div class="item-name"><a class="mod" href="ic_dma_rdlr/index.html" title="mod rp2040_pac::i2c0::ic_dma_rdlr">ic_<wbr>dma_<wbr>rdlr</a></div><div class="desc docblock-short">I2C Receive Data Level Register</div></li><li><div class="item-name"><a class="mod" href="ic_dma_tdlr/index.html" title="mod rp2040_pac::i2c0::ic_dma_tdlr">ic_<wbr>dma_<wbr>tdlr</a></div><div class="desc docblock-short">DMA Transmit Data Level Register</div></li><li><div class="item-name"><a class="mod" href="ic_enable/index.html" title="mod rp2040_pac::i2c0::ic_enable">ic_<wbr>enable</a></div><div class="desc docblock-short">I2C Enable Register</div></li><li><div class="item-name"><a class="mod" href="ic_enable_status/index.html" title="mod rp2040_pac::i2c0::ic_enable_status">ic_<wbr>enable_<wbr>status</a></div><div class="desc docblock-short">I2C Enable Status Register</div></li><li><div class="item-name"><a class="mod" href="ic_fs_scl_hcnt/index.html" title="mod rp2040_pac::i2c0::ic_fs_scl_hcnt">ic_<wbr>fs_<wbr>scl_<wbr>hcnt</a></div><div class="desc docblock-short">Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register</div></li><li><div class="item-name"><a class="mod" href="ic_fs_scl_lcnt/index.html" title="mod rp2040_pac::i2c0::ic_fs_scl_lcnt">ic_<wbr>fs_<wbr>scl_<wbr>lcnt</a></div><div class="desc docblock-short">Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register</div></li><li><div class="item-name"><a class="mod" href="ic_fs_spklen/index.html" title="mod rp2040_pac::i2c0::ic_fs_spklen">ic_<wbr>fs_<wbr>spklen</a></div><div class="desc docblock-short">I2C SS, FS or FM+ spike suppression limit</div></li><li><div class="item-name"><a class="mod" href="ic_intr_mask/index.html" title="mod rp2040_pac::i2c0::ic_intr_mask">ic_<wbr>intr_<wbr>mask</a></div><div class="desc docblock-short">I2C Interrupt Mask Register.</div></li><li><div class="item-name"><a class="mod" href="ic_intr_stat/index.html" title="mod rp2040_pac::i2c0::ic_intr_stat">ic_<wbr>intr_<wbr>stat</a></div><div class="desc docblock-short">I2C Interrupt Status Register</div></li><li><div class="item-name"><a class="mod" href="ic_raw_intr_stat/index.html" title="mod rp2040_pac::i2c0::ic_raw_intr_stat">ic_<wbr>raw_<wbr>intr_<wbr>stat</a></div><div class="desc docblock-short">I2C Raw Interrupt Status Register</div></li><li><div class="item-name"><a class="mod" href="ic_rx_tl/index.html" title="mod rp2040_pac::i2c0::ic_rx_tl">ic_<wbr>rx_<wbr>tl</a></div><div class="desc docblock-short">I2C Receive FIFO Threshold Register</div></li><li><div class="item-name"><a class="mod" href="ic_rxflr/index.html" title="mod rp2040_pac::i2c0::ic_rxflr">ic_<wbr>rxflr</a></div><div class="desc docblock-short">I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.</div></li><li><div class="item-name"><a class="mod" href="ic_sar/index.html" title="mod rp2040_pac::i2c0::ic_sar">ic_sar</a></div><div class="desc docblock-short">I2C Slave Address Register</div></li><li><div class="item-name"><a class="mod" href="ic_sda_hold/index.html" title="mod rp2040_pac::i2c0::ic_sda_hold">ic_<wbr>sda_<wbr>hold</a></div><div class="desc docblock-short">I2C SDA Hold Time Length Register</div></li><li><div class="item-name"><a class="mod" href="ic_sda_setup/index.html" title="mod rp2040_pac::i2c0::ic_sda_setup">ic_<wbr>sda_<wbr>setup</a></div><div class="desc docblock-short">I2C SDA Setup Register</div></li><li><div class="item-name"><a class="mod" href="ic_slv_data_nack_only/index.html" title="mod rp2040_pac::i2c0::ic_slv_data_nack_only">ic_<wbr>slv_<wbr>data_<wbr>nack_<wbr>only</a></div><div class="desc docblock-short">Generate Slave Data NACK Register</div></li><li><div class="item-name"><a class="mod" href="ic_ss_scl_hcnt/index.html" title="mod rp2040_pac::i2c0::ic_ss_scl_hcnt">ic_<wbr>ss_<wbr>scl_<wbr>hcnt</a></div><div class="desc docblock-short">Standard Speed I2C Clock SCL High Count Register</div></li><li><div class="item-name"><a class="mod" href="ic_ss_scl_lcnt/index.html" title="mod rp2040_pac::i2c0::ic_ss_scl_lcnt">ic_<wbr>ss_<wbr>scl_<wbr>lcnt</a></div><div class="desc docblock-short">Standard Speed I2C Clock SCL Low Count Register</div></li><li><div class="item-name"><a class="mod" href="ic_status/index.html" title="mod rp2040_pac::i2c0::ic_status">ic_<wbr>status</a></div><div class="desc docblock-short">I2C Status Register</div></li><li><div class="item-name"><a class="mod" href="ic_tar/index.html" title="mod rp2040_pac::i2c0::ic_tar">ic_tar</a></div><div class="desc docblock-short">I2C Target Address Register</div></li><li><div class="item-name"><a class="mod" href="ic_tx_abrt_source/index.html" title="mod rp2040_pac::i2c0::ic_tx_abrt_source">ic_<wbr>tx_<wbr>abrt_<wbr>source</a></div><div class="desc docblock-short">I2C Transmit Abort Source Register</div></li><li><div class="item-name"><a class="mod" href="ic_tx_tl/index.html" title="mod rp2040_pac::i2c0::ic_tx_tl">ic_<wbr>tx_<wbr>tl</a></div><div class="desc docblock-short">I2C Transmit FIFO Threshold Register</div></li><li><div class="item-name"><a class="mod" href="ic_txflr/index.html" title="mod rp2040_pac::i2c0::ic_txflr">ic_<wbr>txflr</a></div><div class="desc docblock-short">I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::i2c0::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.IC_ACK_GENERAL_CALL.html" title="type rp2040_pac::i2c0::IC_ACK_GENERAL_CALL">IC_<wbr>ACK_<wbr>GENERA<wbr>L_<wbr>CALL</a></div><div class="desc docblock-short">IC_ACK_GENERAL_CALL (rw) register accessor: I2C ACK General Call Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_ACTIVITY.html" title="type rp2040_pac::i2c0::IC_CLR_ACTIVITY">IC_<wbr>CLR_<wbr>ACTIVITY</a></div><div class="desc docblock-short">IC_CLR_ACTIVITY (r) register accessor: Clear ACTIVITY Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_GEN_CALL.html" title="type rp2040_pac::i2c0::IC_CLR_GEN_CALL">IC_<wbr>CLR_<wbr>GEN_<wbr>CALL</a></div><div class="desc docblock-short">IC_CLR_GEN_CALL (r) register accessor: Clear GEN_CALL Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_INTR.html" title="type rp2040_pac::i2c0::IC_CLR_INTR">IC_<wbr>CLR_<wbr>INTR</a></div><div class="desc docblock-short">IC_CLR_INTR (r) register accessor: Clear Combined and Individual Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_RD_REQ.html" title="type rp2040_pac::i2c0::IC_CLR_RD_REQ">IC_<wbr>CLR_<wbr>RD_<wbr>REQ</a></div><div class="desc docblock-short">IC_CLR_RD_REQ (r) register accessor: Clear RD_REQ Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_RESTART_DET.html" title="type rp2040_pac::i2c0::IC_CLR_RESTART_DET">IC_<wbr>CLR_<wbr>RESTAR<wbr>T_<wbr>DET</a></div><div class="desc docblock-short">IC_CLR_RESTART_DET (r) register accessor: Clear RESTART_DET Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_RX_DONE.html" title="type rp2040_pac::i2c0::IC_CLR_RX_DONE">IC_<wbr>CLR_<wbr>RX_<wbr>DONE</a></div><div class="desc docblock-short">IC_CLR_RX_DONE (r) register accessor: Clear RX_DONE Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_RX_OVER.html" title="type rp2040_pac::i2c0::IC_CLR_RX_OVER">IC_<wbr>CLR_<wbr>RX_<wbr>OVER</a></div><div class="desc docblock-short">IC_CLR_RX_OVER (r) register accessor: Clear RX_OVER Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_RX_UNDER.html" title="type rp2040_pac::i2c0::IC_CLR_RX_UNDER">IC_<wbr>CLR_<wbr>RX_<wbr>UNDER</a></div><div class="desc docblock-short">IC_CLR_RX_UNDER (r) register accessor: Clear RX_UNDER Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_START_DET.html" title="type rp2040_pac::i2c0::IC_CLR_START_DET">IC_<wbr>CLR_<wbr>STAR<wbr>T_<wbr>DET</a></div><div class="desc docblock-short">IC_CLR_START_DET (r) register accessor: Clear START_DET Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_STOP_DET.html" title="type rp2040_pac::i2c0::IC_CLR_STOP_DET">IC_<wbr>CLR_<wbr>STOP_<wbr>DET</a></div><div class="desc docblock-short">IC_CLR_STOP_DET (r) register accessor: Clear STOP_DET Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_TX_ABRT.html" title="type rp2040_pac::i2c0::IC_CLR_TX_ABRT">IC_<wbr>CLR_<wbr>TX_<wbr>ABRT</a></div><div class="desc docblock-short">IC_CLR_TX_ABRT (r) register accessor: Clear TX_ABRT Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CLR_TX_OVER.html" title="type rp2040_pac::i2c0::IC_CLR_TX_OVER">IC_<wbr>CLR_<wbr>TX_<wbr>OVER</a></div><div class="desc docblock-short">IC_CLR_TX_OVER (r) register accessor: Clear TX_OVER Interrupt Register</div></li><li><div class="item-name"><a class="type" href="type.IC_COMP_PARAM_1.html" title="type rp2040_pac::i2c0::IC_COMP_PARAM_1">IC_<wbr>COMP_<wbr>PARA<wbr>M_<wbr>1</a></div><div class="desc docblock-short">IC_COMP_PARAM_1 (r) register accessor: Component Parameter Register 1</div></li><li><div class="item-name"><a class="type" href="type.IC_COMP_TYPE.html" title="type rp2040_pac::i2c0::IC_COMP_TYPE">IC_<wbr>COMP_<wbr>TYPE</a></div><div class="desc docblock-short">IC_COMP_TYPE (r) register accessor: I2C Component Type Register</div></li><li><div class="item-name"><a class="type" href="type.IC_COMP_VERSION.html" title="type rp2040_pac::i2c0::IC_COMP_VERSION">IC_<wbr>COMP_<wbr>VERSION</a></div><div class="desc docblock-short">IC_COMP_VERSION (r) register accessor: I2C Component Version Register</div></li><li><div class="item-name"><a class="type" href="type.IC_CON.html" title="type rp2040_pac::i2c0::IC_CON">IC_CON</a></div><div class="desc docblock-short">IC_CON (rw) register accessor: I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0]
register being set to 0. Writes at other times have no effect.</div></li><li><div class="item-name"><a class="type" href="type.IC_DATA_CMD.html" title="type rp2040_pac::i2c0::IC_DATA_CMD">IC_<wbr>DATA_<wbr>CMD</a></div><div class="desc docblock-short">IC_DATA_CMD (rw) register accessor: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.</div></li><li><div class="item-name"><a class="type" href="type.IC_DMA_CR.html" title="type rp2040_pac::i2c0::IC_DMA_CR">IC_<wbr>DMA_<wbr>CR</a></div><div class="desc docblock-short">IC_DMA_CR (rw) register accessor: DMA Control Register</div></li><li><div class="item-name"><a class="type" href="type.IC_DMA_RDLR.html" title="type rp2040_pac::i2c0::IC_DMA_RDLR">IC_<wbr>DMA_<wbr>RDLR</a></div><div class="desc docblock-short">IC_DMA_RDLR (rw) register accessor: I2C Receive Data Level Register</div></li><li><div class="item-name"><a class="type" href="type.IC_DMA_TDLR.html" title="type rp2040_pac::i2c0::IC_DMA_TDLR">IC_<wbr>DMA_<wbr>TDLR</a></div><div class="desc docblock-short">IC_DMA_TDLR (rw) register accessor: DMA Transmit Data Level Register</div></li><li><div class="item-name"><a class="type" href="type.IC_ENABLE.html" title="type rp2040_pac::i2c0::IC_ENABLE">IC_<wbr>ENABLE</a></div><div class="desc docblock-short">IC_ENABLE (rw) register accessor: I2C Enable Register</div></li><li><div class="item-name"><a class="type" href="type.IC_ENABLE_STATUS.html" title="type rp2040_pac::i2c0::IC_ENABLE_STATUS">IC_<wbr>ENABL<wbr>E_<wbr>STATUS</a></div><div class="desc docblock-short">IC_ENABLE_STATUS (r) register accessor: I2C Enable Status Register</div></li><li><div class="item-name"><a class="type" href="type.IC_FS_SCL_HCNT.html" title="type rp2040_pac::i2c0::IC_FS_SCL_HCNT">IC_<wbr>FS_<wbr>SCL_<wbr>HCNT</a></div><div class="desc docblock-short">IC_FS_SCL_HCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register</div></li><li><div class="item-name"><a class="type" href="type.IC_FS_SCL_LCNT.html" title="type rp2040_pac::i2c0::IC_FS_SCL_LCNT">IC_<wbr>FS_<wbr>SCL_<wbr>LCNT</a></div><div class="desc docblock-short">IC_FS_SCL_LCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register</div></li><li><div class="item-name"><a class="type" href="type.IC_FS_SPKLEN.html" title="type rp2040_pac::i2c0::IC_FS_SPKLEN">IC_<wbr>FS_<wbr>SPKLEN</a></div><div class="desc docblock-short">IC_FS_SPKLEN (rw) register accessor: I2C SS, FS or FM+ spike suppression limit</div></li><li><div class="item-name"><a class="type" href="type.IC_INTR_MASK.html" title="type rp2040_pac::i2c0::IC_INTR_MASK">IC_<wbr>INTR_<wbr>MASK</a></div><div class="desc docblock-short">IC_INTR_MASK (rw) register accessor: I2C Interrupt Mask Register.</div></li><li><div class="item-name"><a class="type" href="type.IC_INTR_STAT.html" title="type rp2040_pac::i2c0::IC_INTR_STAT">IC_<wbr>INTR_<wbr>STAT</a></div><div class="desc docblock-short">IC_INTR_STAT (r) register accessor: I2C Interrupt Status Register</div></li><li><div class="item-name"><a class="type" href="type.IC_RAW_INTR_STAT.html" title="type rp2040_pac::i2c0::IC_RAW_INTR_STAT">IC_<wbr>RAW_<wbr>INTR_<wbr>STAT</a></div><div class="desc docblock-short">IC_RAW_INTR_STAT (r) register accessor: I2C Raw Interrupt Status Register</div></li><li><div class="item-name"><a class="type" href="type.IC_RXFLR.html" title="type rp2040_pac::i2c0::IC_RXFLR">IC_<wbr>RXFLR</a></div><div class="desc docblock-short">IC_RXFLR (r) register accessor: I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.</div></li><li><div class="item-name"><a class="type" href="type.IC_RX_TL.html" title="type rp2040_pac::i2c0::IC_RX_TL">IC_<wbr>RX_<wbr>TL</a></div><div class="desc docblock-short">IC_RX_TL (rw) register accessor: I2C Receive FIFO Threshold Register</div></li><li><div class="item-name"><a class="type" href="type.IC_SAR.html" title="type rp2040_pac::i2c0::IC_SAR">IC_SAR</a></div><div class="desc docblock-short">IC_SAR (rw) register accessor: I2C Slave Address Register</div></li><li><div class="item-name"><a class="type" href="type.IC_SDA_HOLD.html" title="type rp2040_pac::i2c0::IC_SDA_HOLD">IC_<wbr>SDA_<wbr>HOLD</a></div><div class="desc docblock-short">IC_SDA_HOLD (rw) register accessor: I2C SDA Hold Time Length Register</div></li><li><div class="item-name"><a class="type" href="type.IC_SDA_SETUP.html" title="type rp2040_pac::i2c0::IC_SDA_SETUP">IC_<wbr>SDA_<wbr>SETUP</a></div><div class="desc docblock-short">IC_SDA_SETUP (rw) register accessor: I2C SDA Setup Register</div></li><li><div class="item-name"><a class="type" href="type.IC_SLV_DATA_NACK_ONLY.html" title="type rp2040_pac::i2c0::IC_SLV_DATA_NACK_ONLY">IC_<wbr>SLV_<wbr>DATA_<wbr>NACK_<wbr>ONLY</a></div><div class="desc docblock-short">IC_SLV_DATA_NACK_ONLY (rw) register accessor: Generate Slave Data NACK Register</div></li><li><div class="item-name"><a class="type" href="type.IC_SS_SCL_HCNT.html" title="type rp2040_pac::i2c0::IC_SS_SCL_HCNT">IC_<wbr>SS_<wbr>SCL_<wbr>HCNT</a></div><div class="desc docblock-short">IC_SS_SCL_HCNT (rw) register accessor: Standard Speed I2C Clock SCL High Count Register</div></li><li><div class="item-name"><a class="type" href="type.IC_SS_SCL_LCNT.html" title="type rp2040_pac::i2c0::IC_SS_SCL_LCNT">IC_<wbr>SS_<wbr>SCL_<wbr>LCNT</a></div><div class="desc docblock-short">IC_SS_SCL_LCNT (rw) register accessor: Standard Speed I2C Clock SCL Low Count Register</div></li><li><div class="item-name"><a class="type" href="type.IC_STATUS.html" title="type rp2040_pac::i2c0::IC_STATUS">IC_<wbr>STATUS</a></div><div class="desc docblock-short">IC_STATUS (r) register accessor: I2C Status Register</div></li><li><div class="item-name"><a class="type" href="type.IC_TAR.html" title="type rp2040_pac::i2c0::IC_TAR">IC_TAR</a></div><div class="desc docblock-short">IC_TAR (rw) register accessor: I2C Target Address Register</div></li><li><div class="item-name"><a class="type" href="type.IC_TXFLR.html" title="type rp2040_pac::i2c0::IC_TXFLR">IC_<wbr>TXFLR</a></div><div class="desc docblock-short">IC_TXFLR (r) register accessor: I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.</div></li><li><div class="item-name"><a class="type" href="type.IC_TX_ABRT_SOURCE.html" title="type rp2040_pac::i2c0::IC_TX_ABRT_SOURCE">IC_<wbr>TX_<wbr>ABRT_<wbr>SOURCE</a></div><div class="desc docblock-short">IC_TX_ABRT_SOURCE (r) register accessor: I2C Transmit Abort Source Register</div></li><li><div class="item-name"><a class="type" href="type.IC_TX_TL.html" title="type rp2040_pac::i2c0::IC_TX_TL">IC_<wbr>TX_<wbr>TL</a></div><div class="desc docblock-short">IC_TX_TL (rw) register accessor: I2C Transmit FIFO Threshold Register</div></li></ul></section></div></main></body></html>
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