rtic/stable/api/search.desc/imxrt_ral/imxrt_ral-desc-0-.js

searchState.loadedDescShard("imxrt_ral", 0, "This package provides a register access layer (RAL) for …\n67 - ADC1\n67 - ADC1\n79 - ADC_ETC_ERROR_IRQ\n79 - ADC_ETC_ERROR_IRQ\n75 - ADC_ETC_IRQ0\n75 - ADC_ETC_IRQ0\n76 - ADC_ETC_IRQ1\n76 - ADC_ETC_IRQ1\n77 - ADC_ETC_IRQ2\n77 - ADC_ETC_IRQ2\n78 - ADC_ETC_IRQ3\n78 - ADC_ETC_IRQ3\n42 - CCM_1\n42 - CCM_1\n43 - CCM_2\n43 - CCM_2\n49 - CSU\n49 - CSU\n69 - DCDC\n69 - DCDC\n50 - DCP\n50 - DCP\n51 - DCP_VMI\n51 - DCP_VMI\n0 - DMA0\n0 - DMA0\n1 - DMA1\n1 - DMA1\n10 - DMA10\n10 - DMA10\n11 - DMA11\n11 - DMA11\n12 - DMA12\n12 - DMA12\n13 - DMA13\n13 - DMA13\n14 - DMA14\n14 - DMA14\n15 - DMA15\n15 - DMA15\n2 - DMA2\n2 - DMA2\n3 - DMA3\n3 - DMA3\n4 - DMA4\n4 - DMA4\n5 - DMA5\n5 - DMA5\n6 - DMA6\n6 - DMA6\n7 - DMA7\n7 - DMA7\n8 - DMA8\n8 - DMA8\n9 - DMA9\n9 - DMA9\n16 - DMA_ERROR\n16 - DMA_ERROR\n44 - EWM\n44 - EWM\n68 - FLEXIO1\n68 - FLEXIO1\n27 - FLEXRAM\n27 - FLEXRAM\n26 - FLEXSPI\n26 - FLEXSPI\n66 - GPC\n66 - GPC\n70 - GPIO1_COMBINED_0_15\n70 - GPIO1_COMBINED_0_15\n71 - GPIO1_COMBINED_16_31\n71 - GPIO1_COMBINED_16_31\n72 - GPIO2_COMBINED_0_15\n72 - GPIO2_COMBINED_0_15\n73 - GPIO5_COMBINED_0_15\n73 - GPIO5_COMBINED_0_15\n41 - GPR (aka “GPC”) interrupt request\n41 - GPR (aka “GPC”) interrupt request\n30 - GPT1\n30 - GPT1\n31 - GPT2\n31 - GPT2\nAn owned peripheral of type <code>T</code>, instance <code>N</code>.\nInstances for all of this device’s peripherals.\n39 - KPP\n39 - KPP\n28 - LPI2C1\n28 - LPI2C1\n29 - LPI2C2\n29 - LPI2C2\n32 - LPSPI1\n32 - LPSPI1\n33 - LPSPI2\n33 - LPSPI2\n20 - LPUART1\n20 - LPUART1\n21 - LPUART2\n21 - LPUART2\n22 - LPUART3\n22 - LPUART3\n23 - LPUART4\n23 - LPUART4\nNumber available in the NVIC for configuring priority\n24 - PIT\n24 - PIT\n61 - PMU\n61 - PMU\n34 - PWM1_0\n34 - PWM1_0\n35 - PWM1_1\n35 - PWM1_1\n36 - PWM1_2\n36 - PWM1_2\n37 - PWM1_3\n37 - PWM1_3\n38 - PWM1_FAULT\n38 - PWM1_FAULT\nA read-only register of type T.\n57 - RTWDOG\n57 - RTWDOG\nA read-write register of type T.\n56 - SAI1\n56 - SAI1\n58 - SAI3_RX\n58 - SAI3_RX\n59 - SAI3_TX\n59 - SAI3_TX\n46 - SNVS_HP_WRAPPER\n46 - SNVS_HP_WRAPPER\n47 - SNVS_HP_WRAPPER_TZ\n47 - SNVS_HP_WRAPPER_TZ\n48 - SNVS_LP_WRAPPER\n48 - SNVS_LP_WRAPPER\nThe instance number for a peripheral singleton.\n60 - SPDIF\n60 - SPDIF\n40 - SRC\n40 - SRC\n63 - TEMP_LOW_HIGH\n63 - TEMP_LOW_HIGH\n64 - TEMP_PANIC\n64 - TEMP_PANIC\n53 - TRNG\n53 - TRNG\n25 - USB_OTG1\n25 - USB_OTG1\n65 - USB_PHY\n65 - USB_PHY\nVouches for an <code>Instance&lt;T, N&gt;</code>’s validity.\n74 - WDOG1\n74 - WDOG1\n45 - WDOG2\n45 - WDOG2\nA write-only register of type T.\n62 - XBAR1_IRQ_0_1_2_3\n62 - XBAR1_IRQ_0_1_2_3\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire all peripheral instances.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nModify a RWRegister or UnsafeRWRegister.\nCreate an arbitrary <code>Instance</code> from a pointer to <code>T</code>.\nReads the value of the register.\nReads the value of the register.\nRead the value from a RORegister, RWRegister, …\nWrites a new value to the register.\nWrites a new value to the register.\nWrite to a RWRegister or UnsafeRWRegister.\nAnalog-to-Digital Converter\nCalibration value register\nCalibration value register\nConfiguration register\nConfiguration register\nCompare value register\nCompare value register\nGeneral control register\nGeneral control register\nGeneral status register\nGeneral status register\nControl register for hardware triggers\nControl register for hardware triggers\nControl register for hardware triggers\nControl register for hardware triggers\nStatus register for HW triggers\nStatus register for HW triggers\nOffset correction value register\nOffset correction value register\nData result register for HW triggers\nData result register for HW triggers\nData result register for HW triggers\nData result register for HW triggers\nAnalog-to-Digital Converter\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nCalibration Result Value\nHigh Speed Configuration\nInput Clock Select\nClock Divide Select\nLow-Power Configuration\nLong Sample Time Configuration\nDefines the sample time duration\nConversion Trigger Select\nHardware Average select\nConversion Mode Selection\nData Overwrite Enable\nVoltage Reference Selection\nNormal conversion selected.\nHigh speed conversion selected.\nIPG clock\nIPG clock divided by 2\nAlternate clock (ALTCLK)\nAsynchronous clock (ADACK)\nInput clock\nInput clock / 2\nInput clock / 4\nInput clock / 8\nADC hard block not in low power mode.\nADC hard block in low power mode.\nShort sample mode.\nLong sample mode.\nSample period (ADC clocks) = 2 if ADLSMP=0b Sample period …\nSample period (ADC clocks) = 4 if ADLSMP=0b Sample period …\nSample period (ADC clocks) = 6 if ADLSMP=0b Sample period …\nSample period (ADC clocks) = 8 if ADLSMP=0b Sample period …\nSoftware trigger selected\nHardware trigger selected\n4 samples averaged\n8 samples averaged\n16 samples averaged\n32 samples averaged\n8-bit conversion\n10-bit conversion\n12-bit conversion\nDisable the overwriting. Existing Data in Data result …\nEnable the overwriting.\nSelects VREFH/VREFL as reference voltage.\nCompare Value 1\nCompare Value 2\nCompare Function Enable\nCompare Function Greater Than Enable\nCompare Function Range Enable\nAsynchronous clock output enable\nContinuous Conversion Enable\nHardware average enable\nCalibration\nDMA Enable\nCompare function disabled\nCompare function enabled\nConfigures “Less Than Threshold, Outside Range Not …\nConfigures “Greater Than Or Equal To Threshold, Outside …\nRange function disabled. Only the compare value 1 of …\nRange function enabled. Both compare values of ADC_CV …\nAsynchronous clock output disabled; Asynchronous clock …\nAsynchronous clock and clock output enabled regardless of …\nOne conversion or one set of conversions if the hardware …\nContinuous conversions or sets of conversions if the …\nHardware average function disabled\nHardware average function enabled\nDMA disabled (default)\nDMA enabled\nConversion Active\nAsynchronous wakeup interrupt status\nCalibration Failed Flag\nConversion not in progress.\nConversion in progress.\nNo asynchronous interrupt.\nAsynchronous wake up interrupt occurred in stop mode.\nCalibration completed normally.\nCalibration failed. ADC accuracy specifications are not …\nInput Channel Select\nConversion Complete Interrupt Enable/Disable Control\nInput Channel Select\nConversion Complete Interrupt Enable/Disable Control\nExternal channel selection from ADC_ETC\nVREFSH = internal channel, for ADC self-test, hard …\nConversion Disabled. Hardware Triggers will not initiate …\nConversion complete interrupt disabled\nConversion complete interrupt enabled\nExternal channel selection from ADC_ETC\nVREFSH = internal channel, for ADC self-test, hard …\nConversion Disabled. Hardware Triggers will not initiate …\nConversion complete interrupt disabled\nConversion complete interrupt enabled\nConversion Complete Flag\nOffset value\nSign bit\nThe offset value is added with the raw result\nThe offset value is subtracted from the raw converted value\nData (result of an ADC conversion)\nData (result of an ADC conversion)\nADC_ETC\nADC_ETC Global Control Register\nADC_ETC Global Control Register\nETC DMA control Register\nETC DMA control Register\nETC DONE0 and DONE1 IRQ State Register\nETC DONE0 and DONE1 IRQ State Register\nETC DONE_2 and DONE_ERR IRQ State Register\nETC DONE_2 and DONE_ERR IRQ State Register\nADC_ETC\nETC_TRIG Chain 0/1 Register\nETC_TRIG Chain 0/1 Register\nETC_TRIG Chain 2/3 Register\nETC_TRIG Chain 2/3 Register\nETC_TRIG Chain 4/5 Register\nETC_TRIG Chain 4/5 Register\nETC_TRIG Chain 6/7 Register\nETC_TRIG Chain 6/7 Register\nETC_TRIG Counter Register\nETC_TRIG Counter Register\nETC_TRIG Control Register\nETC_TRIG Control Register\nETC_TRIG Result Data 1/0 Register\nETC_TRIG Result Data 1/0 Register\nETC_TRIG Result Data 3/2 Register\nETC_TRIG Result Data 3/2 Register\nETC_TRIG Result Data 5/4 Register\nETC_TRIG Result Data 5/4 Register\nETC_TRIG Result Data 7/6 Register\nETC_TRIG Result Data 7/6 Register\nETC_TRIG Chain 0/1 Register\nETC_TRIG Chain 0/1 Register\nETC_TRIG Chain 2/3 Register\nETC_TRIG Chain 2/3 Register\nETC_TRIG Chain 4/5 Register\nETC_TRIG Chain 4/5 Register\nETC_TRIG Chain 6/7 Register\nETC_TRIG Chain 6/7 Register\nETC_TRIG Counter Register\nETC_TRIG Counter Register\nETC_TRIG Control Register\nETC_TRIG Control Register\nETC_TRIG Result Data 1/0 Register\nETC_TRIG Result Data 1/0 Register\nETC_TRIG Result Data 3/2 Register\nETC_TRIG Result Data 3/2 Register\nETC_TRIG Result Data 5/4 Register\nETC_TRIG Result Data 5/4 Register\nETC_TRIG Result Data 7/6 Register\nETC_TRIG Result Data 7/6 Register\nETC_TRIG Chain 0/1 Register\nETC_TRIG Chain 0/1 Register\nETC_TRIG Chain 2/3 Register\nETC_TRIG Chain 2/3 Register\nETC_TRIG Chain 4/5 Register\nETC_TRIG Chain 4/5 Register\nETC_TRIG Chain 6/7 Register\nETC_TRIG Chain 6/7 Register\nETC_TRIG Counter Register\nETC_TRIG Counter Register\nETC_TRIG Control Register\nETC_TRIG Control Register\nETC_TRIG Result Data 1/0 Register\nETC_TRIG Result Data 1/0 Register\nETC_TRIG Result Data 3/2 Register\nETC_TRIG Result Data 3/2 Register\nETC_TRIG Result Data 5/4 Register\nETC_TRIG Result Data 5/4 Register\nETC_TRIG Result Data 7/6 Register\nETC_TRIG Result Data 7/6 Register\nETC_TRIG Chain 0/1 Register\nETC_TRIG Chain 0/1 Register\nETC_TRIG Chain 2/3 Register\nETC_TRIG Chain 2/3 Register\nETC_TRIG Chain 4/5 Register\nETC_TRIG Chain 4/5 Register\nETC_TRIG Chain 6/7 Register\nETC_TRIG Chain 6/7 Register\nETC_TRIG Counter Register\nETC_TRIG Counter Register\nETC_TRIG Control Register\nETC_TRIG Control Register\nETC_TRIG Result Data 1/0 Register\nETC_TRIG Result Data 1/0 Register\nETC_TRIG Result Data 3/2 Register\nETC_TRIG Result Data 3/2 Register\nETC_TRIG Result Data 5/4 Register\nETC_TRIG Result Data 5/4 Register\nETC_TRIG Result Data 7/6 Register\nETC_TRIG Result Data 7/6 Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\n1’b0: Trig DMA_REQ with latched signal, REQ will be …\nTSC0 TRIG enable register. 1’b1: enable external TSC0 …\nExternal TSC0 trigger priority, 7 is Highest, 0 is lowest .\nTSC1 TRIG enable register. 1’b1: enable external TSC1 …\nExternal TSC1 trigger priority, 7 is Highest, 0 is lowest .\nPre-divider for trig delay and interval .\nSoftware reset, high active. When write 1 ,all logical …\nTRIG enable register\n1’b1: TSC is bypassed to ADC2. 1’b0: TSC not bypassed. …\nWhen TRIG0 done enable DMA request\nWhen TRIG0 done DMA request detection\nWhen TRIG1 done enable DMA request\nWhen TRIG1 done DMA request detection\nWhen TRIG2 done enable DMA request\nWhen TRIG2 done DMA request detection\nWhen TRIG3 done enable DMA request\nWhen TRIG3 done DMA request detection\nWhen TRIG4 done enable DMA request\nWhen TRIG4 done DMA request detection\nWhen TRIG5 done enable DMA request\nWhen TRIG5 done DMA request detection\nWhen TRIG6 done enable DMA request\nWhen TRIG6 done DMA request detection\nWhen TRIG7 done enable DMA request\nWhen TRIG7 done DMA request detection\nTRIG0 done0 interrupt detection\nTRIG0 done1 interrupt detection\nTRIG1 done0 interrupt detection\nTRIG1 done1 interrupt detection\nTRIG2 done0 interrupt detection\nTRIG2 done1 interrupt detection\nTRIG3 done0 interrupt detection\nTRIG3 done1 interrupt detection\nTRIG4 done0 interrupt detection\nTRIG4 done1 interrupt detection\nTRIG5 done0 interrupt detection\nTRIG5 done1 interrupt detection\nTRIG6 done0 interrupt detection\nTRIG6 done1 interrupt detection\nTRIG7 done0 interrupt detection\nTRIG7 done1 interrupt detection\nTRIG0 done2 interrupt detection\nTRIG0 done3 interrupt detection\nTRIG0 error interrupt detection\nTRIG1 done2 interrupt detection\nTRIG1 done3 interrupt detection\nTRIG1 error interrupt detection\nTRIG2 done2 interrupt detection\nTRIG2 done3 interrupt detection\nTRIG2 error interrupt detection\nTRIG3 done2 interrupt detection\nTRIG3 done3 interrupt detection\nTRIG3 error interrupt detection\nTRIG4 done2 interrupt detection\nTRIG4 done3 interrupt detection\nTRIG4 error interrupt detection\nTRIG5 done2 interrupt detection\nTRIG5 done3 interrupt detection\nTRIG5 error interrupt detection\nTRIG6 done2 interrupt detection\nTRIG6 done3 interrupt detection\nTRIG6 error interrupt detection\nTRIG7 done2 interrupt detection\nTRIG7 done3 interrupt detection\nTRIG7 error interrupt detection\nCHAIN0 B2B 1’b0: Disable B2B, wait until interval is …\nCHAIN1 B2B 1’b0: Disable B2B, wait until interval is …\nCHAIN0 CSEL ADC channel selection\nCHAIN1 CSEL ADC channel selection\nCHAIN0 HWTS ADC hardware trigger selection. For more …\nCHAIN1 HWTS ADC hardware trigger selection. For more …\nCHAIN0 IE 2’b00: Finished Interrupt on Done0 2’b01: …\nIRQ enable\nCHAIN1 IE 2’b00: Finished Interrupt on Done0 2’b01: …\nIRQ enable\nCHAIN2 B2B\nCHAIN3 B2B\nCHAIN2 CSEL\nCHAIN3 CSEL\nCHAIN2 HWTS\nCHAIN3 HWTS\nCHAIN2 IE\nIRQ enable\nCHAIN3 IE\nIRQ enable\nCHAIN4 B2B\nCHAIN5 B2B\nCHAIN4 CSEL\nCHAIN5 CSEL\nCHAIN4 HWTS\nCHAIN5 HWTS\nCHAIN4 IE\nIRQ enable\nCHAIN5 IE\nIRQ enable\nCHAIN6 B2B\nCHAIN7 B2B\nCHAIN6 CSEL\nCHAIN7 CSEL\nCHAIN6 HWTS\nCHAIN7 HWTS\nCHAIN6 IE\nIRQ enable\nCHAIN7 IE\nIRQ enable\nTRIGGER initial delay counter\nTRIGGER sampling interval counter\nCHAINx done interrupt detection bit 0: CHAIN0 done …\nSoftware write 1 as the TRIGGER. This register is …\nTRIG mode control . 1’b0: Disable sync mode; 1’b1: …\nTRIG chain length to the ADC. 0: Trig length is 1; … 7: …\nTRIG mode register. 1’b0: hardware trigger. 1’b1: …\nExternal trigger priority, 7 is highest, 0 is lowest .\nResult DATA0\nResult DATA1\nResult DATA2\nResult DATA3\nResult DATA4\nResult DATA5\nResult DATA6\nResult DATA7\nCHAIN0 B2B 1’b0: Disable B2B, wait until interval is …\nCHAIN1 B2B 1’b0: Disable B2B, wait until interval is …\nCHAIN0 CSEL ADC channel selection\nCHAIN1 CSEL ADC channel selection\nCHAIN0 HWTS ADC hardware trigger selection. For more …\nCHAIN1 HWTS ADC hardware trigger selection. For more …\nCHAIN0 IE 2’b00: Finished Interrupt on Done0 2’b01: …\nIRQ enable\nCHAIN1 IE 2’b00: Finished Interrupt on Done0 2’b01: …\nIRQ enable\nCHAIN2 B2B\nCHAIN3 B2B\nCHAIN2 CSEL\nCHAIN3 CSEL\nCHAIN2 HWTS\nCHAIN3 HWTS\nCHAIN2 IE\nIRQ enable\nCHAIN3 IE\nIRQ enable\nCHAIN4 B2B\nCHAIN5 B2B\nCHAIN4 CSEL\nCHAIN5 CSEL\nCHAIN4 HWTS\nCHAIN5 HWTS\nCHAIN4 IE\nIRQ enable\nCHAIN5 IE\nIRQ enable\nCHAIN6 B2B\nCHAIN7 B2B\nCHAIN6 CSEL\nCHAIN7 CSEL\nCHAIN6 HWTS\nCHAIN7 HWTS\nCHAIN6 IE\nIRQ enable\nCHAIN7 IE\nIRQ enable\nTRIGGER initial delay counter\nTRIGGER sampling interval counter\nCHAINx done interrupt detection bit 0: CHAIN0 done …\nSoftware write 1 as the TRIGGER. This register is …\nTRIG mode control . 1’b0: Disable sync mode; 1’b1: …\nTRIG chain length to the ADC. 0: Trig length is 1; … 7: …\nTRIG mode register. 1’b0: hardware trigger. 1’b1: …\nExternal trigger priority, 7 is highest, 0 is lowest .\nResult DATA0\nResult DATA1\nResult DATA2\nResult DATA3\nResult DATA4\nResult DATA5\nResult DATA6\nResult DATA7\nCHAIN0 B2B 1’b0: Disable B2B, wait until interval is …\nCHAIN1 B2B 1’b0: Disable B2B, wait until interval is …\nCHAIN0 CSEL ADC channel selection\nCHAIN1 CSEL ADC channel selection\nCHAIN0 HWTS ADC hardware trigger selection. For more …\nCHAIN1 HWTS ADC hardware trigger selection. For more …\nCHAIN0 IE 2’b00: Finished Interrupt on Done0 2’b01: …\nIRQ enable\nCHAIN1 IE 2’b00: Finished Interrupt on Done0 2’b01: …\nIRQ enable\nCHAIN2 B2B\nCHAIN3 B2B\nCHAIN2 CSEL\nCHAIN3 CSEL\nCHAIN2 HWTS\nCHAIN3 HWTS\nCHAIN2 IE\nIRQ enable\nCHAIN3 IE\nIRQ enable\nCHAIN4 B2B\nCHAIN5 B2B\nCHAIN4 CSEL\nCHAIN5 CSEL\nCHAIN4 HWTS\nCHAIN5 HWTS\nCHAIN4 IE\nIRQ enable\nCHAIN5 IE\nIRQ enable\nCHAIN6 B2B\nCHAIN7 B2B\nCHAIN6 CSEL\nCHAIN7 CSEL\nCHAIN6 HWTS\nCHAIN7 HWTS\nCHAIN6 IE\nIRQ enable\nCHAIN7 IE\nIRQ enable\nTRIGGER initial delay counter\nTRIGGER sampling interval counter\nCHAINx done interrupt detection bit 0: CHAIN0 done …\nSoftware write 1 as the TRIGGER. This register is …\nTRIG mode control . 1’b0: Disable sync mode; 1’b1: …\nTRIG chain length to the ADC. 0: Trig length is 1; … 7: …\nTRIG mode register. 1’b0: hardware trigger. 1’b1: …\nExternal trigger priority, 7 is highest, 0 is lowest .\nResult DATA0\nResult DATA1\nResult DATA2\nResult DATA3\nResult DATA4\nResult DATA5\nResult DATA6\nResult DATA7\nCHAIN0 B2B 1’b0: Disable B2B, wait until interval is …\nCHAIN1 B2B 1’b0: Disable B2B, wait until interval is …\nCHAIN0 CSEL ADC channel selection\nCHAIN1 CSEL ADC channel selection\nCHAIN0 HWTS ADC hardware trigger selection. For more …\nCHAIN1 HWTS ADC hardware trigger selection. For more …\nCHAIN0 IE 2’b00: Finished Interrupt on Done0 2’b01: …\nIRQ enable\nCHAIN1 IE 2’b00: Finished Interrupt on Done0 2’b01: …\nIRQ enable\nCHAIN2 B2B\nCHAIN3 B2B\nCHAIN2 CSEL\nCHAIN3 CSEL\nCHAIN2 HWTS\nCHAIN3 HWTS\nCHAIN2 IE\nIRQ enable\nCHAIN3 IE\nIRQ enable\nCHAIN4 B2B\nCHAIN5 B2B\nCHAIN4 CSEL\nCHAIN5 CSEL\nCHAIN4 HWTS\nCHAIN5 HWTS\nCHAIN4 IE\nIRQ enable\nCHAIN5 IE\nIRQ enable\nCHAIN6 B2B\nCHAIN7 B2B\nCHAIN6 CSEL\nCHAIN7 CSEL\nCHAIN6 HWTS\nCHAIN7 HWTS\nCHAIN6 IE\nIRQ enable\nCHAIN7 IE\nIRQ enable\nTRIGGER initial delay counter\nTRIGGER sampling interval counter\nCHAINx done interrupt detection bit 0: CHAIN0 done …\nSoftware write 1 as the TRIGGER. This register is …\nTRIG mode control . 1’b0: Disable sync mode; 1’b1: …\nTRIG chain length to the ADC. 0: Trig length is 1; … 7: …\nTRIG mode register. 1’b0: hardware trigger. 1’b1: …\nExternal trigger priority, 7 is highest, 0 is lowest .\nResult DATA0\nResult DATA1\nResult DATA2\nResult DATA3\nResult DATA4\nResult DATA5\nResult DATA6\nResult DATA7\nAIPSTZ Control Registers\nAIPSTZ Control Registers\nMaster Priviledge Registers\nMaster Priviledge Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nOff-Platform Peripheral Access Control Registers\nAIPSTZ Control Registers\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nMaster 0 Priviledge, Buffer, Read, Write Control\nMaster 1 Priviledge, Buffer, Read, Write Control\nMaster 2 Priviledge, Buffer, Read, Write Control\nMaster 3 Priviledge, Buffer, Read, Write Control.\nMaster 5 Priviledge, Buffer, Read, Write Control.\nAccesses from this master are forced to user-mode …\nAccesses from this master are not forced to user-mode. The …\nAccesses from this master are forced to user-mode …\nAccesses from this master are not forced to user-mode. The …\nAccesses from this master are forced to user-mode …\nAccesses from this master are not forced to user-mode. The …\nAccesses from this master are forced to user-mode …\nAccesses from this master are not forced to user-mode. The …\nAccesses from this master are forced to user-mode …\nAccesses from this master are not forced to user-mode. The …\nOff-platform Peripheral Access Control 0\nOff-platform Peripheral Access Control 1\nOff-platform Peripheral Access Control 2\nOff-platform Peripheral Access Control 3\nOff-platform Peripheral Access Control 4\nOff-platform Peripheral Access Control 5\nOff-platform Peripheral Access Control 6\nOff-platform Peripheral Access Control 7\nOff-platform Peripheral Access Control 10\nOff-platform Peripheral Access Control 11\nOff-platform Peripheral Access Control 12\nOff-platform Peripheral Access Control 13\nOff-platform Peripheral Access Control 14\nOff-platform Peripheral Access Control 15\nOff-platform Peripheral Access Control 8\nOff-platform Peripheral Access Control 9\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nOff-platform Peripheral Access Control 16\nOff-platform Peripheral Access Control 17\nOff-platform Peripheral Access Control 18\nOff-platform Peripheral Access Control 19\nOff-platform Peripheral Access Control 20\nOff-platform Peripheral Access Control 21\nOff-platform Peripheral Access Control 22\nOff-platform Peripheral Access Control 23\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nOff-platform Peripheral Access Control 24\nOff-platform Peripheral Access Control 25\nOff-platform Peripheral Access Control 26\nOff-platform Peripheral Access Control 27\nOff-platform Peripheral Access Control 28\nOff-platform Peripheral Access Control 29\nOff-platform Peripheral Access Control 30\nOff-platform Peripheral Access Control 31\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nOff-platform Peripheral Access Control 32\nOff-platform Peripheral Access Control 33\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAccesses from an untrusted master are allowed.\nAccesses from an untrusted master are not allowed. If an …\nAND/OR/INVERT module\nBoolean Function Term 0 and 1 Configuration Register for …\nBoolean Function Term 0 and 1 Configuration Register for …\nBoolean Function Term 0 and 1 Configuration Register for …\nBoolean Function Term 0 and 1 Configuration Register for …\nBoolean Function Term 0 and 1 Configuration Register for …\nBoolean Function Term 0 and 1 Configuration Register for …\nBoolean Function Term 0 and 1 Configuration Register for …\nBoolean Function Term 0 and 1 Configuration Register for …\nBoolean Function Term 2 and 3 Configuration Register for …\nBoolean Function Term 2 and 3 Configuration Register for …\nBoolean Function Term 2 and 3 Configuration Register for …\nBoolean Function Term 2 and 3 Configuration Register for …\nBoolean Function Term 2 and 3 Configuration Register for …\nBoolean Function Term 2 and 3 Configuration Register for …\nBoolean Function Term 2 and 3 Configuration Register for …\nBoolean Function Term 2 and 3 Configuration Register for …\nAND/OR/INVERT module\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nProduct term 0, A input configuration\nProduct term 0, B input configuration\nProduct term 0, C input configuration\nProduct term 0, D input configuration\nProduct term 1, A input configuration\nProduct term 1, B input configuration\nProduct term 1, C input configuration\nProduct term 1, D input configuration\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nProduct term 0, A input configuration\nProduct term 0, B input configuration\nProduct term 0, C input configuration\nProduct term 0, D input configuration\nProduct term 1, A input configuration\nProduct term 1, B input configuration\nProduct term 1, C input configuration\nProduct term 1, D input configuration\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nProduct term 0, A input configuration\nProduct term 0, B input configuration\nProduct term 0, C input configuration\nProduct term 0, D input configuration\nProduct term 1, A input configuration\nProduct term 1, B input configuration\nProduct term 1, C input configuration\nProduct term 1, D input configuration\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nProduct term 0, A input configuration\nProduct term 0, B input configuration\nProduct term 0, C input configuration\nProduct term 0, D input configuration\nProduct term 1, A input configuration\nProduct term 1, B input configuration\nProduct term 1, C input configuration\nProduct term 1, D input configuration\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nProduct term 2, A input configuration\nProduct term 2, B input configuration\nProduct term 2, C input configuration\nProduct term 2, D input configuration\nProduct term 3, A input configuration\nProduct term 3, B input configuration\nProduct term 3, C input configuration\nProduct term 3, D input configuration\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nProduct term 2, A input configuration\nProduct term 2, B input configuration\nProduct term 2, C input configuration\nProduct term 2, D input configuration\nProduct term 3, A input configuration\nProduct term 3, B input configuration\nProduct term 3, C input configuration\nProduct term 3, D input configuration\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nProduct term 2, A input configuration\nProduct term 2, B input configuration\nProduct term 2, C input configuration\nProduct term 2, D input configuration\nProduct term 3, A input configuration\nProduct term 3, B input configuration\nProduct term 3, C input configuration\nProduct term 3, D input configuration\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nProduct term 2, A input configuration\nProduct term 2, B input configuration\nProduct term 2, C input configuration\nProduct term 2, D input configuration\nProduct term 3, A input configuration\nProduct term 3, B input configuration\nProduct term 3, C input configuration\nProduct term 3, D input configuration\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nForce the A input in this product term to a logical zero\nPass the A input in this product term\nComplement the A input in this product term\nForce the A input in this product term to a logical one\nForce the B input in this product term to a logical zero\nPass the B input in this product term\nComplement the B input in this product term\nForce the B input in this product term to a logical one\nForce the C input in this product term to a logical zero\nPass the C input in this product term\nComplement the C input in this product term\nForce the C input in this product term to a logical one\nForce the D input in this product term to a logical zero\nPass the D input in this product term\nComplement the D input in this product term\nForce the D input in this product term to a logical one\nCCM Bus Clock Divider Register\nCCM Bus Clock Divider Register\nCCM Bus Clock Multiplexer Register\nCCM Bus Clock Multiplexer Register\nCCM Clock Gating Register 0\nCCM Clock Gating Register 0\nCCM Clock Gating Register 1\nCCM Clock Gating Register 1\nCCM Clock Gating Register 2\nCCM Clock Gating Register 2\nCCM Clock Gating Register 3\nCCM Clock Gating Register 3\nCCM Clock Gating Register 4\nCCM Clock Gating Register 4\nCCM Clock Gating Register 5\nCCM Clock Gating Register 5\nCCM Clock Gating Register 6\nCCM Clock Gating Register 6\nCCM\nCCM Clock Output Source Register\nCCM Clock Output Source Register\nCCM Control Register\nCCM Control Register\nCCM Clock Switcher Register\nCCM Clock Switcher Register\nCCM D1 Clock Divider Register\nCCM D1 Clock Divider Register\nCCM Divider Handshake In-Process Register\nCCM Divider Handshake In-Process Register\nCCM General Purpose Register\nCCM General Purpose Register\nCCM Interrupt Mask Register\nCCM Interrupt Mask Register\nCCM Interrupt Status Register\nCCM Interrupt Status Register\nCCM Low Power Control Register\nCCM Low Power Control Register\nCCM Module Enable Overide Register\nCCM Module Enable Overide Register\nCCM Clock Divider Register\nCCM Clock Divider Register\nCCM Serial Clock Divider Register 1\nCCM Serial Clock Divider Register 1\nCCM Serial Clock Divider Register 2\nCCM Serial Clock Divider Register 2\nCCM Serial Clock Multiplexer Register 1\nCCM Serial Clock Multiplexer Register 1\nCCM Serial Clock Multiplexer Register 2\nCCM Serial Clock Multiplexer Register 2\nCCM Status Register\nCCM Status Register\nCCM\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDivider for AHB PODF\nDivider for ipg podf.\nSelector for peripheral main clock\ndivide by 1\ndivide by 2\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\ndivide by 1\ndivide by 2\ndivide by 3\ndivide by 4\nderive clock selected by CCM_CBCMR[CORE_CLK_PRE_SEL]\nderive clock selected by CCM_CBCMR[PERIPH_CLK2_SEL]\nSelector for lpspi clock multiplexer\nDivider for LPSPI. Divider should be updated when output …\nSelector for peripheral clk2 clock multiplexer\nSelector for pre_periph clock multiplexer\nSelector for Trace clock multiplexer\nderive clock from PLL3 PFD1 clk\nderive clock from PLL3 PFD0\nderive clock from PLL2\nderive clock from PLL2 PFD2\ndivide by 1\ndivide by 2\ndivide by 11\ndivide by 12\ndivide by 13\ndivide by 14\ndivide by 15\ndivide by 16\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\ndivide by 9\ndivide by 10\nderive clock from pll3_sw_clk\nderive clock from osc_clk\nderive clock from pll2_bypass_clk\nderive clock from PLL2\nderive clock from PLL3 PFD3\nderive clock from PLL2 PFD3\nderive clock from PLL6\nderive clock from PLL2\nderive clock from PLL2 PFD2\nderive clock from PLL2 PFD0\nderive clock from PLL2 PFD1\naips_tz1 clocks (aips_tz1_clk_enable)\naips_tz2 clocks (aips_tz2_clk_enable)\nReserved\ntrace clock (trace_clk_enable)\ngpt2 bus clocks (gpt2_bus_clk_enable)\ngpt2 serial clocks (gpt2_serial_clk_enable)\nlpuart2 clock (lpuart2_clk_enable)\ngpio2_clocks (gpio2_clk_enable)\nmqs clock ( mqs_hmclk_clock_enable)\nflexspi_exsc clock (flexspi_exsc_clk_enable)\nsim_m_clk_r_clk_enable\ndcp clock (dcp_clk_enable)\nlpuart3 clock (lpuart3_clk_enable)\nReserved\nReserved\nReserved\nlpspi1 clocks (lpspi1_clk_enable)\nlpspi2 clocks (lpspi2_clk_enable)\ngpt1 bus clock (gpt_clk_enable)\ngpt1 serial clock (gpt_serial_clk_enable)\nlpuart4 clock (lpuart4_clk_enable)\ngpio1 clock (gpio1_clk_enable)\ncsu clock (csu_clk_enable)\ngpio5 clock (gpio5_clk_enable)\nReserved\nReserved\nReserved\nReserved\npit clocks (pit_clk_enable)\nReserved\nadc1 clock (adc1_clk_enable)\nReserved\nocram_exsc clock (ocram_exsc_clk_enable)\nReserved\nReserved\nxbar1 clock (xbar1_clk_enable)\nReserved\nReserved\nReserved\nReserved\niomuxc_snvs clock (iomuxc_snvs_clk_enable)\nlpi2c1 clock (lpi2c1_clk_enable)\nlpi2c2 clock (lpi2c2_clk_enable)\nReserved\nOCOTP_CTRL clock (iim_clk_enable)\nReserved\nReserved\nReserved\nReserved\nReserved\nReserved\nReserved\nReserved\nReserved\nThe OCRAM clock cannot be turned off when the CM cache is …\niomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable)\nReserved\nReserved\naoi1 clock (aoi1_clk_enable)\nReserved\nReserved\newm clocks (ewm_clk_enable)\nwdog1 clock (wdog1_clk_enable)\nflexram clock (flexram_clk_enable)\nsim_m7_clk_r_enable\niomuxc clock (iomuxc_clk_enable)\nReserved\nReserved\nReserved\nReserved\nReserved\ndma_ps clocks (dma_ps_clk_enable)\niomuxc gpr clock (iomuxc_gpr_clk_enable)\nReserved\nsim_m7 clock (sim_m7_clk_enable)\nReserved\nsim_m clocks (sim_m_clk_enable)\nsim_ems clocks (sim_ems_clk_enable)\npwm1 clocks (pwm1_clk_enable)\nReserved\nrom clock (rom_clk_enable)\nflexio1 clock (flexio1_clk_enable)\nReserved\nsai3 clock (sai3_clk_enable)\nlpuart1 clock (lpuart1_clk_enable)\nReserved\nsnvs_hp clock (snvs_hp_clk_enable)\nsnvs_lp clock (snvs_lp_clk_enable)\nwdog3 clock (wdog3_clk_enable)\ndma clock (dma_clk_enable)\nkpp clock (kpp_clk_enable)\nwdog2 clock (wdog2_clk_enable)\nReserved\nspdif clock (spdif_clk_enable)\nReserved\nsai1 clock (sai1_clk_enable)\nusboh3 clock (usboh3_clk_enable)\nReserved\nsim_per clock (sim_per_clk_enable)\nanadig clocks (anadig_clk_enable)\nReserved\nReserved\nReserved\nReserved\nReserved\ndcdc clocks (dcdc_clk_enable)\nReserved\nflexspi clocks (flexspi_clk_enable) sim_ems_clk_enable …\ntrng clock (trng_clk_enable)\nReserved\nReserved\nReserved\nSetting the divider of CCM_CLKO1\nEnable of CCM_CLKO1 clock\nSelection of the clock to be generated on CCM_CLKO1\nSetting the divider of CCM_CLKO2\nEnable of CCM_CLKO2 clock\nSelection of the clock to be generated on CCM_CLKO2\nCCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks\ndivide by 1\ndivide by 2\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\nCCM_CLKO1 disabled.\nCCM_CLKO1 enabled.\npll3_sw_clk (divided by 2)\nPLL2 (divided by 2)\ncore_clk_root\nipg_clk_root\nperclk_root\npll4_main_clk\nENET PLL (divided by 2)\ndivide by 1\ndivide by 2\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\nCCM_CLKO2 disabled.\nCCM_CLKO2 enabled.\nosc_clk\nlpspi_clk_root\nsai1_clk_root\nsai3_clk_root\ntrace_clk_root\nflexspi_clk_root\nuart_clk_root\nspdif0_clk_root\nlpi2c_clk_root\nCCM_CLKO1 output drives CCM_CLKO1 clock\nCCM_CLKO1 output drives CCM_CLKO2 clock\nOn chip oscillator enable bit - this bit value is …\nOscillator ready counter value. These bits define value of …\nEnable for REG_BYPASS_COUNTER\nCounter for analog_reg_bypass signal assertion after …\ndisable on chip oscillator\nenable on chip oscillator\nREG_BYPASS_COUNTER disabled\nREG_BYPASS_COUNTER enabled.\nno delay\n1 CKIL clock period delay\n63 CKIL clock periods delay\nSelects source to generate pll3_sw_clk. This bit should …\npll3_main_clk\npll3 bypass clock\nDivider for spdif0 clock podf. Divider should be updated …\nDivider for spdif0 clock pred. Divider should be updated …\nSelector for spdif0 clock multiplexer\nDivide by 1\nDivide by 2\nDivide by 3\nDivide by 4\nDivide by 5\nDivide by 6\nDivide by 7\nDivide by 8\nDivide by 1\nDivide by 2\nDivide by 3\nDivide by 4\nDivide by 5\nDivide by 6\nDivide by 7\nDivide by 8\nderive clock from PLL4\nderive clock from PLL3 PFD2\nderive clock from pll3_sw_clk\nBusy indicator for ahb_podf.\nBusy indicator for flexspi_podf.\nBusy indicator for perclk_podf.\nBusy indicator for periph_clk_sel mux control.\ndivider is not busy and its value represents the actual …\ndivider is busy with handshake process with module. The …\ndivider is not busy and its value represents the actual …\ndivider is busy with handshake process with module. The …\ndivider is not busy and its value represents the actual …\ndivider is busy with handshake process with module. The …\nmux is not busy and its value represents the actual …\nmux is busy with handshake process with module. The value …\nDefines the value of the output signal cgpr_dout[4]. Gate …\nFast PLL enable.\nControl for the Deep Sleep signal to the ARM Platform …\nDefines clock dividion of clock for stby_count (pmic delay …\nSystem memory DS control\nfuse programing supply voltage is gated off to the efuse …\nallow fuse programing.\nEngage PLL enable default way.\nEngage PLL enable 3 CKIL clocks earlier at exiting low …\nDisable the clock to the ARM platform memories when …\nKeep the clocks to the ARM platform memories enabled only …\nclock is not divided\nclock is divided /8\nDisable memory DS mode always\nEnable memory (outside ARM platform) DS mode when system …\nenable memory (outside ARM platform) DS mode when system …\nmask interrupt generation due to frequency change of …\nmask interrupt generation due to on board oscillator ready\nmask interrupt generation due to update of flexspi_podf\nmask interrupt generation due to lrf of PLLs\nmask interrupt generation due to update of perclk_podf\nmask interrupt generation due to update of periph_clk_sel.\ndon’t mask interrupt due to frequency change of ahb_podf …\nmask interrupt due to frequency change of ahb_podf\ndon’t mask interrupt due to on board oscillator ready - …\nmask interrupt due to on board oscillator ready\ndon’t mask interrupt due to update of flexspi_podf\nmask interrupt due to update of flexspi_podf\ndon’t mask interrupt due to lrf of PLLs - interrupt will …\nmask interrupt due to lrf of PLLs\ndon’t mask interrupt due to update of perclk_podf\nmask interrupt due to update of perclk_podf\ndon’t mask interrupt due to update of periph_clk_sel - …\nmask interrupt due to update of periph_clk_sel\nCCM interrupt request 1 generated due to frequency change …\nCCM interrupt request 2 generated due to on board …\nCCM interrupt request 1 generated due to frequency change …\nCCM interrupt request 2 generated due to lock of all …\nCCM interrupt request 1 generated due to frequency change …\nCCM interrupt request 1 generated due to update of …\ninterrupt is not generated due to frequency change of …\ninterrupt generated due to frequency change of ahb_podf\ninterrupt is not generated due to on board oscillator ready\ninterrupt generated due to on board oscillator ready\ninterrupt is not generated due to frequency change of …\ninterrupt generated due to frequency change of flexspi_podf\ninterrupt is not generated due to lock ready of all …\ninterrupt generated due to lock ready of all enabled and …\ninterrupt is not generated due to frequency change of …\ninterrupt generated due to frequency change of perclk_podf\ninterrupt is not generated due to update of periph_clk_sel.\ninterrupt generated due to update of periph_clk_sel.\nDefine if ARM clocks (arm_clk, soc_mxclk, soc_pclk, …\nIn run mode, software can manually control powering down …\ndis_ref_osc - in run mode, software can manually control …\nSetting the low power mode that system will enter on next …\nMask WFI of core0 for entering low power mode Assertion of …\nMask L2CC IDLE for entering low power mode\nMask SCU IDLE for entering low power mode Assertion of all …\nStandby clock oscillator bit\nStandby counter definition\nVoltage standby request bit\nARM clock enabled on wait mode.\nARM clock disabled on wait mode. .\nOn chip oscillator will not be powered down, i.e. …\nOn chip oscillator will be powered down, i.e. cosc_pwrdown …\nexternal high frequency oscillator will be enabled, i.e. …\nexternal high frequency oscillator will be disabled, i.e. …\nRemain in run mode\nTransfer to wait mode\nTransfer to stop mode\nWFI of core0 is not masked\nWFI of core0 is masked\nL2CC IDLE is not masked\nL2CC IDLE is masked\nSCU IDLE is not masked\nSCU IDLE is masked\nOn-chip oscillator will not be powered down, after next …\nOn-chip oscillator will be powered down, after next …\nCCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles\nCCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles\nCCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles\nCCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles\nVoltage will not be changed to standby voltage after next …\nVoltage will be requested to change to standby voltage …\nOveride clock enable signal from GPT - clock will not be …\nOveride clock enable signal from PIT - clock will not be …\nOveride clock enable signal from TRNG\ndon’t override module enable signal\noverride module enable signal\ndon’t override module enable signal\noverride module enable signal\ndon’t override module enable signal\noverride module enable signal\nDivider for flexio1 clock. Divider should be updated when …\nDivider for flexio1 clock.\nDivider for sai1 clock podf. The input clock to this …\nDivider for sai1 clock pred.\nDivider for sai3 clock podf. The input clock to this …\nDivider for sai3 clock pred.\nDivide by 1\nDivide by 10\nDivide by 11\nDivide by 12\nDivide by 13\nDivide by 14\nDivide by 15\nDivide by 16\nDivide by 2\nDivide by 3\nDivide by 4\nDivide by 5\nDivide by 6\nDivide by 7\nDivide by 8\nDivide by 9\ndivide by 1\ndivide by 2\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\nDivide by 1\nDivide by 10\nDivide by 11\nDivide by 12\nDivide by 13\nDivide by 14\nDivide by 15\nDivide by 16\nDivide by 17\nDivide by 18\nDivide by 19\nDivide by 2\nDivide by 20\nDivide by 21\nDivide by 22\nDivide by 23\nDivide by 24\nDivide by 25\nDivide by 26\nDivide by 27\nDivide by 28\nDivide by 29\nDivide by 3\nDivide by 30\nDivide by 31\nDivide by 32\nDivide by 33\nDivide by 34\nDivide by 35\nDivide by 36\nDivide by 37\nDivide by 38\nDivide by 39\nDivide by 4\nDivide by 40\nDivide by 41\nDivide by 42\nDivide by 43\nDivide by 44\nDivide by 45\nDivide by 46\nDivide by 47\nDivide by 48\nDivide by 49\nDivide by 5\nDivide by 50\nDivide by 51\nDivide by 52\nDivide by 53\nDivide by 54\nDivide by 55\nDivide by 56\nDivide by 57\nDivide by 58\nDivide by 59\nDivide by 6\nDivide by 60\nDivide by 61\nDivide by 62\nDivide by 63\nDivide by 64\nDivide by 7\nDivide by 8\nDivide by 9\ndivide by 1\ndivide by 2\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\nDivide by 1\nDivide by 10\nDivide by 11\nDivide by 12\nDivide by 13\nDivide by 14\nDivide by 15\nDivide by 16\nDivide by 17\nDivide by 18\nDivide by 19\nDivide by 2\nDivide by 20\nDivide by 21\nDivide by 22\nDivide by 23\nDivide by 24\nDivide by 25\nDivide by 26\nDivide by 27\nDivide by 28\nDivide by 29\nDivide by 3\nDivide by 30\nDivide by 31\nDivide by 32\nDivide by 33\nDivide by 34\nDivide by 35\nDivide by 36\nDivide by 37\nDivide by 38\nDivide by 39\nDivide by 4\nDivide by 40\nDivide by 41\nDivide by 42\nDivide by 43\nDivide by 44\nDivide by 45\nDivide by 46\nDivide by 47\nDivide by 48\nDivide by 49\nDivide by 5\nDivide by 50\nDivide by 51\nDivide by 52\nDivide by 53\nDivide by 54\nDivide by 55\nDivide by 56\nDivide by 57\nDivide by 58\nDivide by 59\nDivide by 6\nDivide by 60\nDivide by 61\nDivide by 62\nDivide by 63\nDivide by 64\nDivide by 7\nDivide by 8\nDivide by 9\ndivide by 1\ndivide by 2\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\nDivider for trace clock. Divider should be updated when …\nDivider for uart clock podf.\nSelector for the UART clock multiplexor\ndivide by 1\ndivide by 2\ndivide by 11\ndivide by 12\ndivide by 13\ndivide by 14\ndivide by 15\ndivide by 16\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\ndivide by 9\ndivide by 10\nDivide by 1\nDivide by 10\nDivide by 11\nDivide by 12\nDivide by 13\nDivide by 14\nDivide by 15\nDivide by 16\nDivide by 17\nDivide by 18\nDivide by 19\nDivide by 2\nDivide by 20\nDivide by 21\nDivide by 22\nDivide by 23\nDivide by 24\nDivide by 25\nDivide by 26\nDivide by 27\nDivide by 28\nDivide by 29\nDivide by 3\nDivide by 30\nDivide by 31\nDivide by 32\nDivide by 33\nDivide by 34\nDivide by 35\nDivide by 36\nDivide by 37\nDivide by 38\nDivide by 39\nDivide by 4\nDivide by 40\nDivide by 41\nDivide by 42\nDivide by 43\nDivide by 44\nDivide by 45\nDivide by 46\nDivide by 47\nDivide by 48\nDivide by 49\nDivide by 5\nDivide by 50\nDivide by 51\nDivide by 52\nDivide by 53\nDivide by 54\nDivide by 55\nDivide by 56\nDivide by 57\nDivide by 58\nDivide by 59\nDivide by 6\nDivide by 60\nDivide by 61\nDivide by 62\nDivide by 63\nDivide by 64\nDivide by 7\nDivide by 8\nDivide by 9\nderive clock from pll3_80m\nderive clock from osc_clk\nderive clock from per_clk_root\nDivider for lpi2c clock podf. Divider should be updated …\nSelector for the LPI2C clock multiplexor\nDivide by 1\nDivide by 10\nDivide by 11\nDivide by 12\nDivide by 13\nDivide by 14\nDivide by 15\nDivide by 16\nDivide by 17\nDivide by 18\nDivide by 19\nDivide by 2\nDivide by 20\nDivide by 21\nDivide by 22\nDivide by 23\nDivide by 24\nDivide by 25\nDivide by 26\nDivide by 27\nDivide by 28\nDivide by 29\nDivide by 3\nDivide by 30\nDivide by 31\nDivide by 32\nDivide by 33\nDivide by 34\nDivide by 35\nDivide by 36\nDivide by 37\nDivide by 38\nDivide by 39\nDivide by 4\nDivide by 40\nDivide by 41\nDivide by 42\nDivide by 43\nDivide by 44\nDivide by 45\nDivide by 46\nDivide by 47\nDivide by 48\nDivide by 49\nDivide by 5\nDivide by 50\nDivide by 51\nDivide by 52\nDivide by 53\nDivide by 54\nDivide by 55\nDivide by 56\nDivide by 57\nDivide by 58\nDivide by 59\nDivide by 6\nDivide by 60\nDivide by 61\nDivide by 62\nDivide by 63\nDivide by 64\nDivide by 7\nDivide by 8\nDivide by 9\nderive clock from pll3_60m\nderive clock from osc_clk\nSelector for flexspi clock multiplexer\nSelect for source of flexspi_clk_root\nDivider for flexspi clock root.\nSelector for the perclk clock multiplexor\nDivider for perclk podf.\nSelector for sai1 clock multiplexer\nSelector for sai3 clock multiplexer\nderive clock from PLL2\nderive clock from pll3_sw_clk\nderive clock from PLL2 PFD2\nderive clock from PLL3 PFD0\nderive clock selected by CCM_CSCMR1[FLEXSPI_CLK_SEL]\nderive clock selected by CCM_CBCMR[PERIPH_CLK2_ SEL]\ndivide by 1\ndivide by 2\ndivide by 3\ndivide by 4\ndivide by 5\ndivide by 6\ndivide by 7\ndivide by 8\nderive clock from ipg clk root\nderive clock from osc_clk\nDivide by 1\nDivide by 10\nDivide by 11\nDivide by 12\nDivide by 13\nDivide by 14\nDivide by 15\nDivide by 16\nDivide by 17\nDivide by 18\nDivide by 19\nDivide by 2\nDivide by 20\nDivide by 21\nDivide by 22\nDivide by 23\nDivide by 24\nDivide by 25\nDivide by 26\nDivide by 27\nDivide by 28\nDivide by 29\nDivide by 3\nDivide by 30\nDivide by 31\nDivide by 32\nDivide by 33\nDivide by 34\nDivide by 35\nDivide by 36\nDivide by 37\nDivide by 38\nDivide by 39\nDivide by 4\nDivide by 40\nDivide by 41\nDivide by 42\nDivide by 43\nDivide by 44\nDivide by 45\nDivide by 46\nDivide by 47\nDivide by 48\nDivide by 49\nDivide by 5\nDivide by 50\nDivide by 51\nDivide by 52\nDivide by 53\nDivide by 54\nDivide by 55\nDivide by 56\nDivide by 57\nDivide by 58\nDivide by 59\nDivide by 6\nDivide by 60\nDivide by 61\nDivide by 62\nDivide by 63\nDivide by 64\nDivide by 7\nDivide by 8\nDivide by 9\nderive clock from PLL3 PFD2\nderive from pll3_sw_clk\nderive clock from PLL4\nderive clock from PLL3 PFD2\nderive from pll3_sw_clk\nderive clock from PLL4\nEnable ADC alt_clk, so that ADC alt_clk can be driven be …\nDivider for ADC alt_clk, as the list below (other values …\nSelector for flexio1 clock multiplexer\nADC alt_clk source is disabled\nADC alt_clk source is enabled\npll3_sw_clk / 12\npll3_sw_clk / 16\npll3_sw_clk / 8\nderive clock from PLL4 divided clock\nderive clock from PLL3 PFD2 clock\nderive from PLL2\nderive clock from pll3_sw_clk\nStatus indication of CAMP2.\nStatus indication of on board oscillator\nStatus of the value of CCM_REF_EN_B output of ccm\nCAMP2 is not ready.\nCAMP2 is ready.\non board oscillator is not ready.\non board oscillator is ready.\nvalue of CCM_REF_EN_B is ‘0’\nvalue of CCM_REF_EN_B is ‘1’\nCCM_ANALOG\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 2\nMiscellaneous Register 2\nMiscellaneous Register 2\nMiscellaneous Register 2\nMiscellaneous Register 2\nMiscellaneous Register 2\nMiscellaneous Register 2\nMiscellaneous Register 2\n480MHz Clock (PLL3) Phase Fractional Divider Control …\n480MHz Clock (PLL3) Phase Fractional Divider Control …\n480MHz Clock (PLL3) Phase Fractional Divider Control …\n480MHz Clock (PLL3) Phase Fractional Divider Control …\n480MHz Clock (PLL3) Phase Fractional Divider Control …\n480MHz Clock (PLL3) Phase Fractional Divider Control …\n480MHz Clock (PLL3) Phase Fractional Divider Control …\n480MHz Clock (PLL3) Phase Fractional Divider Control …\n528MHz Clock (PLL2) Phase Fractional Divider Control …\n528MHz Clock (PLL2) Phase Fractional Divider Control …\n528MHz Clock (PLL2) Phase Fractional Divider Control …\n528MHz Clock (PLL2) Phase Fractional Divider Control …\n528MHz Clock (PLL2) Phase Fractional Divider Control …\n528MHz Clock (PLL2) Phase Fractional Divider Control …\n528MHz Clock (PLL2) Phase Fractional Divider Control …\n528MHz Clock (PLL2) Phase Fractional Divider Control …\nAnalog Audio PLL control Register\nAnalog Audio PLL control Register\nAnalog Audio PLL control Register\nAnalog Audio PLL control Register\nDenominator of Audio PLL Fractional Loop Divider Register\nDenominator of Audio PLL Fractional Loop Divider Register\nNumerator of Audio PLL Fractional Loop Divider Register\nNumerator of Audio PLL Fractional Loop Divider Register\nAnalog Audio PLL control Register\nAnalog Audio PLL control Register\nAnalog Audio PLL control Register\nAnalog Audio PLL control Register\nAnalog ENET PLL Control Register\nAnalog ENET PLL Control Register\nAnalog ENET PLL Control Register\nAnalog ENET PLL Control Register\nAnalog ENET PLL Control Register\nAnalog ENET PLL Control Register\nAnalog ENET PLL Control Register\nAnalog ENET PLL Control Register\nAnalog System PLL Control Register\nAnalog System PLL Control Register\nAnalog System PLL Control Register\nAnalog System PLL Control Register\nDenominator of 528MHz System PLL Fractional Loop Divider …\nDenominator of 528MHz System PLL Fractional Loop Divider …\nNumerator of 528MHz System PLL Fractional Loop Divider …\nNumerator of 528MHz System PLL Fractional Loop Divider …\nAnalog System PLL Control Register\nAnalog System PLL Control Register\n528MHz System PLL Spread Spectrum Register\n528MHz System PLL Spread Spectrum Register\nAnalog System PLL Control Register\nAnalog System PLL Control Register\nAnalog USB1 480MHz PLL Control Register\nAnalog USB1 480MHz PLL Control Register\nAnalog USB1 480MHz PLL Control Register\nAnalog USB1 480MHz PLL Control Register\nAnalog USB1 480MHz PLL Control Register\nAnalog USB1 480MHz PLL Control Register\nAnalog USB1 480MHz PLL Control Register\nAnalog USB1 480MHz PLL Control Register\nCCM_ANALOG\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to power-down the analog bandgap reference …\nControl bit to disable the self-bias circuit in the analog …\nNot related to CCM. See Power Management Unit (PMU)\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAll analog except RTC powered down on stop mode assertion.\nBeside RTC, analog bandgap, 1p1 and 2p5 regulators are …\nBeside RTC, 1p1 and 2p5 regulators are also on, low-power …\nBeside RTC, low-power bandgap is selected and the rest …\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to power-down the analog bandgap reference …\nControl bit to disable the self-bias circuit in the analog …\nNot related to CCM. See Power Management Unit (PMU)\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAll analog except RTC powered down on stop mode assertion.\nBeside RTC, analog bandgap, 1p1 and 2p5 regulators are …\nBeside RTC, 1p1 and 2p5 regulators are also on, low-power …\nBeside RTC, low-power bandgap is selected and the rest …\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to power-down the analog bandgap reference …\nControl bit to disable the self-bias circuit in the analog …\nNot related to CCM. See Power Management Unit (PMU)\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAll analog except RTC powered down on stop mode assertion.\nBeside RTC, analog bandgap, 1p1 and 2p5 regulators are …\nBeside RTC, 1p1 and 2p5 regulators are also on, low-power …\nBeside RTC, low-power bandgap is selected and the rest …\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to power-down the analog bandgap reference …\nControl bit to disable the self-bias circuit in the analog …\nNot related to CCM. See Power Management Unit (PMU)\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAll analog except RTC powered down on stop mode assertion.\nBeside RTC, analog bandgap, 1p1 and 2p5 regulators are …\nBeside RTC, 1p1 and 2p5 regulators are also on, low-power …\nBeside RTC, low-power bandgap is selected and the rest …\nThis status bit is set to one when when any of the analog …\nThis status bit is set to one when when any of the digital …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis enables a feature that will clkgate (reset) all …\nThis enables a feature that will clkgate (reset) all …\nThis status bit is set to one when when any of the analog …\nThis status bit is set to one when when any of the digital …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis enables a feature that will clkgate (reset) all …\nThis enables a feature that will clkgate (reset) all …\nThis status bit is set to one when when any of the analog …\nThis status bit is set to one when when any of the digital …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis enables a feature that will clkgate (reset) all …\nThis enables a feature that will clkgate (reset) all …\nThis status bit is set to one when when any of the analog …\nThis status bit is set to one when when any of the digital …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis enables a feature that will clkgate (reset) all …\nThis enables a feature that will clkgate (reset) all …\nLSB of Post-divider for Audio PLL\nMSB of Post-divider for Audio PLL\nWhen USB is in low power suspend mode this Control bit is …\nThis field defines the brown out voltage offset for the …\nReg0 brownout status bit.Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nARM supply Not related to CCM. See Power Management Unit …\nNumber of clock periods (24MHz clock).Not related to CCM. …\nThis field defines the brown out voltage offset for the …\nReg1 brownout status bit. Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nGPU supply Not related to CCM. See Power Management Unit …\nNumber of clock periods (24MHz clock).Not related to CCM. …\nThis field defines the brown out voltage offset for the …\nReg2 brownout status bit.Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nSignals that the voltage is above the brownout level for …\nNumber of clock periods (24MHz clock).Not related to CCM. …\ndivide by 1 (Default)\ndivide by 2\ndivide by 1 (Default)\ndivide by 2\nPLL3 is being used by peripherals and is enabled when SoC …\nPLL3 can be disabled when the SoC is not in any low power …\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\n128\n256\n512\n64\nLSB of Post-divider for Audio PLL\nMSB of Post-divider for Audio PLL\nWhen USB is in low power suspend mode this Control bit is …\nThis field defines the brown out voltage offset for the …\nReg0 brownout status bit.Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nARM supply Not related to CCM. See Power Management Unit …\nNumber of clock periods (24MHz clock).Not related to CCM. …\nThis field defines the brown out voltage offset for the …\nReg1 brownout status bit. Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nGPU supply Not related to CCM. See Power Management Unit …\nNumber of clock periods (24MHz clock).Not related to CCM. …\nThis field defines the brown out voltage offset for the …\nReg2 brownout status bit.Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nSignals that the voltage is above the brownout level for …\nNumber of clock periods (24MHz clock).Not related to CCM. …\ndivide by 1 (Default)\ndivide by 2\ndivide by 1 (Default)\ndivide by 2\nPLL3 is being used by peripherals and is enabled when SoC …\nPLL3 can be disabled when the SoC is not in any low power …\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\n128\n256\n512\n64\nLSB of Post-divider for Audio PLL\nMSB of Post-divider for Audio PLL\nWhen USB is in low power suspend mode this Control bit is …\nThis field defines the brown out voltage offset for the …\nReg0 brownout status bit.Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nARM supply Not related to CCM. See Power Management Unit …\nNumber of clock periods (24MHz clock).Not related to CCM. …\nThis field defines the brown out voltage offset for the …\nReg1 brownout status bit. Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nGPU supply Not related to CCM. See Power Management Unit …\nNumber of clock periods (24MHz clock).Not related to CCM. …\nThis field defines the brown out voltage offset for the …\nReg2 brownout status bit.Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nSignals that the voltage is above the brownout level for …\nNumber of clock periods (24MHz clock).Not related to CCM. …\ndivide by 1 (Default)\ndivide by 2\ndivide by 1 (Default)\ndivide by 2\nPLL3 is being used by peripherals and is enabled when SoC …\nPLL3 can be disabled when the SoC is not in any low power …\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\n128\n256\n512\n64\nLSB of Post-divider for Audio PLL\nMSB of Post-divider for Audio PLL\nWhen USB is in low power suspend mode this Control bit is …\nThis field defines the brown out voltage offset for the …\nReg0 brownout status bit.Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nARM supply Not related to CCM. See Power Management Unit …\nNumber of clock periods (24MHz clock).Not related to CCM. …\nThis field defines the brown out voltage offset for the …\nReg1 brownout status bit. Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nGPU supply Not related to CCM. See Power Management Unit …\nNumber of clock periods (24MHz clock).Not related to CCM. …\nThis field defines the brown out voltage offset for the …\nReg2 brownout status bit.Not related to CCM. See Power …\nEnables the brownout detection.Not related to CCM. See …\nSignals that the voltage is above the brownout level for …\nNumber of clock periods (24MHz clock).Not related to CCM. …\ndivide by 1 (Default)\ndivide by 2\ndivide by 1 (Default)\ndivide by 2\nPLL3 is being used by peripherals and is enabled when SoC …\nPLL3 can be disabled when the SoC is not in any low power …\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\n128\n256\n512\n64\nIf set to 1, the IO fractional divider clock (reference …\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIf set to 1, the IO fractional divider clock (reference …\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIf set to 1, the IO fractional divider clock (reference …\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIf set to 1, the IO fractional divider clock (reference …\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIf set to 1, the IO fractional divider clock (reference …\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIf set to 1, the IO fractional divider clock (reference …\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIf set to 1, the IO fractional divider clock (reference …\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIf set to 1, the IO fractional divider clock (reference …\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nIO Clock Gate\nThis field controls the fractional divide value\nThis read-only bitfield is for DIAGNOSTIC PURPOSES ONLY …\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. Valid range for …\nEnable PLL output\n1 - PLL is currently locked. 0 - PLL is not currently …\nThese bits implement a divider after the PLL, but before …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nDivide by 4.\nDivide by 2.\nDivide by 1.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. Valid range for …\nEnable PLL output\n1 - PLL is currently locked. 0 - PLL is not currently …\nThese bits implement a divider after the PLL, but before …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nDivide by 4.\nDivide by 2.\nDivide by 1.\n30 bit denominator of fractional loop divider.\n30 bit numerator of fractional loop divider.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. Valid range for …\nEnable PLL output\n1 - PLL is currently locked. 0 - PLL is not currently …\nThese bits implement a divider after the PLL, but before …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nDivide by 4.\nDivide by 2.\nDivide by 1.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. Valid range for …\nEnable PLL output\n1 - PLL is currently locked. 0 - PLL is not currently …\nThese bits implement a divider after the PLL, but before …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nDivide by 4.\nDivide by 2.\nDivide by 1.\nBypass the PLL.\nDetermines the bypass source.\nEnable the PLL providing ENET 500 MHz reference clock\n1 - PLL is currently locked; 0 - PLL is not currently …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nBypass the PLL.\nDetermines the bypass source.\nEnable the PLL providing ENET 500 MHz reference clock\n1 - PLL is currently locked; 0 - PLL is not currently …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nBypass the PLL.\nDetermines the bypass source.\nEnable the PLL providing ENET 500 MHz reference clock\n1 - PLL is currently locked; 0 - PLL is not currently …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nBypass the PLL.\nDetermines the bypass source.\nEnable the PLL providing ENET 500 MHz reference clock\n1 - PLL is currently locked; 0 - PLL is not currently …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. 0 - Fout=Fref<em>20; </em>…\nEnable PLL output\n1 - PLL is currently locked; 0 - PLL is not currently …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. 0 - Fout=Fref<em>20; </em>…\nEnable PLL output\n1 - PLL is currently locked; 0 - PLL is not currently …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\n30 bit denominator (B) of fractional loop divider …\n30 bit numerator (A) of fractional loop divider (signed …\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. 0 - Fout=Fref<em>20; </em>…\nEnable PLL output\n1 - PLL is currently locked; 0 - PLL is not currently …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nEnable bit\nFrequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*…\nFrequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.\nSpread spectrum modulation disabled\nSoread spectrum modulation enabled\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. 0 - Fout=Fref<em>20; </em>…\nEnable PLL output\n1 - PLL is currently locked; 0 - PLL is not currently …\nPowers down the PLL.\nSelect the 24MHz oscillator as source.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. 0 - Fout=Fref<em>20; </em>…\nEnable the PLL clock output.\nPowers the 9-phase PLL outputs for USBPHYn\n1 - PLL is currently locked. 0 - PLL is not currently …\nPowers up the PLL. This bit will be set automatically when …\nSelect the 24MHz oscillator as source.\nPLL outputs for USBPHYn off.\nPLL outputs for USBPHYn on.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. 0 - Fout=Fref<em>20; </em>…\nEnable the PLL clock output.\nPowers the 9-phase PLL outputs for USBPHYn\n1 - PLL is currently locked. 0 - PLL is not currently …\nPowers up the PLL. This bit will be set automatically when …\nSelect the 24MHz oscillator as source.\nPLL outputs for USBPHYn off.\nPLL outputs for USBPHYn on.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. 0 - Fout=Fref<em>20; </em>…\nEnable the PLL clock output.\nPowers the 9-phase PLL outputs for USBPHYn\n1 - PLL is currently locked. 0 - PLL is not currently …\nPowers up the PLL. This bit will be set automatically when …\nSelect the 24MHz oscillator as source.\nPLL outputs for USBPHYn off.\nPLL outputs for USBPHYn on.\nBypass the PLL.\nDetermines the bypass source.\nThis field controls the PLL loop divider. 0 - Fout=Fref<em>20; </em>…\nEnable the PLL clock output.\nPowers the 9-phase PLL outputs for USBPHYn\n1 - PLL is currently locked. 0 - PLL is not currently …\nPowers up the PLL. This bit will be set automatically when …\nSelect the 24MHz oscillator as source.\nPLL outputs for USBPHYn off.\nPLL outputs for USBPHYn on.\nConfig security level register\nConfig security level register\nCSU registers\nHP0 register\nHP0 register\nHPCONTROL0 register\nHPCONTROL0 register\nCSU registers\nSecure access register\nSecure access register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nThe lock bit corresponding to the first slave. It is …\nThe lock bit corresponding to the second slave. It is …\nNon-secure supervisor read access control for the first …\nNon-secure supervisor read access control for the second …\nNon-secure supervisor write access control for the first …\nNon-secure supervisor write access control for the second …\nNon-secure user read access control for the first slave\nNon-secure user read access control for the second slave\nNon-secure user write access control for the first slave\nNon-secure user write access control for the second slave\nSecure supervisor read access control for the first slave\nSecure supervisor read access control for the second slave\nSecure supervisor write access control for the first slave\nSecure supervisor write access control for the second slave\nSecure user read access control for the first slave\nSecure user read access control for the second slave\nSecure user write access control for the first slave\nSecure user write access control for the second slave\nNot locked. The bits 16-23 can be written by the software.\nThe bits 16-23 are locked and can’t be written by the …\nNot locked. Bits 7-0 can be written by the software.\nBits 7-0 are locked and cannot be written by the software\nThe non-secure supervisor read access is disabled for the …\nThe non-secure supervisor read access is enabled for the …\nThe non-secure supervisor read access is disabled for the …\nThe non-secure supervisor read access is enabled for the …\nThe non-secure supervisor write access is disabled for the …\nThe non-secure supervisor write access is enabled for the …\nThe non-secure supervisor write access is disabled for the …\nThe non-secure supervisor write access is enabled for the …\nThe non-secure user read access is disabled for the first …\nThe non-secure user read access is enabled for the first …\nThe non-secure user read access is disabled for the second …\nThe non-secure user read access is enabled for the second …\nThe non-secure user write access is disabled for the first …\nThe non-secure user write access is enabled for the first …\nThe non-secure user write access is disabled for the …\nThe non-secure user write access is enabled for the second …\nThe secure supervisor read access is disabled for the …\nThe secure supervisor read access is enabled for the first …\nThe secure supervisor read access is disabled for the …\nThe secure supervisor read access is enabled for the …\nThe secure supervisor write access is disabled for the …\nThe secure supervisor write access is enabled for the …\nThe secure supervisor write access is disabled for the …\nThe secure supervisor write access is enabled for the …\nThe secure user read access is disabled for the first …\nThe secure user read access is enabled for the first slave.\nThe secure user read access is disabled for the second …\nThe secure user read access is enabled for the second …\nThe secure user write access is disabled for the first …\nThe secure user write access is enabled for the first …\nThe secure user write access is disabled for the second …\nThe secure user write access is enabled for the second …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nDetermines whether the register value of the corresponding …\nLock bit set by the TZ software for the CSI\nLock bit set by the TZ software for the DCP\nLock bit set by the TZ software for the eDMA\nLock bit set by the TZ software for the ENET\nLock bit set by the TZ software for the LCDIF\nLock bit set by the TZ software for the PXP\nLock bit set by the TZ software for the TPSMP\nLock bit set by the TZ software for the USB\nLock bit set by the TZ software for the USDHC1\nLock bit set by the TZ software for the USDHC2\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nThe hprot1 input signal value is routed to the csu_hprot1 …\nThe HP register bit is routed to the csu_hprot1 output for …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit cannot be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nIndicates the privilege/user mode for the CSI\nIndicates the privilege/user mode for the DCP\nIndicates the privilege/user mode for the eDMA\nIndicates the privilege/user mode for the ENET\nIndicates the privilege/user mode for the LCDIF\nIndicates the privilege/user mode for the PXP\nIndicates the privilege/user mode for the TPSMP\nIndicates the privilege/user mode for the USB\nIndicates the privilege/user mode for the USDHC1\nIndicates the privilege/user mode for the USDHC2\nLock bit set by the TZ software for the CSI\nLock bit set by the TZ software for the DCP\nLock bit set by the TZ software for the eDMA\nLock bit set by the TZ software for the ENET\nLock bit set by the TZ software for the LCDIF\nLock bit set by the TZ software for the PXP\nLock bit set by the TZ software for the TPSMP.\nLock bit set by the TZ software for the USB.\nLock bit set by the TZ software for the USDHC1\nLock bit set by the TZ software for the USDHC2.\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nUser mode for the corresponding master\nSupervisor mode for the corresponding master\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nLock bit set by the TZ software for the CSI\nLock bit set by the TZ software for the DCP\nLock bit set by the TZ software for the eDMA\nLock bit set by the TZ software for the ENET1 and ENET2\nLock bit set by the TZ software for the LCDIF\nLock bit set by the TZ software for the PXP\nLock bit set by the TZ software for the TPSMP\nLock bit set by the TZ software for the USB\nLock bit set by the TZ software for the USDHC1\nLock bit set by the TZ software for the USDHC2\nNon-secure access policy indicator bit\nNon-secure access policy indicator bit\nNon-secure access policy indicator bit\nNon-secure access policy indicator bit\nNon-secure access policy indicator bit\nNon-Secure Access Policy indicator bit\nNon-secure access policy indicator bit\nNon-secure access policy indicator bit\nNon-secure access policy indicator bit\nNon-secure access policy indicator bit\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nNo lock-the adjacent (next lower) bit can be written by …\nLock-the adjacent (next lower) bit can’t be written by …\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nSecure access for the corresponding type-1 master\nNon-secure access for the corresponding type-1 master\nDCDC\nDCDC Register 0\nDCDC Register 0\nDCDC Register 1\nDCDC Register 1\nDCDC Register 2\nDCDC Register 2\nDCDC Register 3\nDCDC Register 3\nDCDC\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nadjust value to poslimit_buck register\nreset current alert signal\nSet the threshold of current detector, if the peak current …\nDisable automatic clock switch from internal osc to xtal …\nenable the overload detection in power save mode, if …\nAdjust hysteretic value in low power from 12.5mV to 25mV\nthe period of counting the charging times in power save …\nthe threshold of the counting number of charging times …\nThe threshold of over current detection in run mode and …\nset to “1” to power down the low voltage detection …\npower down output range comparator\nThe power down signal of the current detector.\npower down overvoltage detection comparator\nPower down internal osc. Only set this bit, when 24 MHz …\npower down overcurrent detection comparator\npower down the zero cross detection function for …\nselect 24 MHz Crystal clock for DCDC, when …\nStatus register to indicate DCDC status. 1’b1: DCDC …\n1’b1: Disable xtalok detection circuit 1’b0: Enable …\nset to 1 to switch internal ring osc to xtal 24M\nEnable hysteresis in switching converter common mode …\nincrease the threshold detection for common mode analog …\nset the current bias of low power comparator 0x0: 50 nA …\nselect the feedback point of the internal regulator\ncontrol the load resistor of the internal regulator of …\ntrim bandgap voltage\nThis bit enables the DC-DC to improve efficiency and …\nSet high to improve the transition from heavy load to …\nSet to “0” : stop charging if the duty cycle is lower …\nRatio of integral control parameter to proportional …\nTwo’s complement feed forward step in duty cycle in the …\nMagnitude of proportional control parameter in the …\nEnable analog circuit of DC-DC converter to respond faster …\nInvert the sign of the hysteresis in DC-DC analog …\nIncrease the threshold detection for RC scale circuit.\nDisable stepping for the output VDD_SOC of DCDC\nSet DCDC clock to half freqeuncy for continuous mode\nAjust delay to reduce ground noise\nReserved\nTarget value of standby (low power) mode 0x0: 0\nTarget value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: …\nDCP capability 0 register\nDCP capability 0 register\nDCP capability 1 register\nDCP capability 1 register\nDCP channel 0 command pointer address register\nDCP channel 0 command pointer address register\nDCP channel 0 options register\nDCP channel 0 options register\nDCP channel 0 options register\nDCP channel 0 options register\nDCP channel 0 options register\nDCP channel 0 options register\nDCP channel 0 options register\nDCP channel 0 options register\nDCP channel 0 semaphore register\nDCP channel 0 semaphore register\nDCP channel 0 status register\nDCP channel 0 status register\nDCP channel 0 status register\nDCP channel 0 status register\nDCP channel 0 status register\nDCP channel 0 status register\nDCP channel 0 status register\nDCP channel 0 status register\nDCP channel 1 command pointer address register\nDCP channel 1 command pointer address register\nDCP channel 1 options register\nDCP channel 1 options register\nDCP channel 1 options register\nDCP channel 1 options register\nDCP channel 1 options register\nDCP channel 1 options register\nDCP channel 1 options register\nDCP channel 1 options register\nDCP channel 1 semaphore register\nDCP channel 1 semaphore register\nDCP channel 1 status register\nDCP channel 1 status register\nDCP channel 1 status register\nDCP channel 1 status register\nDCP channel 1 status register\nDCP channel 1 status register\nDCP channel 1 status register\nDCP channel 1 status register\nDCP channel 2 command pointer address register\nDCP channel 2 command pointer address register\nDCP channel 2 options register\nDCP channel 2 options register\nDCP channel 2 options register\nDCP channel 2 options register\nDCP channel 2 options register\nDCP channel 2 options register\nDCP channel 2 options register\nDCP channel 2 options register\nDCP channel 2 semaphore register\nDCP channel 2 semaphore register\nDCP channel 2 status register\nDCP channel 2 status register\nDCP channel 2 status register\nDCP channel 2 status register\nDCP channel 2 status register\nDCP channel 2 status register\nDCP channel 2 status register\nDCP channel 2 status register\nDCP channel 3 command pointer address register\nDCP channel 3 command pointer address register\nDCP channel 3 options register\nDCP channel 3 options register\nDCP channel 3 options register\nDCP channel 3 options register\nDCP channel 3 options register\nDCP channel 3 options register\nDCP channel 3 options register\nDCP channel 3 options register\nDCP channel 3 semaphore register\nDCP channel 3 semaphore register\nDCP channel 3 status register\nDCP channel 3 status register\nDCP channel 3 status register\nDCP channel 3 status register\nDCP channel 3 status register\nDCP channel 3 status register\nDCP channel 3 status register\nDCP channel 3 status register\nDCP channel control register\nDCP channel control register\nDCP channel control register\nDCP channel control register\nDCP channel control register\nDCP channel control register\nDCP channel control register\nDCP channel control register\nDCP context buffer pointer\nDCP context buffer pointer\nDCP control register 0\nDCP control register 0\nDCP control register 0\nDCP control register 0\nDCP control register 0\nDCP control register 0\nDCP control register 0\nDCP control register 0\nDCP debug data register\nDCP debug data register\nDCP debug select register\nDCP debug select register\nDCP register reference index\nDCP key index\nDCP key index\nDCP key data\nDCP key data\nDCP work packet 0 status register\nDCP work packet 0 status register\nDCP work packet 1 status register\nDCP work packet 1 status register\nDCP work packet 2 status register\nDCP work packet 2 status register\nDCP work packet 3 status register\nDCP work packet 3 status register\nDCP work packet 4 status register\nDCP work packet 4 status register\nDCP work packet 5 status register\nDCP work packet 5 status register\nDCP work packet 6 status register\nDCP work packet 6 status register\nDCP page table register\nDCP page table register\nDCP register reference index\nDCP status register\nDCP status register\nDCP status register\nDCP status register\nDCP status register\nDCP status register\nDCP status register\nDCP status register\nDCP version register\nDCP version register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nWrite to 1 to disable the decryption\nWrite to a 1 to disable the per-device unique key\nEncoded value indicating the number of channels …\nEncoded value indicating the number of key-storage …\nOne-hot field indicating which cipher algorithms are …\nOne-hot field indicating which hashing features are …\nAES128\nCRC32\nSHA1\nSHA256\nPointer to the descriptor structure to be processed for …\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThe value written to this field is added to the semaphore …\nThis read-only field shows the current (instantaneous) …\nIndicates the additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation …\nIndicates the tag from the last completed packet in the …\nError signalled because an error is reported …\nError signalled because the control packet specifies an …\nError signalled because the next pointer is 0x00000000\nError signalled because the semaphore is non-zero and …\nError signalled because an error is reported …\nIndicates the additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation …\nIndicates the tag from the last completed packet in the …\nError signalled because an error is reported …\nError signalled because the control packet specifies an …\nError signalled because the next pointer is 0x00000000\nError signalled because the semaphore is non-zero and …\nError signalled because an error is reported …\nIndicates the additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation …\nIndicates the tag from the last completed packet in the …\nError signalled because an error is reported …\nError signalled because the control packet specifies an …\nError signalled because the next pointer is 0x00000000\nError signalled because the semaphore is non-zero and …\nError signalled because an error is reported …\nIndicates the additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation …\nIndicates the tag from the last completed packet in the …\nError signalled because an error is reported …\nError signalled because the control packet specifies an …\nError signalled because the next pointer is 0x00000000\nError signalled because the semaphore is non-zero and …\nError signalled because an error is reported …\nPointer to the descriptor structure to be processed for …\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThe value written to this field is added to the semaphore …\nThis read-only field shows the current (instantaneous) …\nIndicates the additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported when …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported when …\nIndicates the additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported when …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported when …\nIndicates the additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported when …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported when …\nIndicates the additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported when …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported when …\nPointer to the descriptor structure to be processed for …\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThe value written to this field is added to the semaphore …\nThis read-only field shows the current (instantaneous) …\nIndicates additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported while …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported while …\nIndicates additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported while …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported while …\nIndicates additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported while …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported while …\nIndicates additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported while …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported while …\nPointer to the descriptor structure to be processed for …\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThis field indicates the recovery time for the channel\nThe value written to this field is added to the semaphore …\nThis read-only field shows the current (instantaneous) …\nIndicates additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported while …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported while …\nIndicates additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported while …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported while …\nIndicates additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported while …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported while …\nIndicates additional error codes for some of the error …\nThis bit indicates that a bus error occurred when storing …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a page fault occurred while …\nThis bit indicates that the hardware detected an invalid …\nThis bit indicates that a bus error occurred when reading …\nThis bit indicates that a hashing check operation is …\nIndicates the tag from the last completed packet in the …\nError is signalled because an error was reported while …\nError is signalled because the control packet specifies an …\nError is signalled because the next pointer is 0x00000000.\nError is signalled because the semaphore is of a non-zero …\nError is signalled because an error was reported while …\nIndicates that the interrupt for channel 0 must be merged …\nSetting a bit in this field enables the DMA channel …\nSetting a bit in this field causes the corresponding …\nCH0\nCH1\nCH2\nCH3\nCH0\nCH1\nCH2\nCH3\nIndicates that the interrupt for channel 0 must be merged …\nSetting a bit in this field enables the DMA channel …\nSetting a bit in this field causes the corresponding …\nCH0\nCH1\nCH2\nCH3\nCH0\nCH1\nCH2\nCH3\nIndicates that the interrupt for channel 0 must be merged …\nSetting a bit in this field enables the DMA channel …\nSetting a bit in this field causes the corresponding …\nCH0\nCH1\nCH2\nCH3\nCH0\nCH1\nCH2\nCH3\nIndicates that the interrupt for channel 0 must be merged …\nSetting a bit in this field enables the DMA channel …\nSetting a bit in this field causes the corresponding …\nCH0\nCH1\nCH2\nCH3\nCH0\nCH1\nCH2\nCH3\nContext pointer address\nPer-channel interrupt enable bit\nThis bit must be set to zero for a normal operation\nThe software must set this bit to enable the caching of …\nEnable automatic context switching for the channels\nThe software must set this bit to enable the ragged writes …\nIndicates whether the crypto (cipher/hash) functions are …\nIndicates whether the SHA1/SHA2 functions are present.\nSet this bit to zero to enable a normal DCP operation\nCH0\nCH1\nCH2\nCH3\nAbsent\nPresent\nAbsent\nPresent\nPer-channel interrupt enable bit\nThis bit must be set to zero for a normal operation\nThe software must set this bit to enable the caching of …\nEnable automatic context switching for the channels\nThe software must set this bit to enable the ragged writes …\nIndicates whether the crypto (cipher/hash) functions are …\nIndicates whether the SHA1/SHA2 functions are present.\nSet this bit to zero to enable a normal DCP operation\nCH0\nCH1\nCH2\nCH3\nAbsent\nPresent\nAbsent\nPresent\nPer-channel interrupt enable bit\nThis bit must be set to zero for a normal operation\nThe software must set this bit to enable the caching of …\nEnable automatic context switching for the channels\nThe software must set this bit to enable the ragged writes …\nIndicates whether the crypto (cipher/hash) functions are …\nIndicates whether the SHA1/SHA2 functions are present.\nSet this bit to zero to enable a normal DCP operation\nCH0\nCH1\nCH2\nCH3\nAbsent\nPresent\nAbsent\nPresent\nPer-channel interrupt enable bit\nThis bit must be set to zero for a normal operation\nThe software must set this bit to enable the caching of …\nEnable automatic context switching for the channels\nThe software must set this bit to enable the ragged writes …\nIndicates whether the crypto (cipher/hash) functions are …\nIndicates whether the SHA1/SHA2 functions are present.\nSet this bit to zero to enable a normal DCP operation\nCH0\nCH1\nCH2\nCH3\nAbsent\nPresent\nAbsent\nPresent\nDebug data\nSelects a value to read via the debug data register.\nCONTROL\nOTPKEY0\nOTPKEY1\nOTPKEY2\nOTPKEY3\nKey index pointer. The valid indices are 0-[number_keys].\nKey subword pointer\nWord 0 data for the key. This is the least-significant …\nNext pointer register\nReflects whether the next command pointer register must be …\nReflects whether the next packet’s address is located …\nReflects whether the calculated hash value must be …\nWhen the cipher block is enabled, this bit indicates …\nReflects whether the cipher block must load the …\nWhen this bit is set (MEMCOPY and BLIT modes only), the …\nReflects whether the channel’s semaphore must be …\nReflects whether the DCP must perform a blit operation\nReflects whether the selected cipher function must be …\nReflects whether the selected hashing function must be …\nReflects whether the selected hashing function should be …\nReflects whether the current hashing block is the initial …\nWhen the hashing is enabled, this bit controls whether the …\nReflects whether the current hashing block is the final …\nReflects whether the DCP engine byteswaps the input data …\nReflects whether the DCP engine wordswaps the input data …\nReflects whether the channel must issue an interrupt upon …\nReflects whether the DCP engine swaps the key bytes …\nReflects whether the DCP engine swaps the key words …\nReflects whether a hardware-based key must be used\nReflects whether the DCP engine byteswaps the output data …\nReflects whether the DCP engine wordswaps the output data …\nWhen set, it indicates the payload contains the key\nPacket Tag\nThis bit is used to test the channel semaphore transition …\nDECRYPT\nENCRYPT\nINPUT\nOUTPUT\nCipher configuration bits. Optional configuration bits are …\nCipher mode selection field. Reflects the mode of …\nCipher selection field\nHash Selection Field\nKey selection field\nCBC\nECB\nAES128\nCRC32\nSHA1\nSHA256\nKEY0\nKEY1\nKEY2\nKEY3\nOTP_KEY\nUNIQUE_KEY\nSource buffer address pointer\nDestination buffer address pointer\nByte count register. This value is the working value and …\nThis regiser reflects the payload pointer for the current …\nPage table base address\nPage table enable control\nPage table flush control. To flush the TLB, write this bit …\nCurrent (active) channel (encoded)\nIndicates which channels have pending interrupt requests\nWhen set, it indicates that the OTP key is shifted from …\nIndicates which channels are ready to proceed with a …\nCH0\nCH1\nCH2\nCH3\nNone\nCH0\nCH1\nCH2\nCH3\nCurrent (active) channel (encoded)\nIndicates which channels have pending interrupt requests\nWhen set, it indicates that the OTP key is shifted from …\nIndicates which channels are ready to proceed with a …\nCH0\nCH1\nCH2\nCH3\nNone\nCH0\nCH1\nCH2\nCH3\nCurrent (active) channel (encoded)\nIndicates which channels have pending interrupt requests\nWhen set, it indicates that the OTP key is shifted from …\nIndicates which channels are ready to proceed with a …\nCH0\nCH1\nCH2\nCH3\nNone\nCH0\nCH1\nCH2\nCH3\nCurrent (active) channel (encoded)\nIndicates which channels have pending interrupt requests\nWhen set, it indicates that the OTP key is shifted from …\nIndicates which channels are ready to proceed with a …\nCH0\nCH1\nCH2\nCH3\nNone\nCH0\nCH1\nCH2\nCH3\nFixed read-only value reflecting the MAJOR version of the …\nFixed read-only value reflecting the MINOR version of the …\nFixed read-only value reflecting the stepping of the …\nClear DONE Status Bit Register\nClear DONE Status Bit Register\nClear Enable Error Interrupt Register\nClear Enable Error Interrupt Register\nClear Enable Request Register\nClear Enable Request Register\nClear Error Register\nClear Error Register\nClear Interrupt Request Register\nClear Interrupt Request Register\nControl Register\nControl Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nChannel Priority Register\nDMA\nEnable Asynchronous Request in Stop Register")