rtic/dev/api/search.desc/imxrt_ral/imxrt_ral-desc-1-.js

searchState.loadedDescShard("imxrt_ral", 1, "Enable Asynchronous Request in Stop Register\nEnable Error Interrupt Register\nEnable Error Interrupt Register\nEnable Request Register\nEnable Request Register\nError Register\nError Register\nError Status Register\nError Status Register\nHardware Request Status Register\nHardware Request Status Register\nInterrupt Request Register\nInterrupt Request Register\nDMA\nSet Enable Error Interrupt Register\nSet Enable Error Interrupt Register\nSet Enable Request Register\nSet Enable Request Register\nSet START Bit Register\nSet START Bit Register\nCluster TCD%s, containing TCD*_SADDR, TCD*_SOFF, TCD*_…\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nClears All DONE Bits\nClear DONE Bit\nNo Op enable\nClears only the TCDn_CSR[DONE] bit specified in the CDNE …\nClears all bits in TCDn_CSR[DONE]\nNormal operation\nNo operation, ignore the other bits in this register\nClear All Enable Error Interrupts\nClear Enable Error Interrupt\nNo Op enable\nClear only the EEI bit specified in the CEEI field\nClear all bits in EEI\nNormal operation\nNo operation, ignore the other bits in this register\nClear All Enable Requests\nClear Enable Request\nNo Op enable\nClear only the ERQ bit specified in the CERQ field\nClear all bits in ERQ\nNormal operation\nNo operation, ignore the other bits in this register\nClear All Error Indicators\nClear Error Indicator\nNo Op enable\nClear only the ERR bit specified in the CERR field\nClear all bits in ERR\nNormal operation\nNo operation, ignore the other bits in this register\nClear All Interrupt Requests\nClear Interrupt Request\nNo Op enable\nClear only the INT bit specified in the CINT field\nClear all bits in INT\nNormal operation\nNo operation, ignore the other bits in this register\nDMA Active Status\nContinuous Link Mode\nCancel Transfer\nError Cancel Transfer\nEnable Debug\nEnable Minor Loop Mapping\nEnable Round Robin Channel Arbitration\nHalt DMA Operations\nHalt On Error\neDMA is idle.\neDMA is executing a channel.\nA minor loop channel link made to itself goes through …\nA minor loop channel link made to itself does not go …\nNormal operation\nCancel the remaining data transfer. Stop the executing …\nNormal operation\nCancel the remaining data transfer in the same fashion as …\nWhen in debug mode, the DMA continues to operate.\nWhen in debug mode, the DMA stalls the start of a new …\nDisabled. TCDn.word2 is defined as a 32-bit NBYTES field.\nEnabled. TCDn.word2 is redefined to include individual …\nFixed priority arbitration is used for channel selection .\nRound robin arbitration is used for channel selection .\nNormal operation\nStall the start of any new channels. Executing channels …\nNormal operation\nAny error causes the HALT bit to set. Subsequently, all …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nChannel n Arbitration Priority\nDisable Preempt Ability. This field resets to 0.\nEnable Channel Preemption. This field resets to 0.\nChannel n can suspend a lower priority channel.\nChannel n cannot suspend any channel, regardless of …\nChannel n cannot be suspended by a higher priority channel…\nChannel n can be temporarily suspended by the service …\nEnable asynchronous DMA request in stop mode for channel 0.\nEnable asynchronous DMA request in stop mode for channel 1.\nEnable asynchronous DMA request in stop mode for channel 10\nEnable asynchronous DMA request in stop mode for channel 11\nEnable asynchronous DMA request in stop mode for channel 12\nEnable asynchronous DMA request in stop mode for channel 13\nEnable asynchronous DMA request in stop mode for channel 14\nEnable asynchronous DMA request in stop mode for channel 15\nEnable asynchronous DMA request in stop mode for channel 2.\nEnable asynchronous DMA request in stop mode for channel 3.\nEnable asynchronous DMA request in stop mode for channel 4\nEnable asynchronous DMA request in stop mode for channel 5\nEnable asynchronous DMA request in stop mode for channel 6\nEnable asynchronous DMA request in stop mode for channel 7\nEnable asynchronous DMA request in stop mode for channel 8\nEnable asynchronous DMA request in stop mode for channel 9\nDisable asynchronous DMA request for channel 0.\nEnable asynchronous DMA request for channel 0.\nDisable asynchronous DMA request for channel 10.\nEnable asynchronous DMA request for channel 10.\nDisable asynchronous DMA request for channel 11.\nEnable asynchronous DMA request for channel 11.\nDisable asynchronous DMA request for channel 12.\nEnable asynchronous DMA request for channel 12.\nDisable asynchronous DMA request for channel 13.\nEnable asynchronous DMA request for channel 13.\nDisable asynchronous DMA request for channel 14.\nEnable asynchronous DMA request for channel 14.\nDisable asynchronous DMA request for channel 15.\nEnable asynchronous DMA request for channel 15.\nDisable asynchronous DMA request for channel 1\nEnable asynchronous DMA request for channel 1.\nDisable asynchronous DMA request for channel 2.\nEnable asynchronous DMA request for channel 2.\nDisable asynchronous DMA request for channel 3.\nEnable asynchronous DMA request for channel 3.\nDisable asynchronous DMA request for channel 4.\nEnable asynchronous DMA request for channel 4.\nDisable asynchronous DMA request for channel 5.\nEnable asynchronous DMA request for channel 5.\nDisable asynchronous DMA request for channel 6.\nEnable asynchronous DMA request for channel 6.\nDisable asynchronous DMA request for channel 7.\nEnable asynchronous DMA request for channel 7.\nDisable asynchronous DMA request for channel 8.\nEnable asynchronous DMA request for channel 8.\nDisable asynchronous DMA request for channel 9.\nEnable asynchronous DMA request for channel 9.\nEnable Error Interrupt 0\nEnable Error Interrupt 1\nEnable Error Interrupt 10\nEnable Error Interrupt 11\nEnable Error Interrupt 12\nEnable Error Interrupt 13\nEnable Error Interrupt 14\nEnable Error Interrupt 15\nEnable Error Interrupt 2\nEnable Error Interrupt 3\nEnable Error Interrupt 4\nEnable Error Interrupt 5\nEnable Error Interrupt 6\nEnable Error Interrupt 7\nEnable Error Interrupt 8\nEnable Error Interrupt 9\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nThe error signal for corresponding channel does not …\nThe assertion of the error signal for corresponding …\nEnable DMA Request 0\nEnable DMA Request 1\nEnable DMA Request 10\nEnable DMA Request 11\nEnable DMA Request 12\nEnable DMA Request 13\nEnable DMA Request 14\nEnable DMA Request 15\nEnable DMA Request 2\nEnable DMA Request 3\nEnable DMA Request 4\nEnable DMA Request 5\nEnable DMA Request 6\nEnable DMA Request 7\nEnable DMA Request 8\nEnable DMA Request 9\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nThe DMA request signal for the corresponding channel is …\nError In Channel 0\nError In Channel 1\nError In Channel 10\nError In Channel 11\nError In Channel 12\nError In Channel 13\nError In Channel 14\nError In Channel 15\nError In Channel 2\nError In Channel 3\nError In Channel 4\nError In Channel 5\nError In Channel 6\nError In Channel 7\nError In Channel 8\nError In Channel 9\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nAn error in this channel has not occurred\nAn error in this channel has occurred\nChannel Priority Error\nDestination Address Error\nDestination Bus Error\nDestination Offset Error\nTransfer Canceled\nError Channel Number or Canceled Channel Number\nNBYTES/CITER Configuration Error\nSource Address Error\nSource Bus Error\nScatter/Gather Configuration Error\nSource Offset Error\nVLD\nNo channel priority error\nThe last recorded error was a configuration error in the …\nNo destination address configuration error\nThe last recorded error was a configuration error detected …\nNo destination bus error\nThe last recorded error was a bus error on a destination …\nNo destination offset configuration error\nThe last recorded error was a configuration error detected …\nNo canceled transfers\nThe last recorded entry was a canceled transfer by the …\nNo NBYTES/CITER configuration error\nThe last recorded error was a configuration error detected …\nNo source address configuration error.\nThe last recorded error was a configuration error detected …\nNo source bus error\nThe last recorded error was a bus error on a source read\nNo scatter/gather configuration error\nThe last recorded error was a configuration error detected …\nNo source offset configuration error\nThe last recorded error was a configuration error detected …\nNo ERR bits are set.\nAt least one ERR bit is set indicating a valid error …\nHardware Request Status Channel 0\nHardware Request Status Channel 1\nHardware Request Status Channel 10\nHardware Request Status Channel 11\nHardware Request Status Channel 12\nHardware Request Status Channel 13\nHardware Request Status Channel 14\nHardware Request Status Channel 15\nHardware Request Status Channel 2\nHardware Request Status Channel 3\nHardware Request Status Channel 4\nHardware Request Status Channel 5\nHardware Request Status Channel 6\nHardware Request Status Channel 7\nHardware Request Status Channel 8\nHardware Request Status Channel 9\nA hardware service request for channel 0 is not present\nA hardware service request for channel 0 is present\nA hardware service request for channel 10 is not present\nA hardware service request for channel 10 is present\nA hardware service request for channel 11 is not present\nA hardware service request for channel 11 is present\nA hardware service request for channel 12 is not present\nA hardware service request for channel 12 is present\nA hardware service request for channel 13 is not present\nA hardware service request for channel 13 is present\nA hardware service request for channel 14 is not present\nA hardware service request for channel 14 is present\nA hardware service request for channel 15 is not present\nA hardware service request for channel 15 is present\nA hardware service request for channel 1 is not present\nA hardware service request for channel 1 is present\nA hardware service request for channel 2 is not present\nA hardware service request for channel 2 is present\nA hardware service request for channel 3 is not present\nA hardware service request for channel 3 is present\nA hardware service request for channel 4 is not present\nA hardware service request for channel 4 is present\nA hardware service request for channel 5 is not present\nA hardware service request for channel 5 is present\nA hardware service request for channel 6 is not present\nA hardware service request for channel 6 is present\nA hardware service request for channel 7 is not present\nA hardware service request for channel 7 is present\nA hardware service request for channel 8 is not present\nA hardware service request for channel 8 is present\nA hardware service request for channel 9 is not present\nA hardware service request for channel 9 is present\nInterrupt Request 0\nInterrupt Request 1\nInterrupt Request 10\nInterrupt Request 11\nInterrupt Request 12\nInterrupt Request 13\nInterrupt Request 14\nInterrupt Request 15\nInterrupt Request 2\nInterrupt Request 3\nInterrupt Request 4\nInterrupt Request 5\nInterrupt Request 6\nInterrupt Request 7\nInterrupt Request 8\nInterrupt Request 9\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nThe interrupt request for corresponding channel is cleared\nThe interrupt request for corresponding channel is active\nNo Op enable\nSets All Enable Error Interrupts\nSet Enable Error Interrupt\nNormal operation\nNo operation, ignore the other bits in this register\nSet only the EEI bit specified in the SEEI field.\nSets all bits in EEI\nNo Op enable\nSet All Enable Requests\nSet Enable Request\nNormal operation\nNo operation, ignore the other bits in this register\nSet only the ERQ bit specified in the SERQ field\nSet all bits in ERQ\nNo Op enable\nSet All START Bits (activates all channels)\nSet START Bit\nNormal operation\nNo operation, ignore the other bits in this register\nSet only the TCDn_CSR[START] bit specified in the SSRT …\nSet all bits in TCDn_CSR[START]\nCluster TCD%s, containing TCD*_SADDR, TCD*_SOFF, TCD*_…\nTCD Transfer Attributes\nTCD Transfer Attributes\nTCD Beginning Minor Loop Link, Major Loop Count (Channel …\nTCD Beginning Minor Loop Link, Major Loop Count (Channel …\nTCD Current Minor Loop Link, Major Loop Count (Channel …\nTCD Current Minor Loop Link, Major Loop Count (Channel …\nTCD Control and Status\nTCD Control and Status\nTCD Destination Address\nTCD Destination Address\nTCD Last Destination Address Adjustment/Scatter Gather …\nTCD Last Destination Address Adjustment/Scatter Gather …\nTCD Signed Destination Address Offset\nTCD Signed Destination Address Offset\nTCD Minor Byte Count (Minor Loop Mapping Disabled)\nTCD Minor Byte Count (Minor Loop Mapping Disabled)\nTCD Source Address\nTCD Source Address\nTCD Last Source Address Adjustment\nTCD Last Source Address Adjustment\nTCD Signed Source Address Offset\nTCD Signed Source Address Offset\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDestination Address Modulo\nDestination data transfer size\nSource Address Modulo\nSource data transfer size\nSource address modulo feature is disabled\nThis value defines a specific address range specified to …\nThis value defines a specific address range specified to …\nThis value defines a specific address range specified to …\nThis value defines a specific address range specified to …\nThis value defines a specific address range specified to …\nThis value defines a specific address range specified to …\nThis value defines a specific address range specified to …\nThis value defines a specific address range specified to …\nThis value defines a specific address range specified to …\n8-bit\n16-bit\n32-bit\n64-bit\n32-byte burst (4 beats of 64 bits)\nStarting Major Iteration Count\nEnables channel-to-channel linking on minor loop complete\nThe channel-to-channel linking is disabled\nThe channel-to-channel linking is enabled\nCurrent Major Iteration Count\nEnable channel-to-channel linking on minor-loop complete\nThe channel-to-channel linking is disabled\nThe channel-to-channel linking is enabled\nChannel Active\nBandwidth Control\nChannel Done\nDisable Request\nEnable Scatter/Gather Processing\nEnable an interrupt when major counter is half complete.\nEnable an interrupt when major iteration count completes.\nEnable channel-to-channel linking on major loop complete\nMajor Loop Link Channel Number\nChannel Start\nNo eDMA engine stalls.\neDMA engine stalls for 4 cycles after each R/W.\neDMA engine stalls for 8 cycles after each R/W.\nThe channel’s ERQ bit is not affected.\nThe channel’s ERQ bit is cleared when the major loop is …\nThe current channel’s TCD is normal format.\nThe current channel’s TCD specifies a scatter gather …\nThe half-point interrupt is disabled.\nThe half-point interrupt is enabled.\nThe end-of-major loop interrupt is disabled.\nThe end-of-major loop interrupt is enabled.\nThe channel-to-channel linking is disabled.\nThe channel-to-channel linking is enabled.\nThe channel is not explicitly started.\nThe channel is explicitly started via a software initiated …\nDestination Address\nDLASTSGA\nDestination Address Signed Offset\nMinor Byte Transfer Count\nSource Address\nLast Source Address Adjustment\nSource address signed offset\nChannel 0 Configuration Register\nChannel 0 Configuration Register\nDMAMUX\nDMAMUX\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDMA Channel Always Enable\nDMA Mux Channel Enable\nDMA Channel Source (Slot Number)\nDMA Channel Trigger Enable\nDMA Channel Always ON function is disabled\nDMA Channel Always ON function is enabled\nDMA Mux channel is disabled\nDMA Mux channel is enabled\nTriggering is disabled. If triggering is disabled and ENBL …\nTriggering is enabled. If triggering is enabled and ENBL …\nClock Control Register\nClock Control Register\nClock Prescaler Register\nClock Prescaler Register\nCompare High Register\nCompare High Register\nCompare Low Register\nCompare Low Register\nControl Register\nControl Register\nEWM\nEWM\nService Register\nService Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nCLKSEL\nCLK_DIV\nCOMPAREH\nCOMPAREL\nEWM_in’s Assertion State Select.\nEWM enable.\nInput Enable.\nInterrupt Enable.\nSERVICE\nFlexIO Control Register\nFlexIO Control Register\nFLEXIO\nParameter Register\nParameter Register\nPin State Register\nPin State Register\nFLEXIO\nShifter Buffer N Register\nShifter Buffer N Register\nShifter Buffer N Bit Byte Swapped Register\nShifter Buffer N Bit Byte Swapped Register\nShifter Buffer N Bit Swapped Register\nShifter Buffer N Bit Swapped Register\nShifter Buffer N Byte Swapped Register\nShifter Buffer N Byte Swapped Register\nShifter Buffer N Half Word Swapped Register\nShifter Buffer N Half Word Swapped Register\nShifter Buffer N Nibble Byte Swapped Register\nShifter Buffer N Nibble Byte Swapped Register\nShifter Buffer N Nibble Swapped Register\nShifter Buffer N Nibble Swapped Register\nShifter Configuration N Register\nShifter Configuration N Register\nShifter Control N Register\nShifter Control N Register\nShifter Error Interrupt Enable\nShifter Error Interrupt Enable\nShifter Error Register\nShifter Error Register\nShifter Status DMA Enable\nShifter Status DMA Enable\nShifter Status Interrupt Enable\nShifter Status Interrupt Enable\nShifter Status Register\nShifter Status Register\nShifter State Register\nShifter State Register\nTimer Configuration N Register\nTimer Configuration N Register\nTimer Compare N Register\nTimer Compare N Register\nTimer Control N Register\nTimer Control N Register\nTimer Interrupt Enable Register\nTimer Interrupt Enable Register\nTimer Status Register\nTimer Status Register\nVersion ID Register\nVersion ID Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nFlexIO Control Register\nFlexIO Control Register\nFLEXIO\nParameter Register\nParameter Register\nPin State Register\nPin State Register\nFLEXIO\nShifter Buffer N Register\nShifter Buffer N Register\nShifter Buffer N Bit Byte Swapped Register\nShifter Buffer N Bit Byte Swapped Register\nShifter Buffer N Bit Swapped Register\nShifter Buffer N Bit Swapped Register\nShifter Buffer N Byte Swapped Register\nShifter Buffer N Byte Swapped Register\nShifter Buffer N Half Word Swapped Register\nShifter Buffer N Half Word Swapped Register\nShifter Buffer N Nibble Byte Swapped Register\nShifter Buffer N Nibble Byte Swapped Register\nShifter Buffer N Nibble Swapped Register\nShifter Buffer N Nibble Swapped Register\nShifter Configuration N Register\nShifter Configuration N Register\nShifter Control N Register\nShifter Control N Register\nShifter Error Interrupt Enable\nShifter Error Interrupt Enable\nShifter Error Register\nShifter Error Register\nShifter Status DMA Enable\nShifter Status DMA Enable\nShifter Status Interrupt Enable\nShifter Status Interrupt Enable\nShifter Status Register\nShifter Status Register\nShifter State Register\nShifter State Register\nTimer Configuration N Register\nTimer Configuration N Register\nTimer Compare N Register\nTimer Compare N Register\nTimer Control N Register\nTimer Control N Register\nTimer Interrupt Enable Register\nTimer Interrupt Enable Register\nTimer Status Register\nTimer Status Register\nVersion ID Register\nVersion ID Register\nReturns the instance number <code>N</code> for a peripheral instance.\nDebug Enable\nDoze Enable\nFast Access\nFlexIO Enable\nSoftware Reset\nFlexIO is disabled in debug modes.\nFlexIO is enabled in debug modes\nFlexIO enabled in Doze modes.\nFlexIO disabled in Doze modes.\nConfigures for normal register accesses to FlexIO\nConfigures for fast register accesses to FlexIO\nFlexIO module is disabled.\nFlexIO module is enabled.\nSoftware reset is disabled\nSoftware reset is enabled, all FlexIO registers except the …\nPin Number\nShifter Number\nTimer Number\nTrigger Number\nPin Data Input\nShift Buffer\nShift Buffer\nShift Buffer\nShift Buffer\nShift Buffer\nShift Buffer\nShift Buffer\nInput Source\nParallel Width\nShifter Start bit\nShifter Stop bit\nPin\nShifter N+1 Output\nStart bit disabled for transmitter/receiver/match store, …\nStart bit disabled for transmitter/receiver/match store, …\nTransmitter outputs start bit value 0 before loading data …\nTransmitter outputs start bit value 1 before loading data …\nStop bit disabled for transmitter/receiver/match store\nTransmitter outputs stop bit value 0 on store, …\nTransmitter outputs stop bit value 1 on store, …\nShifter Pin Configuration\nShifter Pin Polarity\nShifter Pin Select\nShifter Mode\nTimer Polarity\nTimer Select\nShifter pin output disabled\nShifter pin open drain or bidirectional output enable\nShifter pin bidirectional output data\nShifter pin output\nPin is active high\nPin is active low\nDisabled.\nReceive mode. Captures the current Shifter content into …\nTransmit mode. Load SHIFTBUF contents into the Shifter on …\nMatch Store mode. Shifter data is compared to SHIFTBUF …\nMatch Continuous mode. Shifter data is continuously …\nState mode. SHIFTBUF contents are used for storing …\nLogic mode. SHIFTBUF contents are used for implementing …\nShift on posedge of Shift clock\nShift on negedge of Shift clock\nShifter Error Interrupt Enable\nShifter Error Flags\nShifter Status DMA Enable\nShifter Status Interrupt Enable\nShifter Status Flag\nCurrent State Pointer\nTimer Decrement\nTimer Disable\nTimer Enable\nTimer Output\nTimer Reset\nTimer Start Bit\nTimer Stop Bit\nDecrement counter on FlexIO clock, Shift clock equals …\nDecrement counter on Trigger input (both edges), Shift …\nDecrement counter on Pin input (both edges), Shift clock …\nDecrement counter on Trigger input (both edges), Shift …\nTimer never disabled\nTimer disabled on Timer N-1 disable\nTimer disabled on Timer compare (upper 8-bits match and …\nTimer disabled on Timer compare (upper 8-bits match and …\nTimer disabled on Pin rising or falling edge\nTimer disabled on Pin rising or falling edge provided …\nTimer disabled on Trigger falling edge\nTimer always enabled\nTimer enabled on Timer N-1 enable\nTimer enabled on Trigger high\nTimer enabled on Trigger high and Pin high\nTimer enabled on Pin rising edge\nTimer enabled on Pin rising edge and Trigger high\nTimer enabled on Trigger rising edge\nTimer enabled on Trigger rising or falling edge\nTimer output is logic one when enabled and is not affected …\nTimer output is logic zero when enabled and is not …\nTimer output is logic one when enabled and on timer reset\nTimer output is logic zero when enabled and on timer reset\nTimer never reset\nTimer reset on Timer Pin equal to Timer Output\nTimer reset on Timer Trigger equal to Timer Output\nTimer reset on Timer Pin rising edge\nTimer reset on Trigger rising edge\nTimer reset on Trigger rising or falling edge\nStart bit disabled\nStart bit enabled\nStop bit disabled\nStop bit is enabled on timer compare\nStop bit is enabled on timer disable\nStop bit is enabled on timer compare and timer disable\nTimer Compare Value\nTimer Pin Configuration\nTimer Pin Polarity\nTimer Pin Select\nTimer Mode\nTrigger Polarity\nTrigger Select\nTrigger Source\nTimer pin output disabled\nTimer pin open drain or bidirectional output enable\nTimer pin bidirectional output data\nTimer pin output\nPin is active high\nPin is active low\nTimer Disabled.\nDual 8-bit counters baud mode.\nDual 8-bit counters PWM high mode.\nSingle 16-bit counter mode.\nTrigger active high\nTrigger active low\nExternal trigger selected\nInternal trigger selected\nTimer Status Interrupt Enable\nTimer Status Flags\nFeature Specification Number\nMajor Version Number\nMinor Version Number\nStandard features implemented.\nSupports state, logic and parallel modes.\nDebug Enable\nDoze Enable\nFast Access\nFlexIO Enable\nSoftware Reset\nFlexIO is disabled in debug modes.\nFlexIO is enabled in debug modes\nFlexIO enabled in Doze modes.\nFlexIO disabled in Doze modes.\nConfigures for normal register accesses to FlexIO\nConfigures for fast register accesses to FlexIO\nFlexIO module is disabled.\nFlexIO module is enabled.\nSoftware reset is disabled\nSoftware reset is enabled, all FlexIO registers except the …\nPin Number\nShifter Number\nTimer Number\nTrigger Number\nPin Data Input\nShift Buffer\nShift Buffer\nShift Buffer\nShift Buffer\nShift Buffer\nShift Buffer\nShift Buffer\nInput Source\nParallel Width\nShifter Start bit\nShifter Stop bit\nPin\nShifter N+1 Output\nStart bit disabled for transmitter/receiver/match store, …\nStart bit disabled for transmitter/receiver/match store, …\nTransmitter outputs start bit value 0 before loading data …\nTransmitter outputs start bit value 1 before loading data …\nStop bit disabled for transmitter/receiver/match store\nTransmitter outputs stop bit value 0 on store, …\nTransmitter outputs stop bit value 1 on store, …\nShifter Pin Configuration\nShifter Pin Polarity\nShifter Pin Select\nShifter Mode\nTimer Polarity\nTimer Select\nShifter pin output disabled\nShifter pin open drain or bidirectional output enable\nShifter pin bidirectional output data\nShifter pin output\nPin is active high\nPin is active low\nDisabled.\nReceive mode. Captures the current Shifter content into …\nTransmit mode. Load SHIFTBUF contents into the Shifter on …\nMatch Store mode. Shifter data is compared to SHIFTBUF …\nMatch Continuous mode. Shifter data is continuously …\nState mode. SHIFTBUF contents are used for storing …\nLogic mode. SHIFTBUF contents are used for implementing …\nShift on posedge of Shift clock\nShift on negedge of Shift clock\nShifter Error Interrupt Enable\nShifter Error Flags\nShifter Status DMA Enable\nShifter Status Interrupt Enable\nShifter Status Flag\nCurrent State Pointer\nTimer Decrement\nTimer Disable\nTimer Enable\nTimer Output\nTimer Reset\nTimer Start Bit\nTimer Stop Bit\nDecrement counter on FlexIO clock, Shift clock equals …\nDecrement counter on Trigger input (both edges), Shift …\nDecrement counter on Pin input (both edges), Shift clock …\nDecrement counter on Trigger input (both edges), Shift …\nTimer never disabled\nTimer disabled on Timer N-1 disable\nTimer disabled on Timer compare (upper 8-bits match and …\nTimer disabled on Timer compare (upper 8-bits match and …\nTimer disabled on Pin rising or falling edge\nTimer disabled on Pin rising or falling edge provided …\nTimer disabled on Trigger falling edge\nTimer always enabled\nTimer enabled on Timer N-1 enable\nTimer enabled on Trigger high\nTimer enabled on Trigger high and Pin high\nTimer enabled on Pin rising edge\nTimer enabled on Pin rising edge and Trigger high\nTimer enabled on Trigger rising edge\nTimer enabled on Trigger rising or falling edge\nTimer output is logic one when enabled and is not affected …\nTimer output is logic zero when enabled and is not …\nTimer output is logic one when enabled and on timer reset\nTimer output is logic zero when enabled and on timer reset\nTimer never reset\nTimer reset on Timer Pin equal to Timer Output\nTimer reset on Timer Trigger equal to Timer Output\nTimer reset on Timer Pin rising edge\nTimer reset on Trigger rising edge\nTimer reset on Trigger rising or falling edge\nStart bit disabled\nStart bit enabled\nStop bit disabled\nStop bit is enabled on timer compare\nStop bit is enabled on timer disable\nStop bit is enabled on timer compare and timer disable\nTimer Compare Value\nTimer Pin Configuration\nTimer Pin Polarity\nTimer Pin Select\nTimer Mode\nTrigger Polarity\nTrigger Select\nTrigger Source\nTimer pin output disabled\nTimer pin open drain or bidirectional output enable\nTimer pin bidirectional output data\nTimer pin output\nPin is active high\nPin is active low\nTimer Disabled.\nDual 8-bit counters baud mode.\nDual 8-bit counters PWM high mode.\nSingle 16-bit counter mode.\nTrigger active high\nTrigger active low\nExternal trigger selected\nInternal trigger selected\nTimer Status Interrupt Enable\nTimer Status Flags\nFeature Specification Number\nMajor Version Number\nMinor Version Number\nStandard features implemented.\nSupports state, logic and parallel modes.\nDTCM Magic Address Register\nDTCM Magic Address Register\nFLEXRAM\nInterrupt Enable Register\nInterrupt Enable Register\nInterrupt Status Register\nInterrupt Status Register\nInterrupt Status Enable Register\nInterrupt Status Enable Register\nITCM Magic Address Register\nITCM Magic Address Register\nOCRAM Magic Address Register\nOCRAM Magic Address Register\nFLEXRAM\nTCM CRTL Register\nTCM CRTL Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDTCM Magic Address\nDTCM Write Read Select\nWhen DTCM read access hits magic address, it will generate …\nWhen DTCM write access hits magic address, it will …\nDTCM Access Error Interrupt Enable\nDTCM Magic Address Match Interrupt Enable\nITCM Access Error Interrupt Enable\nITCM Magic Address Match Interrupt Enable\nOCRAM Access Error Interrupt Enable\nOCRAM Magic Address Match Interrupt Enable\nMasked\nEnabled\nMasked\nEnabled\nMasked\nEnabled\nMasked\nEnabled\nMasked\nEnabled\nMasked\nEnabled\nDTCM Access Error Status\nDTCM Magic Address Match Status\nITCM Access Error Status\nITCM Magic Address Match Status\nOCRAM Access Error Status\nOCRAM Magic Address Match Status\nDTCM access error does not happen\nDTCM access error happens.\nDTCM did not access magic address.\nDTCM accessed magic address.\nITCM access error does not happen\nITCM access error happens.\nITCM did not access magic address.\nITCM accessed magic address.\nOCRAM access error does not happen\nOCRAM access error happens.\nOCRAM did not access magic address.\nOCRAM accessed magic address.\nDTCM Access Error Status Enable\nDTCM Magic Address Match Status Enable\nITCM Access Error Status Enable\nITCM Magic Address Match Status Enable\nOCRAM Access Error Status Enable\nOCRAM Magic Address Match Status Enable\nMasked\nEnabled\nMasked\nEnabled\nMasked\nEnabled\nMasked\nEnabled\nMasked\nEnabled\nMasked\nEnabled\nITCM Magic Address\nITCM Write Read Select\nWhen ITCM read access hits magic address, it will generate …\nWhen ITCM write access hits magic address, it will …\nOCRAM Magic Address\nOCRAM Write Read Select\nWhen OCRAM read access hits magic address, it will …\nWhen OCRAM write access hits magic address, it will …\nForce RAM Clock Always On\nTCM Read Wait Mode Enable\nTCM Write Wait Mode Enable\nTCM read fast mode: Read RAM accesses are expected to be …\nTCM read wait mode: Read RAM accesses are expected to be …\nTCM write fast mode: Write RAM accesses are expected to be …\nTCM write wait mode: Write RAM accesses are expected to be …\nAHB Bus Control Register\nAHB Bus Control Register\nAHB RX Buffer 0 Control Register 0\nAHB RX Buffer 0 Control Register 0\nAHB RX Buffer 1 Control Register 0\nAHB RX Buffer 1 Control Register 0\nAHB RX Buffer 2 Control Register 0\nAHB RX Buffer 2 Control Register 0\nAHB RX Buffer 3 Control Register 0\nAHB RX Buffer 3 Control Register 0\nAHB Suspend Status Register\nAHB Suspend Status Register\nDLL Control Register 0\nDLL Control Register 0\nFlexSPI\nFlash Control Register 0\nFlash Control Register 0\nFlash Control Register 0\nFlash Control Register 0\nFlash Control Register 0\nFlash Control Register 0\nFlash Control Register 0\nFlash Control Register 0\nFlash Control Register 1\nFlash Control Register 1\nFlash Control Register 2\nFlash Control Register 2\nFlash Control Register 4\nFlash Control Register 4\nInterrupt Enable Register\nInterrupt Enable Register\nInterrupt Register\nInterrupt Register\nIP Command Register\nIP Command Register\nIP Control Register 0\nIP Control Register 0\nIP Control Register 1\nIP Control Register 1\nIP RX FIFO Control Register\nIP RX FIFO Control Register\nIP RX FIFO Status Register\nIP RX FIFO Status Register\nIP TX FIFO Control Register\nIP TX FIFO Control Register\nIP TX FIFO Status Register\nIP TX FIFO Status Register\nLUT 0\nLUT 0\nLUT Control Register\nLUT Control Register\nLUT Key Register\nLUT Key Register\nModule Control Register 0\nModule Control Register 0\nModule Control Register 1\nModule Control Register 1\nModule Control Register 2\nModule Control Register 2\nIP RX FIFO Data Register 0\nIP RX FIFO Data Register 0\nFlexSPI\nStatus Register 0\nStatus Register 0\nStatus Register 1\nStatus Register 1\nStatus Register 2\nStatus Register 2\nIP TX FIFO Data Register 0\nIP TX FIFO Data Register 0\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nParallel mode enabled for AHB triggered Command (both read …\nEnable AHB bus bufferable write access support. This field …\nEnable AHB bus cachable read access support.\nClear the status/pointers of AHB RX Buffer. Auto-cleared.\nClear the status/pointers of AHB TX Buffer. Auto-cleared.\nAHB Read Prefetch Enable.\nAHB Read Address option bit. This option bit is intend to …\nAHB Read Size Alignment\nFlash will be accessed in Individual mode.\nFlash will be accessed in Parallel mode.\nDisabled. For all AHB write access (no matter bufferable …\nEnabled. For AHB bufferable write access, FlexSPI will …\nDisabled. When there is AHB bus cachable read access, …\nEnabled. When there is AHB bus cachable read access, …\nThere is AHB read burst start address alignment limitation …\nThere is no AHB read burst start address alignment …\nAHB read size will be decided by other register setting …\nAHB read size to up size to 8 bytes aligned, no prefetching\nAHB RX Buffer Size in 64 bits.\nThis AHB RX Buffer is assigned according to AHB Master …\nAHB Read Prefetch Enable for current AHB RX Buffer …\nThis priority for AHB Master Read which this AHB RX Buffer …\nAHB RX Buffer Size in 64 bits.\nThis AHB RX Buffer is assigned according to AHB Master …\nAHB Read Prefetch Enable for current AHB RX Buffer …\nThis priority for AHB Master Read which this AHB RX Buffer …\nAHB RX Buffer Size in 64 bits.\nThis AHB RX Buffer is assigned according to AHB Master …\nAHB Read Prefetch Enable for current AHB RX Buffer …\nThis priority for AHB Master Read which this AHB RX Buffer …\nAHB RX Buffer Size in 64 bits.\nThis AHB RX Buffer is assigned according to AHB Master …\nAHB Read Prefetch Enable for current AHB RX Buffer …\nThis priority for AHB Master Read which this AHB RX Buffer …\nIndicates if an AHB read prefetch command sequence has …\nAHB RX BUF ID for suspended command sequence.\nLeft Data size for suspended command sequence (in byte).\nDLL calibration enable.\nSoftware could force a reset on DLL by setting this field …\nSlave clock delay line delay cell number selection …\nSlave clock delay line delay cell number selection …\nThe delay target for slave delay line is: …\nFlash Size in KByte.\nFlash Size in KByte.\nFlash Size in KByte.\nFlash Size in KByte.\nColumn Address Size.\nThis field is used to set the minimum interval between …\nCS interval unit\nSerial Flash CS Hold time.\nSerial Flash CS setup time.\nWord Addressable.\nThe CS interval unit is 1 serial clock cycle\nThe CS interval unit is 256 serial clock cycle\nSequence Index for AHB Read triggered Command in LUT.\nSequence Number for AHB Read triggered Command in LUT.\nSequence Index for AHB Write triggered Command.\nSequence Number for AHB Write triggered Command.\nFor certain devices (such as FPGA), it need some time to …\nAWRWAIT unit\nClear the instruction pointer which is internally saved …\nThe AWRWAIT unit is 2 ahb clock cycle\nThe AWRWAIT unit is 8 ahb clock cycle\nThe AWRWAIT unit is 32 ahb clock cycle\nThe AWRWAIT unit is 128 ahb clock cycle\nThe AWRWAIT unit is 512 ahb clock cycle\nThe AWRWAIT unit is 2048 ahb clock cycle\nThe AWRWAIT unit is 8192 ahb clock cycle\nThe AWRWAIT unit is 32768 ahb clock cycle\nWrite mask enable bit for flash device on port A. When …\nWrite mask enable bit for flash device on port B. When …\nWrite mask option bit 1. This option bit could be used to …\nWrite mask is disabled, DQS(RWDS) pin will be un-driven …\nWrite mask is enabled, DQS(RWDS) pin will be driven by …\nWrite mask is disabled, DQS(RWDS) pin will be un-driven …\nWrite mask is enabled, DQS(RWDS) pin will be driven by …\nDQS pin will be used as Write Mask when writing to …\nDQS pin will not be used as Write Mask when writing to …\nAHB Bus error interrupt enable.Refer Interrupts chapter …\nAHB triggered Command Sequences Error Detected interrupt …\nAHB triggered Command Sequences Grant Timeout interrupt …\nIP triggered Command Sequences Execution finished …\nIP triggered Command Sequences Error Detected interrupt …\nIP triggered Command Sequences Grant Timeout interrupt …\nIP RX FIFO WaterMark available interrupt enable.\nIP TX FIFO WaterMark empty interrupt enable.\nOTFAD key blob processing done interrupt enable.Refer …\nOTFAD key blob processing error interrupt enable.Refer …\nSCLK is stopped during command sequence because Async RX …\nSCLK is stopped during command sequence because Async TX …\nSequence execution timeout interrupt enable.Refer …\nAHB Bus timeout or AHB bus illegal access Flash during …\nAHB triggered Command Sequences Error Detected interrupt. …\nAHB triggered Command Sequences Grant Timeout interrupt.\nIP triggered Command Sequences Execution finished …\nIP triggered Command Sequences Error Detected interrupt. …\nIP triggered Command Sequences Grant Timeout interrupt.\nIP RX FIFO watermark available interrupt.\nIP TX FIFO watermark empty interrupt.\nOTFAD key blob processing done interrupt.\nOTFAD key blob processing error interrupt.\nSCLK is stopped during command sequence because Async RX …\nSCLK is stopped during command sequence because Async TX …\nSequence execution timeout interrupt.\nSetting this bit will trigger an IP Command.\nSerial Flash Address for IP command.\nFlash Read/Program Data Size (in Bytes) for IP command.\nParallel mode Enabled for IP command.\nSequence Index in LUT for IP command.\nSequence Number for IP command: ISEQNUM+1.\nFlash will be accessed in Individual mode.\nFlash will be accessed in Parallel mode.\nClear all valid data entries in IP RX FIFO.\nIP RX FIFO reading by DMA enabled.\nWatermark level is (RXWMRK+1)*64 Bits.\nIP RX FIFO would be read by processor.\nIP RX FIFO would be read by DMA.\nFill level of IP RX FIFO.\nTotal Read Data Counter: RDCNTR * 64 Bits.\nClear all valid data entries in IP TX FIFO.\nIP TX FIFO filling by DMA enabled.\nWatermark level is (TXWMRK+1)*64 Bits.\nIP TX FIFO would be filled by processor.\nIP TX FIFO would be filled by DMA.\nFill level of IP TX FIFO.\nTotal Write Data Counter: WRCNTR * 64 Bits.\nNUM_PADS0\nNUM_PADS1\nOPCODE\nOPCODE1\nOPERAND0\nOPERAND1\nLock LUT\nUnlock LUT\nThe Key to lock or unlock LUT.\nTimeout wait cycle for AHB command grant.\nEnable AHB bus Read Access to IP RX FIFO.\nEnable AHB bus Write Access to IP TX FIFO.\nThis bit is to support Flash Octal mode access by …\nDoze mode enable bit\nHalf Speed Serial Flash access Enable.\nTime out wait cycle for IP command grant.\nModule Disable\nSample Clock source selection for Flash Reading\nThis bit is used to force SCLK output free-running. For …\nThe serial root clock could be divided inside FlexSPI . …\nSoftware Reset\nIP RX FIFO should be read by IP Bus. AHB Bus read access …\nIP RX FIFO should be read by AHB Bus. IP Bus read access …\nIP TX FIFO should be written by IP Bus. AHB Bus write …\nIP TX FIFO should be written by AHB Bus. IP Bus write …\nDisable.\nEnable.\nDoze mode support disabled. AHB clock and serial clock …\nDoze mode support enabled. AHB clock and serial clock will …\nDisable divide by 2 of serial flash clock for half speed …\nEnable divide by 2 of serial flash clock for half speed …\nDummy Read strobe generated by FlexSPI Controller and …\nDummy Read strobe generated by FlexSPI Controller and …\nFlash provided Read strobe and input from DQS pad\nDisable.\nEnable.\nDivided by 1\nDivided by 2\nDivided by 3\nDivided by 4\nDivided by 5\nDivided by 6\nDivided by 7\nDivided by 8\nAHB Read/Write access to Serial Flash Memory space will …\nCommand Sequence Execution will timeout and abort after …\nThis bit determines whether AHB RX Buffer and AHB TX …\nThe sampling clock phase selection will be reset to phase …\nWait cycle (in AHB clock cycle) for idle state before …\nAll external devices are same devices (both in types and …\nB_SCLK pad can be used as A_SCLK differential clock output …\nAHB RX/TX Buffer will not be cleaned automatically when …\nAHB RX/TX Buffer will be cleaned automatically when …\nIn Individual mode, …\nFLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be …\nB_SCLK pad is used as port B SCLK clock output. Port B …\nB_SCLK pad is used as port A SCLK inverted clock output …\nRX Data\nThis status field indicates the trigger source of current …\nThis status bit indicates the state machine in ARB_CTL is …\nThis status bit indicates the state machine in SEQ_CTL is …\nTriggered by AHB read command (triggered by AHB read).\nTriggered by AHB write command (triggered by AHB Write).\nTriggered by IP command (triggered by setting register bit …\nTriggered by suspended command (resumed).\nIndicates the Error Code when AHB command Error detected. …\nIndicates the sequence index when an AHB command error is …\nIndicates the Error Code when IP command Error detected. …\nIndicates the sequence Index when IP command error …\nNo error.\nSequence execution timeout.\nAHB Write command with JMP_ON_CS instruction used in the …\nThere is unknown instruction opcode in the sequence.\nInstruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.\nInstruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.\nNo error.\nSequence execution timeout.\nFlash boundary crossed.\nIP command with JMP_ON_CS instruction used in the sequence.\nThere is unknown instruction opcode in the sequence.\nInstruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.\nInstruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.\nFlash access start address exceed the whole flash address …\nFlash A sample clock reference delay line locked.\nFlash A sample clock reference delay line delay cell …\nFlash A sample clock slave delay line locked.\nFlash A sample clock slave delay line delay cell number …\nFlash B sample clock reference delay line locked.\nFlash B sample clock reference delay line delay cell …\nFlash B sample clock slave delay line locked.\nFlash B sample clock slave delay line delay cell number …\nTX Data\nGPC Interface control register\nGPC Interface control register\nGPC\nIRQ masking register 1\nIRQ masking register 1\nIRQ masking register 2\nIRQ masking register 2\nIRQ masking register 3\nIRQ masking register 3\nIRQ masking register 4\nIRQ masking register 4\nIRQ masking register 5\nIRQ masking register 5\nIRQ status resister 1\nIRQ status resister 1\nIRQ status resister 2\nIRQ status resister 2\nIRQ status resister 3\nIRQ status resister 3\nIRQ status resister 4\nIRQ status resister 4\nIRQ status resister 5\nIRQ status resister 5\nGPC\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nMEGA domain power down request\nMEGA domain power up request\nFlexRAM PDRAM0 Power Gate Enable\nNo Request\nRequest power down sequence\nNo Request\nRequest power up sequence\nFlexRAM PDRAM0 domain will keep power even if the CPU core …\nFlexRAM PDRAM0 domain will be powered down when the CPU …\nIRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked\nIRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked\nIRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked\nIRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked\nIRQ[159:128] masking bits: 1-irq masked, 0-irq is not …\nIRQ[31:0] status, read only\nIRQ[63:32] status, read only\nIRQ[95:64] status, read only\nIRQ[127:96] status, read only\nIRQ[159:128] status, read only\nGPIO data register\nGPIO data register\nGPIO data register CLEAR\nGPIO data register CLEAR\nGPIO data register SET\nGPIO data register SET\nGPIO data register TOGGLE\nGPIO data register TOGGLE\nGPIO edge select register\nGPIO edge select register\nGPIO direction register\nGPIO direction register\nGPIO\nGPIO\nGPIO\nGPIO interrupt configuration register1\nGPIO interrupt configuration register1\nGPIO interrupt configuration register2\nGPIO interrupt configuration register2\nGPIO interrupt mask register\nGPIO interrupt mask register\nGPIO interrupt status register\nGPIO interrupt status register\nGPIO pad status register\nGPIO pad status register\nGPIO\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDR\nDR_CLEAR\nDR_SET\nDR_TOGGLE\nGPIO_EDGE_SEL\nGDIR\nICR0\nICR1\nICR10\nICR11\nICR12\nICR13\nICR14\nICR15\nICR2\nICR3\nICR4\nICR5\nICR6\nICR7\nICR8\nICR9\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nICR16\nICR17\nICR18\nICR19\nICR20\nICR21\nICR22\nICR23\nICR24\nICR25\nICR26\nICR27\nICR28\nICR29\nICR30\nICR31\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nInterrupt n is falling-edge sensitive.\nInterrupt n is high-level sensitive.\nInterrupt n is low-level sensitive.\nInterrupt n is rising-edge sensitive.\nIMR\nISR\nPSR\nGPT Counter Register\nGPT Counter Register\nGPT Control Register\nGPT Control Register\nGPT\nGPT\nGPT Input Capture Register 1\nGPT Input Capture Register 1\nGPT Interrupt Register\nGPT Interrupt Register\nGPT Output Compare Register 1\nGPT Output Compare Register 1\nGPT Prescaler Register\nGPT Prescaler Register\nGPT\nGPT Status Register\nGPT Status Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nCounter Value. The COUNT bits show the current count value …\nClock Source select\nGPT debug mode enable\nGPT Doze Mode Enable\nGPT Enable\nGPT Enable mode\nEnable 24 MHz clock input from crystal\nSee F03\nSee F03\nFO3 Force Output Compare Channel 3 FO2 Force Output …\nFree-Run or Restart mode\nSee IM2\nIM2 (bits 19-18, Input Capture Channel 2 operating mode) …\nSee OM3\nSee OM3\nOM3 (bits 28-26) controls the Output Compare Channel 3 …\nGPT Stop Mode enable\nSoftware reset\nGPT Wait Mode enable\nNo clock\nPeripheral Clock (ipg_clk)\nHigh Frequency Reference Clock (ipg_clk_highfreq)\nExternal Clock\nLow Frequency Reference Clock (ipg_clk_32k)\nCrystal oscillator as Reference Clock (ipg_clk_24M)\nGPT is disabled in debug mode.\nGPT is enabled in debug mode.\nGPT is disabled in doze mode.\nGPT is enabled in doze mode.\nGPT is disabled.\nGPT is enabled.\nGPT counter will retain its value when it is disabled.\nGPT counter value is reset to 0 when it is disabled.\n24M clock disabled\n24M clock enabled\nRestart mode\nFree-Run mode\nGPT is disabled in Stop mode.\nGPT is enabled in Stop mode.\nGPT is not in reset state\nGPT is in reset state\nGPT is disabled in wait mode.\nGPT is enabled in wait mode.\nCapture Value\nSee IF2IE\nIF2IE Input capture 2 Interrupt Enable IF1IE Input capture …\nSee OF3IE\nSee OF3IE\nOF3IE Output Compare 3 Interrupt Enable OF2IE Output …\nRollover Interrupt Enable. The ROVIE bit controls the …\nRollover interrupt is disabled.\nRollover interrupt enabled.\nCompare Value\nPrescaler bits\nPrescaler bits\nDivide by 1\nDivide by 2\nDivide by 16\nDivide by 1\nDivide by 2\nDivide by 4096\nSee IF2\nIF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn …\nSee OF3\nSee OF3\nOF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 …\nRollover Flag\nRollover has not occurred.\nRollover has occurred.\nFLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register\nFLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register\nFLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register\nFLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register\nFLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register\nFLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register\nFLEXPWM1_PWMA_SELECT_INPUT_3 DAISY Register\nFLEXPWM1_PWMA_SELECT_INPUT_3 DAISY Register\nFLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register\nFLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register\nFLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register\nFLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register\nFLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register\nFLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register\nFLEXPWM1_PWMB_SELECT_INPUT_3 DAISY Register\nFLEXPWM1_PWMB_SELECT_INPUT_3 DAISY Register\nFLEXSPI_DQS_FA_SELECT_INPUT DAISY Register\nFLEXSPI_DQS_FA_SELECT_INPUT DAISY Register\nFLEXSPI_DQS_FB_SELECT_INPUT DAISY Register\nFLEXSPI_DQS_FB_SELECT_INPUT DAISY Register\nIOMUXC\nKPP_COL_SELECT_INPUT_0 DAISY Register\nKPP_COL_SELECT_INPUT_0 DAISY Register\nKPP_COL_SELECT_INPUT_1 DAISY Register\nKPP_COL_SELECT_INPUT_1 DAISY Register\nKPP_COL_SELECT_INPUT_2 DAISY Register\nKPP_COL_SELECT_INPUT_2 DAISY Register\nKPP_COL_SELECT_INPUT_3 DAISY Register\nKPP_COL_SELECT_INPUT_3 DAISY Register\nKPP_ROW_SELECT_INPUT_0 DAISY Register\nKPP_ROW_SELECT_INPUT_0 DAISY Register\nKPP_ROW_SELECT_INPUT_1 DAISY Register\nKPP_ROW_SELECT_INPUT_1 DAISY Register\nKPP_ROW_SELECT_INPUT_2 DAISY Register\nKPP_ROW_SELECT_INPUT_2 DAISY Register\nKPP_ROW_SELECT_INPUT_3 DAISY Register\nKPP_ROW_SELECT_INPUT_3 DAISY Register\nLPI2C1_HREQ_SELECT_INPUT DAISY Register\nLPI2C1_HREQ_SELECT_INPUT DAISY Register\nLPI2C1_SCL_SELECT_INPUT DAISY Register\nLPI2C1_SCL_SELECT_INPUT DAISY Register\nLPI2C1_SDA_SELECT_INPUT DAISY Register\nLPI2C1_SDA_SELECT_INPUT DAISY Register\nLPI2C2_SCL_SELECT_INPUT DAISY Register\nLPI2C2_SCL_SELECT_INPUT DAISY Register\nLPI2C2_SDA_SELECT_INPUT DAISY Register\nLPI2C2_SDA_SELECT_INPUT DAISY Register\nLPSPI1_PCS_SELECT_INPUT_0 DAISY Register\nLPSPI1_PCS_SELECT_INPUT_0 DAISY Register\nLPSPI1_SCK_SELECT_INPUT DAISY Register\nLPSPI1_SCK_SELECT_INPUT DAISY Register\nLPSPI1_SDI_SELECT_INPUT DAISY Register\nLPSPI1_SDI_SELECT_INPUT DAISY Register\nLPSPI1_SDO_SELECT_INPUT DAISY Register\nLPSPI1_SDO_SELECT_INPUT DAISY Register\nLPSPI2_PCS_SELECT_INPUT_0 DAISY Register\nLPSPI2_PCS_SELECT_INPUT_0 DAISY Register\nLPSPI2_SCK_SELECT_INPUT DAISY Register\nLPSPI2_SCK_SELECT_INPUT DAISY Register\nLPSPI2_SDI_SELECT_INPUT DAISY Register\nLPSPI2_SDI_SELECT_INPUT DAISY Register\nLPSPI2_SDO_SELECT_INPUT DAISY Register\nLPSPI2_SDO_SELECT_INPUT DAISY Register\nLPUART1_RXD_SELECT_INPUT DAISY Register\nLPUART1_RXD_SELECT_INPUT DAISY Register\nLPUART1_TXD_SELECT_INPUT DAISY Register\nLPUART1_TXD_SELECT_INPUT DAISY Register\nLPUART2_RXD_SELECT_INPUT DAISY Register\nLPUART2_RXD_SELECT_INPUT DAISY Register\nLPUART2_TXD_SELECT_INPUT DAISY Register\nLPUART2_TXD_SELECT_INPUT DAISY Register\nLPUART3_RXD_SELECT_INPUT DAISY Register\nLPUART3_RXD_SELECT_INPUT DAISY Register\nLPUART3_TXD_SELECT_INPUT DAISY Register\nLPUART3_TXD_SELECT_INPUT DAISY Register\nLPUART4_RXD_SELECT_INPUT DAISY Register\nLPUART4_RXD_SELECT_INPUT DAISY Register\nLPUART4_TXD_SELECT_INPUT DAISY Register\nLPUART4_TXD_SELECT_INPUT DAISY Register\nNMI_GLUE_NMI_SELECT_INPUT DAISY Register\nNMI_GLUE_NMI_SELECT_INPUT DAISY Register\nIOMUXC\nSPDIF_IN1_SELECT_INPUT DAISY Register\nSPDIF_IN1_SELECT_INPUT DAISY Register\nSPDIF_TX_CLK2_SELECT_INPUT DAISY Register\nSPDIF_TX_CLK2_SELECT_INPUT DAISY Register\nSW_MUX_CTL_PAD_GPIO_00 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_00 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_01 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_01 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_02 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_02 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_03 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_03 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_05 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_05 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_06 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_06 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_07 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_07 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_08 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_08 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_09 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_09 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_10 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_10 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_11 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_11 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_12 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_12 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_13 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_13 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_00 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_00 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_01 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_01 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_02 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_02 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_03 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_03 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_04 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_04 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_05 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_05 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_06 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_06 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_07 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_07 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_08 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_08 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_09 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_09 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_11 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_11 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_12 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_12 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_13 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_13 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_14 SW MUX Control Register\nSW_MUX_CTL_PAD_GPIO_SD_14 SW MUX Control Register\nSW_PAD_CTL_PAD_GPIO_00 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_00 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_01 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_01 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_02 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_02 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_03 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_03 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_04 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_04 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_05 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_05 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_06 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_06 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_07 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_07 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_08 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_08 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_09 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_09 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_10 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_10 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_11 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_11 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_12 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_12 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_13 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_13 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_00 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_00 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_01 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_01 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_02 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_02 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_03 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_03 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_04 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_04 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_05 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_05 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_06 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_06 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_07 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_07 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_08 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_08 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_09 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_09 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_10 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_10 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_11 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_11 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_12 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_12 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_13 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_13 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_14 SW PAD Control Register\nSW_PAD_CTL_PAD_GPIO_SD_14 SW PAD Control Register\nUSB_OTG_ID_SELECT_INPUT DAISY Register\nUSB_OTG_ID_SELECT_INPUT DAISY Register\nUSB_OTG_OC_SELECT_INPUT DAISY Register\nUSB_OTG_OC_SELECT_INPUT DAISY Register\nXEV_GLUE_RXEV_SELECT_INPUT DAISY Register\nXEV_GLUE_RXEV_SELECT_INPUT DAISY Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_02 for Mode: ALT2\nSelecting Pad: GPIO_SD_02 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_04 for Mode: ALT2\nSelecting Pad: GPIO_SD_04 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_06 for Mode: ALT2\nSelecting Pad: GPIO_AD_04 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_08 for Mode: ALT2\nSelecting Pad: GPIO_AD_06 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_01 for Mode: ALT2\nSelecting Pad: GPIO_SD_01 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_03 for Mode: ALT2\nSelecting Pad: GPIO_SD_03 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_05 for Mode: ALT2\nSelecting Pad: GPIO_AD_03 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_07 for Mode: ALT2\nSelecting Pad: GPIO_AD_05 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_SD_12 for Mode: ALT0\nSelecting Pad: GPIO_SD_14 for Mode: ALT0\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_00 for Mode: ALT0\nSelecting Pad: GPIO_SD_14 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_12 for Mode: ALT2\nSelecting Pad: GPIO_AD_14 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_06 for Mode: ALT3\nSelecting Pad: GPIO_AD_12 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_04 for Mode: ALT3\nSelecting Pad: GPIO_AD_10 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_02 for Mode: ALT4\nSelecting Pad: GPIO_AD_00 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_11 for Mode: ALT2\nSelecting Pad: GPIO_AD_13 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_05 for Mode: ALT3\nSelecting Pad: GPIO_AD_11 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_03 for Mode: ALT3\nSelecting Pad: GPIO_AD_09 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_01 for Mode: ALT4\nSelecting Pad: GPIO_13 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_10 for Mode: ALT1\nSelecting Pad: GPIO_AD_06 for Mode: ALT6\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_02 for Mode: ALT3\nSelecting Pad: GPIO_12 for Mode: ALT1\nSelecting Pad: GPIO_AD_14 for Mode: ALT0\nSelecting Pad: GPIO_SD_06 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_01 for Mode: ALT3\nSelecting Pad: GPIO_11 for Mode: ALT1\nSelecting Pad: GPIO_AD_13 for Mode: ALT0\nSelecting Pad: GPIO_SD_05 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_10 for Mode: ALT3\nSelecting Pad: GPIO_AD_02 for Mode: ALT3\nSelecting Pad: GPIO_AD_08 for Mode: ALT0\nSelecting Pad: GPIO_SD_08 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_09 for Mode: ALT3\nSelecting Pad: GPIO_AD_01 for Mode: ALT3\nSelecting Pad: GPIO_AD_07 for Mode: ALT0\nSelecting Pad: GPIO_SD_07 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_05 for Mode: ALT0\nSelecting Pad: GPIO_SD_07 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_06 for Mode: ALT0\nSelecting Pad: GPIO_SD_08 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_03 for Mode: ALT0\nSelecting Pad: GPIO_SD_05 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_04 for Mode: ALT0\nSelecting Pad: GPIO_SD_06 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_11 for Mode: ALT0\nSelecting Pad: GPIO_SD_12 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_12 for Mode: ALT0\nSelecting Pad: GPIO_SD_11 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_09 for Mode: ALT0\nSelecting Pad: GPIO_SD_09 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_10 for Mode: ALT0\nSelecting Pad: GPIO_SD_10 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_09 for Mode: ALT0\nSelecting Pad: GPIO_SD_11 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_10 for Mode: ALT0\nSelecting Pad: GPIO_SD_12 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_13 for Mode: ALT0\nSelecting Pad: GPIO_SD_09 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_00 for Mode: ALT0\nSelecting Pad: GPIO_SD_10 for Mode: ALT2\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_07 for Mode: ALT3\nSelecting Pad: GPIO_11 for Mode: ALT0\nSelecting Pad: GPIO_AD_07 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_08 for Mode: ALT3\nSelecting Pad: GPIO_12 for Mode: ALT0\nSelecting Pad: GPIO_AD_08 for Mode: ALT1\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_05 for Mode: ALT3\nSelecting Pad: GPIO_AD_01 for Mode: ALT0\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_06 for Mode: ALT3\nSelecting Pad: GPIO_AD_02 for Mode: ALT0\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_00 for Mode: ALT6\nSelecting Pad: GPIO_AD_13 for Mode: ALT6\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_04 for Mode: ALT4\nSelecting Pad: GPIO_10 for Mode: ALT6\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_06 for Mode: ALT4\nSelecting Pad: GPIO_12 for Mode: ALT6\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_B_DQS of instance: …\nSelect mux mode: ALT1 mux port: SAI3_MCLK of instance: SAI3\nSelect mux mode: ALT2 mux port: LPSPI2_PCS3 of instance: …\nSelect mux mode: ALT3 mux port: LPSPI1_PCS3 of instance: …\nSelect mux mode: ALT4 mux port: PIT_TRIGGER00 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO00 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_00\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SAI1_RX_BCLK of instance: …\nSelect mux mode: ALT1 mux port: WDOG1_ANY of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM0_B of …\nSelect mux mode: ALT3 mux port: LPI2C1_SDA of instance: …\nSelect mux mode: ALT4 mux port: KPP_ROW03 of instance: KPP\nSelect mux mode: ALT5 mux port: GPIOMUX_IO01 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_01\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SAI1_RX_SYNC of instance: …\nSelect mux mode: ALT1 mux port: WDOG2_B of instance: WDOG2\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM0_A of …\nSelect mux mode: ALT3 mux port: LPI2C1_SCL of instance: …\nSelect mux mode: ALT4 mux port: KPP_COL03 of instance: KPP\nSelect mux mode: ALT5 mux port: GPIOMUX_IO02 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_02\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SAI1_RX_DATA00 of …\nSelect mux mode: ALT1 mux port: GPT1_COMPARE3 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM1_B of …\nSelect mux mode: ALT4 mux port: SPDIF_SR_CLK of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO03 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_03\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SAI1_TX_DATA00 of …\nSelect mux mode: ALT1 mux port: GPT1_CAPTURE2 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of …\nSelect mux mode: ALT4 mux port: SPDIF_IN of instance: SPDIF\nSelect mux mode: ALT5 mux port: GPIOMUX_IO04 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_04\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SAI1_TX_DATA01 of …\nSelect mux mode: ALT1 mux port: GPT1_COMPARE2 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM2_B of …\nSelect mux mode: ALT3 mux port: LPUART4_RXD of instance: …\nSelect mux mode: ALT4 mux port: SPDIF_OUT of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO05 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_05\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SAI1_TX_BCLK of instance: …\nSelect mux mode: ALT1 mux port: GPT1_CAPTURE1 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM2_A of …\nSelect mux mode: ALT3 mux port: LPUART4_TXD of instance: …\nSelect mux mode: ALT4 mux port: SPDIF_EXT_CLK of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO06 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_06\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SAI1_TX_SYNC of instance: …\nSelect mux mode: ALT1 mux port: GPT1_COMPARE1 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of …\nSelect mux mode: ALT3 mux port: LPUART3_RXD of instance: …\nSelect mux mode: ALT4 mux port: SPDIF_LOCK of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO07 of instance: …\nSelect mux mode: ALT6 mux port: LPUART1_RTS_B of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_07\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SAI1_MCLK of instance: SAI1\nSelect mux mode: ALT1 mux port: GPT1_CLK of instance: GPT1\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of …\nSelect mux mode: ALT3 mux port: LPUART3_TXD of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO00 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO08 of instance: …\nSelect mux mode: ALT6 mux port: LPUART1_CTS_B of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_08\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPUART1_RXD of instance: …\nSelect mux mode: ALT1 mux port: WDOG1_B of instance: WDOG1\nSelect mux mode: ALT2 mux port: FLEXSPI_A_SS1_B of …\nSelect mux mode: ALT3 mux port: LPI2C2_SDA of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO01 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO09 of instance: …\nSelect mux mode: ALT6 mux port: SPDIF_SR_CLK of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_09\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPUART1_TXD of instance: …\nSelect mux mode: ALT1 mux port: LPI2C1_HREQ of instance: …\nSelect mux mode: ALT2 mux port: EWM_OUT_B of instance: EWM\nSelect mux mode: ALT3 mux port: LPI2C2_SCL of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO02 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO10 of instance: …\nSelect mux mode: ALT6 mux port: SPDIF_IN of instance: SPDIF\nInput Path is determined by functionality\nForce input path of pad GPIO_10\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPUART3_RXD of instance: …\nSelect mux mode: ALT1 mux port: LPI2C1_SDA of instance: …\nSelect mux mode: ALT2 mux port: KPP_ROW00 of instance: KPP\nSelect mux mode: ALT3 mux port: FLEXSPI_B_SS1_B of …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO03 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO11 of instance: …\nSelect mux mode: ALT6 mux port: SPDIF_OUT of instance: …\nSelect mux mode: ALT7 mux port: ARM_CM7_TRACE03 of …\nInput Path is determined by functionality\nForce input path of pad GPIO_11\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPUART3_TXD of instance: …\nSelect mux mode: ALT1 mux port: LPI2C1_SCL of instance: …\nSelect mux mode: ALT2 mux port: KPP_COL00 of instance: KPP\nSelect mux mode: ALT3 mux port: USB_OTG1_OC of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO04 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO12 of instance: …\nSelect mux mode: ALT6 mux port: SPDIF_EXT_CLK of instance: …\nSelect mux mode: ALT7 mux port: ARM_CM7_TRACE02 of …\nInput Path is determined by functionality\nForce input path of pad GPIO_12\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPUART2_RXD of instance: …\nSelect mux mode: ALT1 mux port: LPSPI2_PCS2 of instance: …\nSelect mux mode: ALT2 mux port: KPP_ROW03 of instance: KPP\nSelect mux mode: ALT3 mux port: OTG1_ID of instance: anatop\nSelect mux mode: ALT4 mux port: FLEXIO1_IO05 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO13 of instance: …\nSelect mux mode: ALT6 mux port: SPDIF_LOCK of instance: …\nSelect mux mode: ALT7 mux port: ARM_CM7_TRACE01 of …\nInput Path is determined by functionality\nForce input path of pad GPIO_13\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPUART2_TXD of instance: …\nSelect mux mode: ALT1 mux port: LPSPI1_PCS2 of instance: …\nSelect mux mode: ALT2 mux port: KPP_COL03 of instance: KPP\nSelect mux mode: ALT3 mux port: USB_OTG1_PWR of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO20 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO14 of instance: …\nSelect mux mode: ALT6 mux port: NMI_GLUE_NMI of instance: …\nSelect mux mode: ALT7 mux port: ARM_CM7_TRACE00 of …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_00\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPUART4_RXD of instance: …\nSelect mux mode: ALT1 mux port: LPSPI2_PCS1 of instance: …\nSelect mux mode: ALT2 mux port: WDOG1_ANY of instance: …\nSelect mux mode: ALT3 mux port: LPI2C2_SDA of instance: …\nSelect mux mode: ALT4 mux port: MQS_LEFT of instance: MQS\nSelect mux mode: ALT5 mux port: GPIOMUX_IO15 of instance: …\nSelect mux mode: ALT6 mux port: USB_OTG1_OC of instance: …\nSelect mux mode: ALT7 mux port: ARM_CM7_TRACE_SWO of …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_01\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPUART4_TXD of instance: …\nSelect mux mode: ALT1 mux port: LPSPI1_PCS1 of instance: …\nSelect mux mode: ALT2 mux port: WDOG2_B of instance: WDOG2\nSelect mux mode: ALT3 mux port: LPI2C2_SCL of instance: …\nSelect mux mode: ALT4 mux port: MQS_RIGHT of instance: MQS\nSelect mux mode: ALT5 mux port: GPIOMUX_IO16 of instance: …\nSelect mux mode: ALT7 mux port: ARM_CM7_TRACE_CLK of …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_02\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPSPI1_SDI of instance: …\nSelect mux mode: ALT1 mux port: PIT_TRIGGER03 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM2_B of …\nSelect mux mode: ALT3 mux port: KPP_ROW02 of instance: KPP\nSelect mux mode: ALT4 mux port: GPT2_CLK of instance: GPT2\nSelect mux mode: ALT5 mux port: GPIOMUX_IO17 of instance: …\nSelect mux mode: ALT6 mux port: SNVS_HP_VIO_5_B of …\nSelect mux mode: ALT7 mux port: JTAG_DE_B of instance: JTAG\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_03\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPSPI1_SDO of instance: …\nSelect mux mode: ALT1 mux port: PIT_TRIGGER02 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM2_A of …\nSelect mux mode: ALT3 mux port: KPP_COL02 of instance: KPP\nSelect mux mode: ALT4 mux port: GPT2_COMPARE1 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO18 of instance: …\nSelect mux mode: ALT6 mux port: SNVS_HP_VIO_5_CTL of …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_04\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPSPI1_PCS0 of instance: …\nSelect mux mode: ALT1 mux port: PIT_TRIGGER01 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of …\nSelect mux mode: ALT3 mux port: KPP_ROW01 of instance: KPP\nSelect mux mode: ALT4 mux port: GPT2_CAPTURE1 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO19 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_05\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPSPI1_SCK of instance: …\nSelect mux mode: ALT1 mux port: PIT_TRIGGER00 of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of …\nSelect mux mode: ALT3 mux port: KPP_COL01 of instance: KPP\nSelect mux mode: ALT4 mux port: GPT2_COMPARE2 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO20 of instance: …\nSelect mux mode: ALT6 mux port: LPI2C1_HREQ of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_06\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPI2C2_SDA of instance: …\nSelect mux mode: ALT1 mux port: LPUART3_RXD of instance: …\nSelect mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: …\nSelect mux mode: ALT3 mux port: LPUART2_RTS_B of instance: …\nSelect mux mode: ALT4 mux port: GPT2_CAPTURE2 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO21 of instance: …\nSelect mux mode: ALT6 mux port: OCOTP_FUSE_LATCHED of …\nSelect mux mode: ALT7 mux port: XBAR1_INOUT03 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_07\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPI2C2_SCL of instance: …\nSelect mux mode: ALT1 mux port: LPUART3_TXD of instance: …\nSelect mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: …\nSelect mux mode: ALT3 mux port: LPUART2_CTS_B of instance: …\nSelect mux mode: ALT4 mux port: GPT2_COMPARE3 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO22 of instance: …\nSelect mux mode: ALT6 mux port: EWM_OUT_B of instance: EWM\nSelect mux mode: ALT7 mux port: JTAG_TRSTB of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_08\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPSPI2_SDI of instance: …\nSelect mux mode: ALT1 mux port: FLEXPWM1_PWM3_X of …\nSelect mux mode: ALT2 mux port: KPP_ROW02 of instance: KPP\nSelect mux mode: ALT3 mux port: ARM_TRACE_SWO of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO21 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO23 of instance: …\nSelect mux mode: ALT6 mux port: REF_32K_OUT of instance: …\nSelect mux mode: ALT7 mux port: JTAG_TDO of instance: JTAG\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_09\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPSPI2_SDO of instance: …\nSelect mux mode: ALT1 mux port: FLEXPWM1_PWM2_X of …\nSelect mux mode: ALT2 mux port: KPP_COL02 of instance: KPP\nSelect mux mode: ALT3 mux port: PIT_TRIGGER03 of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO22 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO24 of instance: …\nSelect mux mode: ALT6 mux port: OTG1_ID of instance: anatop\nSelect mux mode: ALT7 mux port: JTAG_TDI of instance: JTAG\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_10\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPSPI2_PCS0 of instance: …\nSelect mux mode: ALT1 mux port: FLEXPWM1_PWM1_X of …\nSelect mux mode: ALT2 mux port: KPP_ROW01 of instance: KPP\nSelect mux mode: ALT3 mux port: PIT_TRIGGER02 of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO23 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO25 of instance: …\nSelect mux mode: ALT6 mux port: WDOG1_B of instance: WDOG1\nSelect mux mode: ALT7 mux port: JTAG_MOD of instance: JTAG\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_11\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPSPI2_SCK of instance: …\nSelect mux mode: ALT1 mux port: FLEXPWM1_PWM0_X of …\nSelect mux mode: ALT2 mux port: KPP_COL01 of instance: KPP\nSelect mux mode: ALT3 mux port: PIT_TRIGGER01 of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO24 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO26 of instance: …\nSelect mux mode: ALT6 mux port: USB_OTG1_PWR of instance: …\nSelect mux mode: ALT7 mux port: JTAG_TCK of instance: JTAG\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_12\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPI2C1_SDA of instance: …\nSelect mux mode: ALT1 mux port: LPUART3_RTS_B of instance: …\nSelect mux mode: ALT2 mux port: KPP_ROW00 of instance: KPP\nSelect mux mode: ALT3 mux port: LPUART4_RTS_B of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO25 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO27 of instance: …\nSelect mux mode: ALT6 mux port: NMI_GLUE_NMI of instance: …\nSelect mux mode: ALT7 mux port: JTAG_TMS of instance: JTAG\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_13\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: LPI2C1_SCL of instance: …\nSelect mux mode: ALT1 mux port: LPUART3_CTS_B of instance: …\nSelect mux mode: ALT2 mux port: KPP_COL00 of instance: KPP\nSelect mux mode: ALT3 mux port: LPUART4_CTS_B of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO26 of instance: …\nSelect mux mode: ALT5 mux port: GPIOMUX_IO28 of instance: …\nSelect mux mode: ALT6 mux port: REF_CLK_24M of instance: …\nSelect mux mode: ALT7 mux port: XBAR1_INOUT02 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_AD_14\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_B_SS0_B of …\nSelect mux mode: ALT1 mux port: SAI3_TX_SYNC of instance: …\nSelect mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: …\nSelect mux mode: ALT3 mux port: CCM_STOP of instance: CCM\nSelect mux mode: ALT4 mux port: FLEXIO1_IO06 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO00 of instance: …\nSelect mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_00\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_B_DATA01 of …\nSelect mux mode: ALT1 mux port: SAI3_TX_BCLK of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM0_B of …\nSelect mux mode: ALT3 mux port: CCM_CLKO2 of instance: CCM\nSelect mux mode: ALT4 mux port: FLEXIO1_IO07 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO01 of instance: …\nSelect mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_01\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_B_DATA02 of …\nSelect mux mode: ALT1 mux port: SAI3_TX_DATA of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM0_A of …\nSelect mux mode: ALT3 mux port: CCM_CLKO1 of instance: CCM\nSelect mux mode: ALT4 mux port: FLEXIO1_IO08 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO02 of instance: …\nSelect mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_02\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_B_DATA00 of …\nSelect mux mode: ALT1 mux port: SAI3_RX_DATA of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM1_B of …\nSelect mux mode: ALT3 mux port: CCM_REF_EN_B of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO09 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO03 of instance: …\nSelect mux mode: ALT6 mux port: SRC_BOOT_MODE01 of …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_03\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_B_DATA03 of …\nSelect mux mode: ALT1 mux port: SAI3_RX_SYNC of instance: …\nSelect mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of …\nSelect mux mode: ALT3 mux port: CCM_WAIT of instance: CCM\nSelect mux mode: ALT4 mux port: FLEXIO1_IO10 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO04 of instance: …\nSelect mux mode: ALT6 mux port: SRC_BOOT_MODE00 of …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_04\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_SS1_B of …\nSelect mux mode: ALT1 mux port: LPI2C1_SDA of instance: …\nSelect mux mode: ALT2 mux port: LPSPI1_SDI of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO11 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO05 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_05\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_SS0_B of …\nSelect mux mode: ALT1 mux port: LPI2C1_SCL of instance: …\nSelect mux mode: ALT2 mux port: LPSPI1_SDO of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO12 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO06 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_06\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_DATA1 of …\nSelect mux mode: ALT1 mux port: LPI2C2_SDA of instance: …\nSelect mux mode: ALT2 mux port: LPSPI1_PCS0 of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO13 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO07 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_07\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_DATA2 of …\nSelect mux mode: ALT1 mux port: LPI2C2_SCL of instance: …\nSelect mux mode: ALT2 mux port: LPSPI1_SCK of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO14 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO08 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_08\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_DATA0 of …\nSelect mux mode: ALT1 mux port: LPSPI2_SDI of instance: …\nSelect mux mode: ALT2 mux port: LPUART2_RXD of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO15 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO09 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_09\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_SCLK of …\nSelect mux mode: ALT1 mux port: LPSPI2_SDO of instance: …\nSelect mux mode: ALT2 mux port: LPUART2_TXD of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO16 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO10 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_10\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_DATA3 of …\nSelect mux mode: ALT1 mux port: LPSPI2_SCK of instance: …\nSelect mux mode: ALT2 mux port: LPUART1_RXD of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO17 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO11 of instance: …\nSelect mux mode: ALT6 mux port: WDOG1_RST_B_DEB of …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_11\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: …\nSelect mux mode: ALT1 mux port: LPSPI2_PCS0 of instance: …\nSelect mux mode: ALT2 mux port: LPUART1_TXD of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO18 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO12 of instance: …\nSelect mux mode: ALT6 mux port: WDOG2_RST_B_DEB of …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_12\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_B_SCLK of …\nSelect mux mode: ALT1 mux port: SAI3_RX_BCLK of instance: …\nSelect mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: …\nSelect mux mode: ALT3 mux port: CCM_PMIC_RDY of instance: …\nSelect mux mode: ALT4 mux port: FLEXIO1_IO19 of instance: …\nSelect mux mode: ALT5 mux port: GPIO2_IO13 of instance: …\nSelect mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_13\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: …\nSelect mux mode: ALT1 mux port: FLEXSPI_B_DQS of instance: …\nInput Path is determined by functionality\nForce input path of pad GPIO_SD_14\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nlow(50MHz)\nmedium(100MHz)\nfast(150MHz)\nmax(200MHz)\nSlow Slew Rate\nFast Slew Rate\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_13 for Mode: ALT3\nSelecting Pad: GPIO_AD_10 for Mode: ALT6\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_12 for Mode: ALT3\nSelecting Pad: GPIO_AD_01 for Mode: ALT6\nSelecting Pads Involved in Daisy Chain.\nSelecting Pad: GPIO_AD_07 for Mode: ALT2\nSelecting Pad: GPIO_SD_00 for Mode: ALT2\nGPR0 General Purpose Register\nGPR1 General Purpose Register\nGPR1 General Purpose Register\nGPR10 General Purpose Register\nGPR10 General Purpose Register\nGPR11 General Purpose Register\nGPR11 General Purpose Register\nGPR12 General Purpose Register\nGPR12 General Purpose Register\nGPR13 General Purpose Register\nGPR13 General Purpose Register\nGPR14 General Purpose Register\nGPR14 General Purpose Register\nGPR15 General Purpose Register\nGPR16 General Purpose Register\nGPR16 General Purpose Register\nGPR17 General Purpose Register\nGPR17 General Purpose Register\nGPR18 General Purpose Register\nGPR18 General Purpose Register\nGPR19 General Purpose Register\nGPR19 General Purpose Register\nGPR2 General Purpose Register\nGPR2 General Purpose Register\nGPR20 General Purpose Register\nGPR20 General Purpose Register\nGPR21 General Purpose Register\nGPR21 General Purpose Register\nGPR22 General Purpose Register\nGPR22 General Purpose Register\nGPR23 General Purpose Register\nGPR23 General Purpose Register\nGPR24 General Purpose Register\nGPR24 General Purpose Register\nGPR25 General Purpose Register\nGPR25 General Purpose Register\nGPR26 General Purpose Register\nGPR26 General Purpose Register\nGPR27 General Purpose Register\nGPR27 General Purpose Register\nGPR28 General Purpose Register\nGPR28 General Purpose Register\nGPR29 General Purpose Register\nGPR29 General Purpose Register\nGPR3 General Purpose Register\nGPR3 General Purpose Register\nGPR4 General Purpose Register\nGPR4 General Purpose Register\nGPR5 General Purpose Register\nGPR5 General Purpose Register\nGPR6 General Purpose Register\nGPR6 General Purpose Register\nGPR7 General Purpose Register\nGPR7 General Purpose Register\nGPR8 General Purpose Register\nGPR8 General Purpose Register\nGPR9 General Purpose Register\nIOMUXC_GPR\nIOMUXC_GPR")