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https://github.com/rtic-rs/rtic.git
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109 lines
3.8 KiB
Rust
109 lines
3.8 KiB
Rust
use proc_macro2::TokenStream as TokenStream2;
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use quote::quote;
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use rtic_syntax::ast::App;
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use crate::{analyze::Analysis, check::Extra, codegen::util};
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/// Generates code that runs before `#[init]`
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pub fn codegen(app: &App, analysis: &Analysis, extra: &Extra) -> Vec<TokenStream2> {
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let mut stmts = vec![];
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// Disable interrupts -- `init` must run with interrupts disabled
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stmts.push(quote!(rtic::export::interrupt::disable();));
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// Populate the FreeQueue
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for fq in &analysis.free_queues {
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// Get the task name
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let name = fq.0;
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let task = &app.software_tasks[name];
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let cap = task.args.capacity;
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let fq_ident = util::fq_ident(name);
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stmts.push(quote!(
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(0..#cap).for_each(|i| #fq_ident.enqueue_unchecked(i));
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));
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}
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stmts.push(quote!(
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// To set the variable in cortex_m so the peripherals cannot be taken multiple times
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let mut core: rtic::export::Peripherals = rtic::export::Peripherals::steal().into();
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));
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let device = extra.device;
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let nvic_prio_bits = quote!(#device::NVIC_PRIO_BITS);
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// Unmask interrupts and set their priorities
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for (&priority, name) in analysis
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.interrupts
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.iter()
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.chain(app.hardware_tasks.values().flat_map(|task| {
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if !util::is_exception(&task.args.binds) {
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Some((&task.args.priority, &task.args.binds))
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} else {
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// We do exceptions in another pass
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None
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}
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}))
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{
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// Compile time assert that this priority is supported by the device
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stmts.push(quote!(let _ = [(); ((1 << #nvic_prio_bits) - #priority as usize)];));
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// NOTE this also checks that the interrupt exists in the `Interrupt` enumeration
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let interrupt = util::interrupt_ident();
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stmts.push(quote!(
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core.NVIC.set_priority(
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#device::#interrupt::#name,
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rtic::export::logical2hw(#priority, #nvic_prio_bits),
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);
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));
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// NOTE unmask the interrupt *after* setting its priority: changing the priority of a pended
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// interrupt is implementation defined
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stmts.push(quote!(rtic::export::NVIC::unmask(#device::#interrupt::#name);));
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}
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// Set exception priorities
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for (name, priority) in app.hardware_tasks.values().filter_map(|task| {
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if util::is_exception(&task.args.binds) {
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Some((&task.args.binds, task.args.priority))
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} else {
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None
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}
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}) {
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// Compile time assert that this priority is supported by the device
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stmts.push(quote!(let _ = [(); ((1 << #nvic_prio_bits) - #priority as usize)];));
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stmts.push(quote!(core.SCB.set_priority(
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rtic::export::SystemHandler::#name,
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rtic::export::logical2hw(#priority, #nvic_prio_bits),
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);));
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}
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// Initialize the SysTick if there exist a TimerQueue
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if let Some(tq) = analysis.timer_queues.first() {
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let priority = tq.priority;
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// Compile time assert that this priority is supported by the device
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stmts.push(quote!(let _ = [(); ((1 << #nvic_prio_bits) - #priority as usize)];));
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stmts.push(quote!(core.SCB.set_priority(
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rtic::export::SystemHandler::SysTick,
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rtic::export::logical2hw(#priority, #nvic_prio_bits),
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);));
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stmts.push(quote!(
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core.SYST.set_clock_source(rtic::export::SystClkSource::Core);
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core.SYST.enable_counter();
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core.DCB.enable_trace();
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));
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}
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// If there's no user `#[idle]` then optimize returning from interrupt handlers
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if app.idles.is_empty() {
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// Set SLEEPONEXIT bit to enter sleep mode when returning from ISR
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stmts.push(quote!(core.SCB.scr.modify(|r| r | 1 << 1);));
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}
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stmts
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}
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