1
0
Fork 0
mirror of https://github.com/rtic-rs/rtic.git synced 2024-12-22 09:59:32 +01:00
rtic/ci/expected/hifive1/prio_inheritance.run
Román Cárdenas Rodríguez 4060c3def8
RISC-V support over CLINT ()
* Rebase to master

* using interrupt_mod

* bug fixes

* fix other backends

* Add changelog

* forgot about rtic-macros

* backend-specific configuration

* core peripherals optional over macro argument

* pre_init_preprocessing binding

* CI for RISC-V (WIP)

* separation of concerns

* add targets for RISC-V examples

* remove qemu feature

* prepare examples folder

* move examples all together

* move ci out of examples

* minor changes

* add cortex-m

* new xtask: proof of concept

* fix build.yml

* feature typo

* clean rtic examples

* reproduce weird issue

* remove unsafe code in user app

* update dependencies

* allow builds on riscv32imc

* let's fix QEMU

* Update .github/workflows/build.yml

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>

* New build.rs

* removing test features

* adapt ui test to new version of clippy

* add more examples to RISC-V backend

* proper configuration of heapless for riscv32imc

* opt-out examples for riscv32imc

* point to new version of riscv-slic

* adapt new macro bindings

* adapt examples and CI to stable

* fix cortex-m CI

* Review

---------

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2024-03-20 20:06:47 +00:00

17 lines
391 B
Text

[Idle]: Started
[SoftMedium]: Started
[SoftMedium]: Shared: 1
[SoftHigh]: Started
[SoftHigh]: Shared: 2
[SoftHigh]: Finished
[SoftMedium]: Finished
[SoftLow1]: Started
[SoftLow1]: Shared: 3
[SoftLow1]: Yield
[SoftLow2]: Started
[SoftLow2]: Shared: 4
[SoftLow2]: Yield
[SoftLow1]: Finished
[SoftLow2]: Finished
[Idle]: Shared: 4
[Idle]: Finished