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* Rebase to master * using interrupt_mod * bug fixes * fix other backends * Add changelog * forgot about rtic-macros * backend-specific configuration * core peripherals optional over macro argument * pre_init_preprocessing binding * CI for RISC-V (WIP) * separation of concerns * add targets for RISC-V examples * remove qemu feature * prepare examples folder * move examples all together * move ci out of examples * minor changes * add cortex-m * new xtask: proof of concept * fix build.yml * feature typo * clean rtic examples * reproduce weird issue * remove unsafe code in user app * update dependencies * allow builds on riscv32imc * let's fix QEMU * Update .github/workflows/build.yml Co-authored-by: Henrik Tjäder <henrik@tjaders.com> * New build.rs * removing test features * adapt ui test to new version of clippy * add more examples to RISC-V backend * proper configuration of heapless for riscv32imc * opt-out examples for riscv32imc * point to new version of riscv-slic * adapt new macro bindings * adapt examples and CI to stable * fix cortex-m CI * Review --------- Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
34 lines
635 B
Markdown
34 lines
635 B
Markdown
# Change Log
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All notable changes to this project will be documented in this file.
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This project adheres to [Semantic Versioning](http://semver.org/).
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For each category, *Added*, *Changed*, *Fixed* add new entries at the top!
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## [Unreleased]
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## [v2.1.0] - 2024-02-27
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### Added
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- Unstable support for RISC-V targets compatible with `riscv-slic`
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- RTIC v2 now works on stable.
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- Unstable ESP32-C3 support.
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### Changed
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- Upgraded from syn 1.x to syn 2.x
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## [v2.0.1] - 2023-07-25
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### Added
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- `init` and `idle` can now be externed.
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### Fixed
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- Support new TAIT syntax requirement.
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## [v2.0.0] - 2023-05-31
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- Initial v2 release
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