rtic/rtic-macros/CHANGELOG.md
Román Cárdenas Rodríguez 4060c3def8
RISC-V support over CLINT (#815)
* Rebase to master

* using interrupt_mod

* bug fixes

* fix other backends

* Add changelog

* forgot about rtic-macros

* backend-specific configuration

* core peripherals optional over macro argument

* pre_init_preprocessing binding

* CI for RISC-V (WIP)

* separation of concerns

* add targets for RISC-V examples

* remove qemu feature

* prepare examples folder

* move examples all together

* move ci out of examples

* minor changes

* add cortex-m

* new xtask: proof of concept

* fix build.yml

* feature typo

* clean rtic examples

* reproduce weird issue

* remove unsafe code in user app

* update dependencies

* allow builds on riscv32imc

* let's fix QEMU

* Update .github/workflows/build.yml

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>

* New build.rs

* removing test features

* adapt ui test to new version of clippy

* add more examples to RISC-V backend

* proper configuration of heapless for riscv32imc

* opt-out examples for riscv32imc

* point to new version of riscv-slic

* adapt new macro bindings

* adapt examples and CI to stable

* fix cortex-m CI

* Review

---------

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2024-03-20 20:06:47 +00:00

635 B

Change Log

All notable changes to this project will be documented in this file. This project adheres to Semantic Versioning.

For each category, Added, Changed, Fixed add new entries at the top!

[Unreleased]

[v2.1.0] - 2024-02-27

Added

  • Unstable support for RISC-V targets compatible with riscv-slic
  • RTIC v2 now works on stable.
  • Unstable ESP32-C3 support.

Changed

  • Upgraded from syn 1.x to syn 2.x

[v2.0.1] - 2023-07-25

Added

  • init and idle can now be externed.

Fixed

  • Support new TAIT syntax requirement.

[v2.0.0] - 2023-05-31

  • Initial v2 release