mirror of
https://github.com/rtic-rs/rtic.git
synced 2024-11-23 20:22:51 +01:00
4060c3def8
* Rebase to master * using interrupt_mod * bug fixes * fix other backends * Add changelog * forgot about rtic-macros * backend-specific configuration * core peripherals optional over macro argument * pre_init_preprocessing binding * CI for RISC-V (WIP) * separation of concerns * add targets for RISC-V examples * remove qemu feature * prepare examples folder * move examples all together * move ci out of examples * minor changes * add cortex-m * new xtask: proof of concept * fix build.yml * feature typo * clean rtic examples * reproduce weird issue * remove unsafe code in user app * update dependencies * allow builds on riscv32imc * let's fix QEMU * Update .github/workflows/build.yml Co-authored-by: Henrik Tjäder <henrik@tjaders.com> * New build.rs * removing test features * adapt ui test to new version of clippy * add more examples to RISC-V backend * proper configuration of heapless for riscv32imc * opt-out examples for riscv32imc * point to new version of riscv-slic * adapt new macro bindings * adapt examples and CI to stable * fix cortex-m CI * Review --------- Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
47 lines
700 B
Text
47 lines
700 B
Text
init
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idle p0 started
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t2 p4 called 1 time
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enter lock s4 0
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t3 p4 exit
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idle enter lock s3 0
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idle pend t0
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idle pend t1
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idle pend t2
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t2 p4 called 2 times
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enter lock s4 1
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t3 p4 exit
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idle still in lock s3 0
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t1 p3 called 1 time
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t1 enter lock s4 2
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t1 pend t0
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t1 pend t2
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t1 still in lock s4 2
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t2 p4 called 3 times
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enter lock s4 2
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t3 p4 exit
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t1 p3 exit
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t0 p2 called 1 time
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t0 p2 exit
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back in idle
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enter lock s2 0
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idle pend t0
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idle pend t1
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t1 p3 called 2 times
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t1 enter lock s4 3
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t1 pend t0
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t1 pend t2
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t1 still in lock s4 3
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t2 p4 called 4 times
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enter lock s4 3
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t3 p4 exit
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t1 p3 exit
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idle pend t2
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t2 p4 called 5 times
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enter lock s4 4
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t3 p4 exit
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idle still in lock s2 0
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t0 p2 called 2 times
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t0 p2 exit
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idle exit
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