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120 lines
3.2 KiB
Rust
120 lines
3.2 KiB
Rust
//! Real-Time Interrupt-driven Concurrency (RTIC) framework for ARM Cortex-M microcontrollers
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//!
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//! **HEADS UP** This is an **beta** pre-release; there may be breaking changes in the API and
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//! semantics before a proper release is made.
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//!
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//! **IMPORTANT**: This crate is published as [`cortex-m-rtic`] on crates.io but the name of the
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//! library is `rtic`.
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//!
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//! [`cortex-m-rtic`]: https://crates.io/crates/cortex-m-rtic
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//!
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//! The user level documentation can be found [here].
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//!
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//! [here]: https://rtic.rs
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//!
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//! Don't forget to check the documentation of the `#[app]` attribute (listed under the reexports
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//! section), which is the main component of the framework.
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//!
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//! # Minimum Supported Rust Version (MSRV)
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//!
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//! This crate is guaranteed to compile on stable Rust 1.36 (2018 edition) and up. It *might*
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//! compile on older versions but that may change in any new patch release.
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//!
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//! # Semantic Versioning
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//!
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//! Like the Rust project, this crate adheres to [SemVer]: breaking changes in the API and semantics
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//! require a *semver bump* (a new minor version release), with the exception of breaking changes
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//! that fix soundness issues -- those are considered bug fixes and can be landed in a new patch
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//! release.
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//!
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//! [SemVer]: https://semver.org/spec/v2.0.0.html
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#![deny(missing_docs)]
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#![deny(rust_2018_compatibility)]
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#![deny(rust_2018_idioms)]
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#![deny(warnings)]
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#![no_std]
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use core::ops::Sub;
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use cortex_m::{
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interrupt::Nr,
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peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, TPIU},
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};
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pub use cortex_m_rtic_macros::app;
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pub use rtic_core::{prelude as mutex_prelude, Exclusive, Mutex};
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#[cfg(armv7m)]
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pub mod cyccnt;
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#[doc(hidden)]
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pub mod export;
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#[doc(hidden)]
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mod tq;
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/// `cortex_m::Peripherals` minus `SYST`
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#[allow(non_snake_case)]
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pub struct Peripherals {
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/// Cache and branch predictor maintenance operations (not present on Cortex-M0 variants)
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pub CBP: CBP,
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/// CPUID
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pub CPUID: CPUID,
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/// Debug Control Block
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pub DCB: DCB,
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/// Data Watchpoint and Trace unit
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pub DWT: DWT,
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/// Flash Patch and Breakpoint unit (not present on Cortex-M0 variants)
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pub FPB: FPB,
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/// Floating Point Unit (only present on `thumbv7em-none-eabihf`)
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pub FPU: FPU,
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/// Instrumentation Trace Macrocell (not present on Cortex-M0 variants)
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pub ITM: ITM,
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/// Memory Protection Unit
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pub MPU: MPU,
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/// Nested Vector Interrupt Controller
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pub NVIC: NVIC,
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/// System Control Block
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pub SCB: SCB,
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// SysTick: System Timer
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// pub SYST: SYST,
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/// Trace Port Interface Unit (not present on Cortex-M0 variants)
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pub TPIU: TPIU,
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}
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impl From<cortex_m::Peripherals> for Peripherals {
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fn from(p: cortex_m::Peripherals) -> Self {
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Self {
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CBP: p.CBP,
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CPUID: p.CPUID,
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DCB: p.DCB,
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DWT: p.DWT,
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FPB: p.FPB,
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FPU: p.FPU,
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ITM: p.ITM,
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MPU: p.MPU,
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NVIC: p.NVIC,
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SCB: p.SCB,
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TPIU: p.TPIU,
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}
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}
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}
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/// Sets the given `interrupt` as pending
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///
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/// This is a convenience function around
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/// [`NVIC::pend`](../cortex_m/peripheral/struct.NVIC.html#method.pend)
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pub fn pend<I>(interrupt: I)
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where
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I: Nr,
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{
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NVIC::pend(interrupt)
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}
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