368ab1d4fb
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets. |
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Real-Time Interrupt-driven Concurrency
A concurrency framework for building real-time systems.
Formerly known as Real-Time For the Masses.
Features
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Tasks as the unit of concurrency 1. Tasks can be event triggered (fired in response to asynchronous stimuli) or spawned by the application on demand.
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Message passing between tasks. Specifically, messages can be passed to software tasks at spawn time.
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A timer queue 2. Software tasks can be scheduled to run at some time in the future. This feature can be used to implement periodic tasks.
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Support for prioritization of tasks and, thus, preemptive multitasking.
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Efficient and data race free memory sharing through fine grained priority based critical sections 1.
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Deadlock free execution guaranteed at compile time. This is a stronger guarantee than what's provided by the standard
Mutexabstraction.
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Minimal scheduling overhead. The task scheduler has minimal software footprint; the hardware does the bulk of the scheduling.
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Highly efficient memory usage: All the tasks share a single call stack and there's no hard dependency on a dynamic memory allocator.
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All Cortex-M devices are fully supported.
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This task model is amenable to known WCET (Worst Case Execution Time) analysis and scheduling analysis techniques.
Crate cortex-m 0.6 vs 0.7 in RTIC 0.5.x
The crate cortex-m 0.7 started using trait InterruptNumber for interrupts instead of Nr from bare-metal. In order to preserve backwards compatibility, RTIC 0.5.x will keep using cortex-m 0.6 by default. cortex-m 0.7 can be enabled using the feature cortex-m-7 and disabling default features:
cortex-m-rtic = { version = "0.5.8", default-features = false, features = ["cortex-m-7"] }
RTIC 1.0.0 already uses cortex-m 0.7 by default.
User documentation
Documentation for the development version.
API reference
Community provided examples repo
Chat
Join us and talk about RTIC in the Matrix room.
Weekly meeting notes can be found over at HackMD
Contributing
New features and big changes should go through the RFC process in the dedicated RFC repository.
Running tests locally
To check all Run-pass tests locally on your thumbv6m-none-eabi or thumbv7m-none-eabi target device, run
$ cargo xtask --target <your target>
# ˆˆˆˆˆˆˆˆˆˆˆˆ
# e.g. thumbv7m-none-eabi
Acknowledgments
This crate is based on the Real-Time For the Masses language created by the Embedded Systems group at Luleå University of Technology, led by Prof. Per Lindgren.
References
License
All source code (including code snippets) is licensed under either of
- Apache License, Version 2.0 (LICENSE-APACHE or https://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or https://opensource.org/licenses/MIT)
at your option.
The written prose contained within the book is licensed under the terms of the Creative Commons CC-BY-SA v4.0 license (LICENSE-CC-BY-SA or https://creativecommons.org/licenses/by-sa/4.0/legalcode).
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be licensed as above, without any additional terms or conditions.
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Eriksson, J., Häggström, F., Aittamaa, S., Kruglyak, A., & Lindgren, P. (2013, June). Real-time for the masses, step 1: Programming API and static priority SRP kernel primitives. In Industrial Embedded Systems (SIES), 2013 8th IEEE International Symposium on (pp. 110-113). IEEE. ↩︎
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Lindgren, P., Fresk, E., Lindner, M., Lindner, A., Pereira, D., & Pinho, L. M. (2016). Abstract timers and their implementation onto the arm cortex-m family of mcus. ACM SIGBED Review, 13(1), 48-53. ↩︎