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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Receive Status Register/Error Clear Register, UARTRSR/UARTECR"><title>rp2040_pac::uart0::uartrsr - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module uartrsr</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>uart0</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">uart0</a></span><h1>Module <span>uartrsr</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/rp2040_pac/uart0/uartrsr.rs.html#1-96">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Receive Status Register/Error Clear Register, UARTRSR/UARTECR</p>
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</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.UARTRSR_SPEC.html" title="struct rp2040_pac::uart0::uartrsr::UARTRSR_SPEC">UARTRSR_<wbr>SPEC</a></div><div class="desc docblock-short">Receive Status Register/Error Clear Register, UARTRSR/UARTECR</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.BE_R.html" title="type rp2040_pac::uart0::uartrsr::BE_R">BE_R</a></div><div class="desc docblock-short">Field <code>BE</code> reader - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.</div></li><li><div class="item-name"><a class="type" href="type.BE_W.html" title="type rp2040_pac::uart0::uartrsr::BE_W">BE_W</a></div><div class="desc docblock-short">Field <code>BE</code> writer - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.</div></li><li><div class="item-name"><a class="type" href="type.FE_R.html" title="type rp2040_pac::uart0::uartrsr::FE_R">FE_R</a></div><div class="desc docblock-short">Field <code>FE</code> reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.FE_W.html" title="type rp2040_pac::uart0::uartrsr::FE_W">FE_W</a></div><div class="desc docblock-short">Field <code>FE</code> writer - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.OE_R.html" title="type rp2040_pac::uart0::uartrsr::OE_R">OE_R</a></div><div class="desc docblock-short">Field <code>OE</code> reader - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.OE_W.html" title="type rp2040_pac::uart0::uartrsr::OE_W">OE_W</a></div><div class="desc docblock-short">Field <code>OE</code> writer - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.PE_R.html" title="type rp2040_pac::uart0::uartrsr::PE_R">PE_R</a></div><div class="desc docblock-short">Field <code>PE</code> reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.PE_W.html" title="type rp2040_pac::uart0::uartrsr::PE_W">PE_W</a></div><div class="desc docblock-short">Field <code>PE</code> writer - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.R.html" title="type rp2040_pac::uart0::uartrsr::R">R</a></div><div class="desc docblock-short">Register <code>UARTRSR</code> reader</div></li><li><div class="item-name"><a class="type" href="type.W.html" title="type rp2040_pac::uart0::uartrsr::W">W</a></div><div class="desc docblock-short">Register <code>UARTRSR</code> writer</div></li></ul></section></div></main></body></html> |