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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."><title>rp2040_pac::sio::fifo_st - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module fifo_st</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>sio</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">sio</a></span><h1>Module <span>fifo_st</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/rp2040_pac/sio/fifo_st.rs.html#1-84">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Status register for inter-core FIFOs (mailboxes).<br />
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There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.<br />
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Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).<br />
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Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).<br />
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The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</p>
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</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.FIFO_ST_SPEC.html" title="struct rp2040_pac::sio::fifo_st::FIFO_ST_SPEC">FIFO_<wbr>ST_<wbr>SPEC</a></div><div class="desc docblock-short">Status register for inter-core FIFOs (mailboxes).<br />
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There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.<br />
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Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).<br />
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Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).<br />
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The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.R.html" title="type rp2040_pac::sio::fifo_st::R">R</a></div><div class="desc docblock-short">Register <code>FIFO_ST</code> reader</div></li><li><div class="item-name"><a class="type" href="type.RDY_R.html" title="type rp2040_pac::sio::fifo_st::RDY_R">RDY_R</a></div><div class="desc docblock-short">Field <code>RDY</code> reader - Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)</div></li><li><div class="item-name"><a class="type" href="type.ROE_R.html" title="type rp2040_pac::sio::fifo_st::ROE_R">ROE_R</a></div><div class="desc docblock-short">Field <code>ROE</code> reader - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.ROE_W.html" title="type rp2040_pac::sio::fifo_st::ROE_W">ROE_W</a></div><div class="desc docblock-short">Field <code>ROE</code> writer - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.VLD_R.html" title="type rp2040_pac::sio::fifo_st::VLD_R">VLD_R</a></div><div class="desc docblock-short">Field <code>VLD</code> reader - Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid)</div></li><li><div class="item-name"><a class="type" href="type.W.html" title="type rp2040_pac::sio::fifo_st::W">W</a></div><div class="desc docblock-short">Register <code>FIFO_ST</code> writer</div></li><li><div class="item-name"><a class="type" href="type.WOF_R.html" title="type rp2040_pac::sio::fifo_st::WOF_R">WOF_R</a></div><div class="desc docblock-short">Field <code>WOF</code> reader - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.</div></li><li><div class="item-name"><a class="type" href="type.WOF_W.html" title="type rp2040_pac::sio::fifo_st::WOF_W">WOF_W</a></div><div class="desc docblock-short">Field <code>WOF</code> writer - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.</div></li></ul></section></div></main></body></html> |