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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Control Register, UARTCR"><title>rp2040_pac::uart0::uartcr - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module uartcr</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>uart0</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">uart0</a></span><h1>Module <span>uartcr</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/rp2040_pac/uart0/uartcr.rs.html#1-216">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Control Register, UARTCR</p>
</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.UARTCR_SPEC.html" title="struct rp2040_pac::uart0::uartcr::UARTCR_SPEC">UARTCR_<wbr>SPEC</a></div><div class="desc docblock-short">Control Register, UARTCR</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.CTSEN_R.html" title="type rp2040_pac::uart0::uartcr::CTSEN_R">CTSEN_R</a></div><div class="desc docblock-short">Field <code>CTSEN</code> reader - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.</div></li><li><div class="item-name"><a class="type" href="type.CTSEN_W.html" title="type rp2040_pac::uart0::uartcr::CTSEN_W">CTSEN_W</a></div><div class="desc docblock-short">Field <code>CTSEN</code> writer - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.</div></li><li><div class="item-name"><a class="type" href="type.DTR_R.html" title="type rp2040_pac::uart0::uartcr::DTR_R">DTR_R</a></div><div class="desc docblock-short">Field <code>DTR</code> reader - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.</div></li><li><div class="item-name"><a class="type" href="type.DTR_W.html" title="type rp2040_pac::uart0::uartcr::DTR_W">DTR_W</a></div><div class="desc docblock-short">Field <code>DTR</code> writer - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.</div></li><li><div class="item-name"><a class="type" href="type.LBE_R.html" title="type rp2040_pac::uart0::uartcr::LBE_R">LBE_R</a></div><div class="desc docblock-short">Field <code>LBE</code> reader - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.</div></li><li><div class="item-name"><a class="type" href="type.LBE_W.html" title="type rp2040_pac::uart0::uartcr::LBE_W">LBE_W</a></div><div class="desc docblock-short">Field <code>LBE</code> writer - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.</div></li><li><div class="item-name"><a class="type" href="type.OUT1_R.html" title="type rp2040_pac::uart0::uartcr::OUT1_R">OUT1_R</a></div><div class="desc docblock-short">Field <code>OUT1</code> reader - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).</div></li><li><div class="item-name"><a class="type" href="type.OUT1_W.html" title="type rp2040_pac::uart0::uartcr::OUT1_W">OUT1_W</a></div><div class="desc docblock-short">Field <code>OUT1</code> writer - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).</div></li><li><div class="item-name"><a class="type" href="type.OUT2_R.html" title="type rp2040_pac::uart0::uartcr::OUT2_R">OUT2_R</a></div><div class="desc docblock-short">Field <code>OUT2</code> reader - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).</div></li><li><div class="item-name"><a class="type" href="type.OUT2_W.html" title="type rp2040_pac::uart0::uartcr::OUT2_W">OUT2_W</a></div><div class="desc docblock-short">Field <code>OUT2</code> writer - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).</div></li><li><div class="item-name"><a class="type" href="type.R.html" title="type rp2040_pac::uart0::uartcr::R">R</a></div><div class="desc docblock-short">Register <code>UARTCR</code> reader</div></li><li><div class="item-name"><a class="type" href="type.RTSEN_R.html" title="type rp2040_pac::uart0::uartcr::RTSEN_R">RTSEN_R</a></div><div class="desc docblock-short">Field <code>RTSEN</code> reader - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.</div></li><li><div class="item-name"><a class="type" href="type.RTSEN_W.html" title="type rp2040_pac::uart0::uartcr::RTSEN_W">RTSEN_W</a></div><div class="desc docblock-short">Field <code>RTSEN</code> writer - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.</div></li><li><div class="item-name"><a class="type" href="type.RTS_R.html" title="type rp2040_pac::uart0::uartcr::RTS_R">RTS_R</a></div><div class="desc docblock-short">Field <code>RTS</code> reader - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.</div></li><li><div class="item-name"><a class="type" href="type.RTS_W.html" title="type rp2040_pac::uart0::uartcr::RTS_W">RTS_W</a></div><div class="desc docblock-short">Field <code>RTS</code> writer - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.</div></li><li><div class="item-name"><a class="type" href="type.RXE_R.html" title="type rp2040_pac::uart0::uartcr::RXE_R">RXE_R</a></div><div class="desc docblock-short">Field <code>RXE</code> reader - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.</div></li><li><div class="item-name"><a class="type" href="type.RXE_W.html" title="type rp2040_pac::uart0::uartcr::RXE_W">RXE_W</a></div><div class="desc docblock-short">Field <code>RXE</code> writer - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.</div></li><li><div class="item-name"><a class="type" href="type.SIREN_R.html" title="type rp2040_pac::uart0::uartcr::SIREN_R">SIREN_R</a></div><div class="desc docblock-short">Field <code>SIREN</code> reader - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.</div></li><li><div class="item-name"><a class="type" href="type.SIREN_W.html" title="type rp2040_pac::uart0::uartcr::SIREN_W">SIREN_W</a></div><div class="desc docblock-short">Field <code>SIREN</code> writer - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.</div></li><li><div class="item-name"><a class="type" href="type.SIRLP_R.html" title="type rp2040_pac::uart0::uartcr::SIRLP_R">SIRLP_R</a></div><div class="desc docblock-short">Field <code>SIRLP</code> reader - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.</div></li><li><div class="item-name"><a class="type" href="type.SIRLP_W.html" title="type rp2040_pac::uart0::uartcr::SIRLP_W">SIRLP_W</a></div><div class="desc docblock-short">Field <code>SIRLP</code> writer - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.</div></li><li><div class="item-name"><a class="type" href="type.TXE_R.html" title="type rp2040_pac::uart0::uartcr::TXE_R">TXE_R</a></div><div class="desc docblock-short">Field <code>TXE</code> reader - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.</div></li><li><div class="item-name"><a class="type" href="type.TXE_W.html" title="type rp2040_pac::uart0::uartcr::TXE_W">TXE_W</a></div><div class="desc docblock-short">Field <code>TXE</code> writer - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.</div></li><li><div class="item-name"><a class="type" href="type.UARTEN_R.html" title="type rp2040_pac::uart0::uartcr::UARTEN_R">UARTEN_<wbr>R</a></div><div class="desc docblock-short">Field <code>UARTEN</code> reader - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.</div></li><li><div class="item-name"><a class="type" href="type.UARTEN_W.html" title="type rp2040_pac::uart0::uartcr::UARTEN_W">UARTEN_<wbr>W</a></div><div class="desc docblock-short">Field <code>UARTEN</code> writer - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.</div></li><li><div class="item-name"><a class="type" href="type.W.html" title="type rp2040_pac::uart0::uartcr::W">W</a></div><div class="desc docblock-short">Register <code>UARTCR</code> writer</div></li></ul></section></div></main></body></html>
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