mirror of
https://github.com/rtic-rs/rtic.git
synced 2024-12-25 11:29:33 +01:00
16 lines
No EOL
6.1 KiB
HTML
16 lines
No EOL
6.1 KiB
HTML
<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="PLL_SYS"><title>rp2040_pac::pll_sys - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module pll_sys</a></h2><h3><a href="#modules">Module Items</a></h3><ul class="block"><li><a href="#modules" title="Modules">Modules</a></li><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2 class="in-crate"><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../index.html">rp2040_pac</a></span><h1>Module <span>pll_sys</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../src/rp2040_pac/pll_sys.rs.html#1-87">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>PLL_SYS</p>
|
|
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="cs/index.html" title="mod rp2040_pac::pll_sys::cs">cs</a></div><div class="desc docblock-short">Control and Status<br />
|
|
GENERAL CONSTRAINTS:<br />
|
|
Reference clock frequency min=5MHz, max=800MHz<br />
|
|
Feedback divider min=16, max=320<br />
|
|
VCO frequency min=750MHz, max=1600MHz</div></li><li><div class="item-name"><a class="mod" href="fbdiv_int/index.html" title="mod rp2040_pac::pll_sys::fbdiv_int">fbdiv_<wbr>int</a></div><div class="desc docblock-short">Feedback divisor<br />
|
|
(note: this PLL does not support fractional division)</div></li><li><div class="item-name"><a class="mod" href="prim/index.html" title="mod rp2040_pac::pll_sys::prim">prim</a></div><div class="desc docblock-short">Controls the PLL post dividers for the primary output<br />
|
|
(note: this PLL does not have a secondary output)<br />
|
|
the primary output is driven from VCO divided by postdiv1*postdiv2</div></li><li><div class="item-name"><a class="mod" href="pwr/index.html" title="mod rp2040_pac::pll_sys::pwr">pwr</a></div><div class="desc docblock-short">Controls the PLL power modes.</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::pll_sys::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.CS.html" title="type rp2040_pac::pll_sys::CS">CS</a></div><div class="desc docblock-short">CS (rw) register accessor: Control and Status<br />
|
|
GENERAL CONSTRAINTS:<br />
|
|
Reference clock frequency min=5MHz, max=800MHz<br />
|
|
Feedback divider min=16, max=320<br />
|
|
VCO frequency min=750MHz, max=1600MHz</div></li><li><div class="item-name"><a class="type" href="type.FBDIV_INT.html" title="type rp2040_pac::pll_sys::FBDIV_INT">FBDIV_<wbr>INT</a></div><div class="desc docblock-short">FBDIV_INT (rw) register accessor: Feedback divisor<br />
|
|
(note: this PLL does not support fractional division)</div></li><li><div class="item-name"><a class="type" href="type.PRIM.html" title="type rp2040_pac::pll_sys::PRIM">PRIM</a></div><div class="desc docblock-short">PRIM (rw) register accessor: Controls the PLL post dividers for the primary output<br />
|
|
(note: this PLL does not have a secondary output)<br />
|
|
the primary output is driven from VCO divided by postdiv1*postdiv2</div></li><li><div class="item-name"><a class="type" href="type.PWR.html" title="type rp2040_pac::pll_sys::PWR">PWR</a></div><div class="desc docblock-short">PWR (rw) register accessor: Controls the PLL power modes.</div></li></ul></section></div></main></body></html> |