mirror/rtic
1
0
Fork 0
mirror of https://github.com/rtic-rs/rtic.git synced 2024-12-25 11:29:33 +01:00
Code Issues Projects Releases Packages Wiki Activity
rtic/2/api/rp2040_pac/clocks/index.html
korken89 d2b764a7c5 deploy: 1a1237690c
2024-12-06 13:35:18 +00:00

28 lines
No EOL
33 KiB
HTML
Raw Permalink Blame History

This file contains ambiguous Unicode characters

This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="CLOCKS"><title>rp2040_pac::clocks - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module clocks</a></h2><h3><a href="#modules">Module Items</a></h3><ul class="block"><li><a href="#modules" title="Modules">Modules</a></li><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2 class="in-crate"><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../index.html">rp2040_pac</a></span><h1>Module <span>clocks</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../src/rp2040_pac/clocks.rs.html#1-781">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>CLOCKS</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="clk_adc_ctrl/index.html" title="mod rp2040_pac::clocks::clk_adc_ctrl">clk_<wbr>adc_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_adc_div/index.html" title="mod rp2040_pac::clocks::clk_adc_div">clk_<wbr>adc_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_adc_selected/index.html" title="mod rp2040_pac::clocks::clk_adc_selected">clk_<wbr>adc_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="mod" href="clk_gpout0_ctrl/index.html" title="mod rp2040_pac::clocks::clk_gpout0_ctrl">clk_<wbr>gpout0_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_gpout0_div/index.html" title="mod rp2040_pac::clocks::clk_gpout0_div">clk_<wbr>gpout0_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_gpout0_selected/index.html" title="mod rp2040_pac::clocks::clk_gpout0_selected">clk_<wbr>gpout0_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="mod" href="clk_gpout1_ctrl/index.html" title="mod rp2040_pac::clocks::clk_gpout1_ctrl">clk_<wbr>gpout1_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_gpout1_div/index.html" title="mod rp2040_pac::clocks::clk_gpout1_div">clk_<wbr>gpout1_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_gpout1_selected/index.html" title="mod rp2040_pac::clocks::clk_gpout1_selected">clk_<wbr>gpout1_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="mod" href="clk_gpout2_ctrl/index.html" title="mod rp2040_pac::clocks::clk_gpout2_ctrl">clk_<wbr>gpout2_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_gpout2_div/index.html" title="mod rp2040_pac::clocks::clk_gpout2_div">clk_<wbr>gpout2_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_gpout2_selected/index.html" title="mod rp2040_pac::clocks::clk_gpout2_selected">clk_<wbr>gpout2_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="mod" href="clk_gpout3_ctrl/index.html" title="mod rp2040_pac::clocks::clk_gpout3_ctrl">clk_<wbr>gpout3_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_gpout3_div/index.html" title="mod rp2040_pac::clocks::clk_gpout3_div">clk_<wbr>gpout3_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_gpout3_selected/index.html" title="mod rp2040_pac::clocks::clk_gpout3_selected">clk_<wbr>gpout3_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="mod" href="clk_peri_ctrl/index.html" title="mod rp2040_pac::clocks::clk_peri_ctrl">clk_<wbr>peri_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_peri_selected/index.html" title="mod rp2040_pac::clocks::clk_peri_selected">clk_<wbr>peri_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="mod" href="clk_ref_ctrl/index.html" title="mod rp2040_pac::clocks::clk_ref_ctrl">clk_<wbr>ref_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_ref_div/index.html" title="mod rp2040_pac::clocks::clk_ref_div">clk_<wbr>ref_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_ref_selected/index.html" title="mod rp2040_pac::clocks::clk_ref_selected">clk_<wbr>ref_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</div></li><li><div class="item-name"><a class="mod" href="clk_rtc_ctrl/index.html" title="mod rp2040_pac::clocks::clk_rtc_ctrl">clk_<wbr>rtc_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_rtc_div/index.html" title="mod rp2040_pac::clocks::clk_rtc_div">clk_<wbr>rtc_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_rtc_selected/index.html" title="mod rp2040_pac::clocks::clk_rtc_selected">clk_<wbr>rtc_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="mod" href="clk_sys_ctrl/index.html" title="mod rp2040_pac::clocks::clk_sys_ctrl">clk_<wbr>sys_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_sys_div/index.html" title="mod rp2040_pac::clocks::clk_sys_div">clk_<wbr>sys_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_sys_resus_ctrl/index.html" title="mod rp2040_pac::clocks::clk_sys_resus_ctrl">clk_<wbr>sys_<wbr>resus_<wbr>ctrl</a></div></li><li><div class="item-name"><a class="mod" href="clk_sys_resus_status/index.html" title="mod rp2040_pac::clocks::clk_sys_resus_status">clk_<wbr>sys_<wbr>resus_<wbr>status</a></div></li><li><div class="item-name"><a class="mod" href="clk_sys_selected/index.html" title="mod rp2040_pac::clocks::clk_sys_selected">clk_<wbr>sys_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</div></li><li><div class="item-name"><a class="mod" href="clk_usb_ctrl/index.html" title="mod rp2040_pac::clocks::clk_usb_ctrl">clk_<wbr>usb_<wbr>ctrl</a></div><div class="desc docblock-short">Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="mod" href="clk_usb_div/index.html" title="mod rp2040_pac::clocks::clk_usb_div">clk_<wbr>usb_<wbr>div</a></div><div class="desc docblock-short">Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="mod" href="clk_usb_selected/index.html" title="mod rp2040_pac::clocks::clk_usb_selected">clk_<wbr>usb_<wbr>selected</a></div><div class="desc docblock-short">Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="mod" href="enabled0/index.html" title="mod rp2040_pac::clocks::enabled0">enabled0</a></div><div class="desc docblock-short">indicates the state of the clock enable</div></li><li><div class="item-name"><a class="mod" href="enabled1/index.html" title="mod rp2040_pac::clocks::enabled1">enabled1</a></div><div class="desc docblock-short">indicates the state of the clock enable</div></li><li><div class="item-name"><a class="mod" href="fc0_delay/index.html" title="mod rp2040_pac::clocks::fc0_delay">fc0_<wbr>delay</a></div><div class="desc docblock-short">Delays the start of frequency counting to allow the mux to settle<br />
Delay is measured in multiples of the reference clock period</div></li><li><div class="item-name"><a class="mod" href="fc0_interval/index.html" title="mod rp2040_pac::clocks::fc0_interval">fc0_<wbr>interval</a></div><div class="desc docblock-short">The test interval is 0.98us * 2<strong>interval, but let’s call it 1us * 2</strong>interval<br />
The default gives a test interval of 250us</div></li><li><div class="item-name"><a class="mod" href="fc0_max_khz/index.html" title="mod rp2040_pac::clocks::fc0_max_khz">fc0_<wbr>max_<wbr>khz</a></div><div class="desc docblock-short">Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</div></li><li><div class="item-name"><a class="mod" href="fc0_min_khz/index.html" title="mod rp2040_pac::clocks::fc0_min_khz">fc0_<wbr>min_<wbr>khz</a></div><div class="desc docblock-short">Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</div></li><li><div class="item-name"><a class="mod" href="fc0_ref_khz/index.html" title="mod rp2040_pac::clocks::fc0_ref_khz">fc0_<wbr>ref_<wbr>khz</a></div><div class="desc docblock-short">Reference clock frequency in kHz</div></li><li><div class="item-name"><a class="mod" href="fc0_result/index.html" title="mod rp2040_pac::clocks::fc0_result">fc0_<wbr>result</a></div><div class="desc docblock-short">Result of frequency measurement, only valid when status_done=1</div></li><li><div class="item-name"><a class="mod" href="fc0_src/index.html" title="mod rp2040_pac::clocks::fc0_src">fc0_src</a></div><div class="desc docblock-short">Clock sent to frequency counter, set to 0 when not required<br />
Writing to this register initiates the frequency count</div></li><li><div class="item-name"><a class="mod" href="fc0_status/index.html" title="mod rp2040_pac::clocks::fc0_status">fc0_<wbr>status</a></div><div class="desc docblock-short">Frequency counter status</div></li><li><div class="item-name"><a class="mod" href="inte/index.html" title="mod rp2040_pac::clocks::inte">inte</a></div><div class="desc docblock-short">Interrupt Enable</div></li><li><div class="item-name"><a class="mod" href="intf/index.html" title="mod rp2040_pac::clocks::intf">intf</a></div><div class="desc docblock-short">Interrupt Force</div></li><li><div class="item-name"><a class="mod" href="intr/index.html" title="mod rp2040_pac::clocks::intr">intr</a></div><div class="desc docblock-short">Raw Interrupts</div></li><li><div class="item-name"><a class="mod" href="ints/index.html" title="mod rp2040_pac::clocks::ints">ints</a></div><div class="desc docblock-short">Interrupt status after masking &amp; forcing</div></li><li><div class="item-name"><a class="mod" href="sleep_en0/index.html" title="mod rp2040_pac::clocks::sleep_en0">sleep_<wbr>en0</a></div><div class="desc docblock-short">enable clock in sleep mode</div></li><li><div class="item-name"><a class="mod" href="sleep_en1/index.html" title="mod rp2040_pac::clocks::sleep_en1">sleep_<wbr>en1</a></div><div class="desc docblock-short">enable clock in sleep mode</div></li><li><div class="item-name"><a class="mod" href="wake_en0/index.html" title="mod rp2040_pac::clocks::wake_en0">wake_<wbr>en0</a></div><div class="desc docblock-short">enable clock in wake mode</div></li><li><div class="item-name"><a class="mod" href="wake_en1/index.html" title="mod rp2040_pac::clocks::wake_en1">wake_<wbr>en1</a></div><div class="desc docblock-short">enable clock in wake mode</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::clocks::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.CLK_ADC_CTRL.html" title="type rp2040_pac::clocks::CLK_ADC_CTRL">CLK_<wbr>ADC_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_ADC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_ADC_DIV.html" title="type rp2040_pac::clocks::CLK_ADC_DIV">CLK_<wbr>ADC_<wbr>DIV</a></div><div class="desc docblock-short">CLK_ADC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_ADC_SELECTED.html" title="type rp2040_pac::clocks::CLK_ADC_SELECTED">CLK_<wbr>ADC_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_ADC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT0_CTRL.html" title="type rp2040_pac::clocks::CLK_GPOUT0_CTRL">CLK_<wbr>GPOU<wbr>T0_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_GPOUT0_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT0_DIV.html" title="type rp2040_pac::clocks::CLK_GPOUT0_DIV">CLK_<wbr>GPOU<wbr>T0_<wbr>DIV</a></div><div class="desc docblock-short">CLK_GPOUT0_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT0_SELECTED.html" title="type rp2040_pac::clocks::CLK_GPOUT0_SELECTED">CLK_<wbr>GPOU<wbr>T0_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_GPOUT0_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT1_CTRL.html" title="type rp2040_pac::clocks::CLK_GPOUT1_CTRL">CLK_<wbr>GPOU<wbr>T1_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_GPOUT1_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT1_DIV.html" title="type rp2040_pac::clocks::CLK_GPOUT1_DIV">CLK_<wbr>GPOU<wbr>T1_<wbr>DIV</a></div><div class="desc docblock-short">CLK_GPOUT1_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT1_SELECTED.html" title="type rp2040_pac::clocks::CLK_GPOUT1_SELECTED">CLK_<wbr>GPOU<wbr>T1_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_GPOUT1_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT2_CTRL.html" title="type rp2040_pac::clocks::CLK_GPOUT2_CTRL">CLK_<wbr>GPOU<wbr>T2_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_GPOUT2_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT2_DIV.html" title="type rp2040_pac::clocks::CLK_GPOUT2_DIV">CLK_<wbr>GPOU<wbr>T2_<wbr>DIV</a></div><div class="desc docblock-short">CLK_GPOUT2_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT2_SELECTED.html" title="type rp2040_pac::clocks::CLK_GPOUT2_SELECTED">CLK_<wbr>GPOU<wbr>T2_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_GPOUT2_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT3_CTRL.html" title="type rp2040_pac::clocks::CLK_GPOUT3_CTRL">CLK_<wbr>GPOU<wbr>T3_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_GPOUT3_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT3_DIV.html" title="type rp2040_pac::clocks::CLK_GPOUT3_DIV">CLK_<wbr>GPOU<wbr>T3_<wbr>DIV</a></div><div class="desc docblock-short">CLK_GPOUT3_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_GPOUT3_SELECTED.html" title="type rp2040_pac::clocks::CLK_GPOUT3_SELECTED">CLK_<wbr>GPOU<wbr>T3_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_GPOUT3_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="type" href="type.CLK_PERI_CTRL.html" title="type rp2040_pac::clocks::CLK_PERI_CTRL">CLK_<wbr>PERI_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_PERI_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_PERI_SELECTED.html" title="type rp2040_pac::clocks::CLK_PERI_SELECTED">CLK_<wbr>PERI_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_PERI_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="type" href="type.CLK_REF_CTRL.html" title="type rp2040_pac::clocks::CLK_REF_CTRL">CLK_<wbr>REF_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_REF_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_REF_DIV.html" title="type rp2040_pac::clocks::CLK_REF_DIV">CLK_<wbr>REF_<wbr>DIV</a></div><div class="desc docblock-short">CLK_REF_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_REF_SELECTED.html" title="type rp2040_pac::clocks::CLK_REF_SELECTED">CLK_<wbr>REF_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_REF_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</div></li><li><div class="item-name"><a class="type" href="type.CLK_RTC_CTRL.html" title="type rp2040_pac::clocks::CLK_RTC_CTRL">CLK_<wbr>RTC_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_RTC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_RTC_DIV.html" title="type rp2040_pac::clocks::CLK_RTC_DIV">CLK_<wbr>RTC_<wbr>DIV</a></div><div class="desc docblock-short">CLK_RTC_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_RTC_SELECTED.html" title="type rp2040_pac::clocks::CLK_RTC_SELECTED">CLK_<wbr>RTC_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_RTC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="type" href="type.CLK_SYS_CTRL.html" title="type rp2040_pac::clocks::CLK_SYS_CTRL">CLK_<wbr>SYS_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_SYS_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_SYS_DIV.html" title="type rp2040_pac::clocks::CLK_SYS_DIV">CLK_<wbr>SYS_<wbr>DIV</a></div><div class="desc docblock-short">CLK_SYS_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_SYS_RESUS_CTRL.html" title="type rp2040_pac::clocks::CLK_SYS_RESUS_CTRL">CLK_<wbr>SYS_<wbr>RESUS_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_SYS_RESUS_CTRL (rw) register accessor:</div></li><li><div class="item-name"><a class="type" href="type.CLK_SYS_RESUS_STATUS.html" title="type rp2040_pac::clocks::CLK_SYS_RESUS_STATUS">CLK_<wbr>SYS_<wbr>RESUS_<wbr>STATUS</a></div><div class="desc docblock-short">CLK_SYS_RESUS_STATUS (r) register accessor:</div></li><li><div class="item-name"><a class="type" href="type.CLK_SYS_SELECTED.html" title="type rp2040_pac::clocks::CLK_SYS_SELECTED">CLK_<wbr>SYS_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_SYS_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</div></li><li><div class="item-name"><a class="type" href="type.CLK_USB_CTRL.html" title="type rp2040_pac::clocks::CLK_USB_CTRL">CLK_<wbr>USB_<wbr>CTRL</a></div><div class="desc docblock-short">CLK_USB_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc)</div></li><li><div class="item-name"><a class="type" href="type.CLK_USB_DIV.html" title="type rp2040_pac::clocks::CLK_USB_DIV">CLK_<wbr>USB_<wbr>DIV</a></div><div class="desc docblock-short">CLK_USB_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly</div></li><li><div class="item-name"><a class="type" href="type.CLK_USB_SELECTED.html" title="type rp2040_pac::clocks::CLK_USB_SELECTED">CLK_<wbr>USB_<wbr>SELECTED</a></div><div class="desc docblock-short">CLK_USB_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot).<br />
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</div></li><li><div class="item-name"><a class="type" href="type.ENABLED0.html" title="type rp2040_pac::clocks::ENABLED0">ENABLE<wbr>D0</a></div><div class="desc docblock-short">ENABLED0 (r) register accessor: indicates the state of the clock enable</div></li><li><div class="item-name"><a class="type" href="type.ENABLED1.html" title="type rp2040_pac::clocks::ENABLED1">ENABLE<wbr>D1</a></div><div class="desc docblock-short">ENABLED1 (r) register accessor: indicates the state of the clock enable</div></li><li><div class="item-name"><a class="type" href="type.FC0_DELAY.html" title="type rp2040_pac::clocks::FC0_DELAY">FC0_<wbr>DELAY</a></div><div class="desc docblock-short">FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle<br />
Delay is measured in multiples of the reference clock period</div></li><li><div class="item-name"><a class="type" href="type.FC0_INTERVAL.html" title="type rp2040_pac::clocks::FC0_INTERVAL">FC0_<wbr>INTERVAL</a></div><div class="desc docblock-short">FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2<strong>interval, but let’s call it 1us * 2</strong>interval<br />
The default gives a test interval of 250us</div></li><li><div class="item-name"><a class="type" href="type.FC0_MAX_KHZ.html" title="type rp2040_pac::clocks::FC0_MAX_KHZ">FC0_<wbr>MAX_<wbr>KHZ</a></div><div class="desc docblock-short">FC0_MAX_KHZ (rw) register accessor: Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</div></li><li><div class="item-name"><a class="type" href="type.FC0_MIN_KHZ.html" title="type rp2040_pac::clocks::FC0_MIN_KHZ">FC0_<wbr>MIN_<wbr>KHZ</a></div><div class="desc docblock-short">FC0_MIN_KHZ (rw) register accessor: Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</div></li><li><div class="item-name"><a class="type" href="type.FC0_REF_KHZ.html" title="type rp2040_pac::clocks::FC0_REF_KHZ">FC0_<wbr>REF_<wbr>KHZ</a></div><div class="desc docblock-short">FC0_REF_KHZ (rw) register accessor: Reference clock frequency in kHz</div></li><li><div class="item-name"><a class="type" href="type.FC0_RESULT.html" title="type rp2040_pac::clocks::FC0_RESULT">FC0_<wbr>RESULT</a></div><div class="desc docblock-short">FC0_RESULT (r) register accessor: Result of frequency measurement, only valid when status_done=1</div></li><li><div class="item-name"><a class="type" href="type.FC0_SRC.html" title="type rp2040_pac::clocks::FC0_SRC">FC0_SRC</a></div><div class="desc docblock-short">FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required<br />
Writing to this register initiates the frequency count</div></li><li><div class="item-name"><a class="type" href="type.FC0_STATUS.html" title="type rp2040_pac::clocks::FC0_STATUS">FC0_<wbr>STATUS</a></div><div class="desc docblock-short">FC0_STATUS (r) register accessor: Frequency counter status</div></li><li><div class="item-name"><a class="type" href="type.INTE.html" title="type rp2040_pac::clocks::INTE">INTE</a></div><div class="desc docblock-short">INTE (rw) register accessor: Interrupt Enable</div></li><li><div class="item-name"><a class="type" href="type.INTF.html" title="type rp2040_pac::clocks::INTF">INTF</a></div><div class="desc docblock-short">INTF (rw) register accessor: Interrupt Force</div></li><li><div class="item-name"><a class="type" href="type.INTR.html" title="type rp2040_pac::clocks::INTR">INTR</a></div><div class="desc docblock-short">INTR (r) register accessor: Raw Interrupts</div></li><li><div class="item-name"><a class="type" href="type.INTS.html" title="type rp2040_pac::clocks::INTS">INTS</a></div><div class="desc docblock-short">INTS (r) register accessor: Interrupt status after masking &amp; forcing</div></li><li><div class="item-name"><a class="type" href="type.SLEEP_EN0.html" title="type rp2040_pac::clocks::SLEEP_EN0">SLEEP_<wbr>EN0</a></div><div class="desc docblock-short">SLEEP_EN0 (rw) register accessor: enable clock in sleep mode</div></li><li><div class="item-name"><a class="type" href="type.SLEEP_EN1.html" title="type rp2040_pac::clocks::SLEEP_EN1">SLEEP_<wbr>EN1</a></div><div class="desc docblock-short">SLEEP_EN1 (rw) register accessor: enable clock in sleep mode</div></li><li><div class="item-name"><a class="type" href="type.WAKE_EN0.html" title="type rp2040_pac::clocks::WAKE_EN0">WAKE_<wbr>EN0</a></div><div class="desc docblock-short">WAKE_EN0 (rw) register accessor: enable clock in wake mode</div></li><li><div class="item-name"><a class="type" href="type.WAKE_EN1.html" title="type rp2040_pac::clocks::WAKE_EN1">WAKE_<wbr>EN1</a></div><div class="desc docblock-short">WAKE_EN1 (rw) register accessor: enable clock in wake mode</div></li></ul></section></div></main></body></html>
Reference in a new issue View git blame Copy permalink